[deliverable/linux.git] / arch / arm / mach-omap2 / io.c

/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
 *
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <asm/tlb.h>
#include <asm/mach/map.h>

#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/serial.h>
#include <plat/omap-pm.h>
#include <plat/omap_hwmod.h>
#include <plat/multi.h>

#include "iomap.h"
#include "voltage.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "common.h"
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "clock44xx.h"

/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */

#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#ifdef CONFIG_SOC_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
	{
		.virtual	= DSP_MEM_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_2420_PHYS),
		.length		= DSP_MEM_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_IPI_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_2420_PHYS),
		.length		= DSP_IPI_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_MMU_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_2420_PHYS),
		.length		= DSP_MMU_2420_SIZE,
		.type		= MT_DEVICE
	},
};

#endif

#ifdef CONFIG_SOC_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#endif

#ifdef	CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
	{
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
#if defined(CONFIG_DEBUG_LL) &&							\
	(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
	{
		.virtual	= ZOOM_UART_VIRT,
		.pfn		= __phys_to_pfn(ZOOM_UART_BASE),
		.length		= SZ_1M,
		.type		= MT_DEVICE
	},
#endif
};
#endif

#ifdef CONFIG_SOC_OMAPTI81XX
static struct map_desc omapti81xx_io_desc[] __initdata = {
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	}
};
#endif

#ifdef CONFIG_SOC_OMAPAM33XX
static struct map_desc omapam33xx_io_desc[] __initdata = {
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_WK_AM33XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
		.length		= L4_WK_AM33XX_SIZE,
		.type		= MT_DEVICE
	}
};
#endif

#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_GPMC_PHYS),
		.length		= OMAP44XX_GPMC_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_EMIF1_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
		.length		= OMAP44XX_EMIF1_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_EMIF2_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
		.length		= OMAP44XX_EMIF2_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_DMM_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_DMM_PHYS),
		.length		= OMAP44XX_DMM_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_EMU_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_44XX_PHYS),
		.length		= L4_EMU_44XX_SIZE,
		.type		= MT_DEVICE,
	},
#ifdef CONFIG_OMAP4_ERRATA_I688
	{
		.virtual	= OMAP4_SRAM_VA,
		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
		.length		= PAGE_SIZE,
		.type		= MT_MEMORY_SO,
	},
#endif

};
#endif

#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
}
#endif

#ifdef CONFIG_SOC_OMAP2430
void __init omap243x_map_common_io(void)
{
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
}
#endif

#ifdef CONFIG_ARCH_OMAP3
void __init omap34xx_map_common_io(void)
{
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
}
#endif

#ifdef CONFIG_SOC_OMAPTI81XX
void __init omapti81xx_map_common_io(void)
{
	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
}
#endif

#ifdef CONFIG_SOC_OMAPAM33XX
void __init omapam33xx_map_common_io(void)
{
	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	omap_barriers_init();
}
#endif

/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (IS_ERR(dpll3_m2_ck))
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}

static void __init omap_common_init_early(void)
{
	omap_init_consistent_dma_size();
}

static void __init omap_hwmod_init_postsetup(void)
{
	u8 postsetup_state;

	/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM_RUNTIME
	postsetup_state = _HWMOD_STATE_IDLE;
#else
	postsetup_state = _HWMOD_STATE_ENABLED;
#endif
	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);

	/*
	 * Set the default postsetup state for unusual modules (like
	 * MPU WDT).
	 *
	 * The postsetup_state is not actually used until
	 * omap_hwmod_late_init(), so boards that desire full watchdog
	 * coverage of kernel initialization can reprogram the
	 * postsetup_state between the calls to
	 * omap2_init_common_infra() and omap_sdrc_init().
	 *
	 * XXX ideally we could detect whether the MPU WDT was currently
	 * enabled here and make this conditional
	 */
	postsetup_state = _HWMOD_STATE_DISABLED;
	omap_hwmod_for_each_by_class("wd_timer",
				     _set_hwmod_postsetup_state,
				     &postsetup_state);

	omap_pm_if_early_init();
}

#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
	omap2_set_globals_242x();
	omap2xxx_check_revision();
	omap_common_init_early();
	omap2xxx_voltagedomains_init();
	omap242x_powerdomains_init();
	omap242x_clockdomains_init();
	omap2420_hwmod_init();
	omap_hwmod_init_postsetup();
	omap2420_clk_init();
}
#endif

#ifdef CONFIG_SOC_OMAP2430
void __init omap2430_init_early(void)
{
	omap2_set_globals_243x();
	omap2xxx_check_revision();
	omap_common_init_early();
	omap2xxx_voltagedomains_init();
	omap243x_powerdomains_init();
	omap243x_clockdomains_init();
	omap2430_hwmod_init();
	omap_hwmod_init_postsetup();
	omap2430_clk_init();
}
#endif

/*
 * Currently only board-omap3beagle.c should call this because of the
 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 */
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
{
	omap2_set_globals_3xxx();
	omap3xxx_check_revision();
	omap3xxx_check_features();
	omap_common_init_early();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap3xxx_clk_init();
}

void __init omap3430_init_early(void)
{
	omap3_init_early();
}

void __init omap35xx_init_early(void)
{
	omap3_init_early();
}

void __init omap3630_init_early(void)
{
	omap3_init_early();
}

void __init am35xx_init_early(void)
{
	omap3_init_early();
}

void __init ti81xx_init_early(void)
{
	omap2_set_globals_ti81xx();
	omap3xxx_check_revision();
	ti81xx_check_features();
	omap_common_init_early();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap3xxx_clk_init();
}
#endif

#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
	omap2_set_globals_443x();
	omap4xxx_check_revision();
	omap4xxx_check_features();
	omap_common_init_early();
	omap44xx_voltagedomains_init();
	omap44xx_powerdomains_init();
	omap44xx_clockdomains_init();
	omap44xx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap4xxx_clk_init();
}
#endif

void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
				      struct omap_sdrc_params *sdrc_cs1)
{
	omap_sram_init();

	if (cpu_is_omap24xx() || omap3_has_sdrc()) {
		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
		_omap2_init_reprogram_sdrc();
	}
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/io.c
	3	*
	4	* OMAP2 I/O mapping code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
44169075	7	* Copyright (C) 2007-2009 Texas Instruments
646e3ed1 TL	8	*
	9	* Author:
	10	* Juha Yrjola <juha.yrjola@nokia.com>
	11	* Syed Khasim <x0khasim@ti.com>
1dbae815	12	*
44169075 SS	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075 SS	14	*
1dbae815 TL	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
1dbae815 TL	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
fced80c7	22	#include <linux/io.h>
2f135eaf	23	#include <linux/clk.h>
1dbae815	24
120db2cb	25	#include <asm/tlb.h>
120db2cb TL	26	#include <asm/mach/map.h>
120db2cb TL	27
ce491cf8 TL	28	#include <plat/sram.h>
ce491cf8 TL	29	#include <plat/sdrc.h>
ce491cf8	30	#include <plat/serial.h>
ce491cf8	31	#include <plat/omap-pm.h>
ee0839c2 TL	32	#include <plat/omap_hwmod.h>
	33	#include <plat/multi.h>
	34
	35	#include "iomap.h"
81a60482	36	#include "voltage.h"
72e06d08	37	#include "powerdomain.h"
1540f214	38	#include "clockdomain.h"
4e65331c	39	#include "common.h"
ee0839c2 TL	40	#include "clock2xxx.h"
	41	#include "clock3xxx.h"
	42	#include "clock44xx.h"
02bfc030	43
1dbae815 TL	44	/*
	45	* The machine specific code may provide the extra mapping besides the
	46	* default mapping provided here.
	47	*/
cc26b3b0	48
e48f814e	49	#if defined(CONFIG_SOC_OMAP2420) \|\| defined(CONFIG_SOC_OMAP2430)
cc26b3b0	50	static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815 TL	51	{
	52	.virtual = L3_24XX_VIRT,
	53	.pfn = __phys_to_pfn(L3_24XX_PHYS),
	54	.length = L3_24XX_SIZE,
	55	.type = MT_DEVICE
	56	},
09f21ed4	57	{
cc26b3b0 SMK	58	.virtual = L4_24XX_VIRT,
	59	.pfn = __phys_to_pfn(L4_24XX_PHYS),
	60	.length = L4_24XX_SIZE,
	61	.type = MT_DEVICE
09f21ed4	62	},
cc26b3b0 SMK	63	};
cc26b3b0 SMK	64
59b479e0	65	#ifdef CONFIG_SOC_OMAP2420
cc26b3b0 SMK	66	static struct map_desc omap242x_io_desc[] __initdata = {
cc26b3b0 SMK	67	{
7adb9987 PW	68	.virtual = DSP_MEM_2420_VIRT,
	69	.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
	70	.length = DSP_MEM_2420_SIZE,
cc26b3b0 SMK	71	.type = MT_DEVICE
	72	},
	73	{
7adb9987 PW	74	.virtual = DSP_IPI_2420_VIRT,
	75	.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
	76	.length = DSP_IPI_2420_SIZE,
cc26b3b0	77	.type = MT_DEVICE
09f21ed4	78	},
cc26b3b0	79	{
7adb9987 PW	80	.virtual = DSP_MMU_2420_VIRT,
	81	.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
	82	.length = DSP_MMU_2420_SIZE,
cc26b3b0 SMK	83	.type = MT_DEVICE
	84	},
	85	};
	86
	87	#endif
	88
59b479e0	89	#ifdef CONFIG_SOC_OMAP2430
cc26b3b0	90	static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3 SMK	91	{
	92	.virtual = L4_WK_243X_VIRT,
	93	.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
	94	.length = L4_WK_243X_SIZE,
	95	.type = MT_DEVICE
	96	},
	97	{
	98	.virtual = OMAP243X_GPMC_VIRT,
	99	.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
	100	.length = OMAP243X_GPMC_SIZE,
	101	.type = MT_DEVICE
	102	},
cc26b3b0 SMK	103	{
	104	.virtual = OMAP243X_SDRC_VIRT,
	105	.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
	106	.length = OMAP243X_SDRC_SIZE,
	107	.type = MT_DEVICE
	108	},
	109	{
	110	.virtual = OMAP243X_SMS_VIRT,
	111	.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
	112	.length = OMAP243X_SMS_SIZE,
	113	.type = MT_DEVICE
	114	},
	115	};
72d0f1c3	116	#endif
72d0f1c3	117	#endif
cc26b3b0	118
a8eb7ca0	119	#ifdef CONFIG_ARCH_OMAP3
cc26b3b0	120	static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815	121	{
cc26b3b0 SMK	122	.virtual = L3_34XX_VIRT,
	123	.pfn = __phys_to_pfn(L3_34XX_PHYS),
	124	.length = L3_34XX_SIZE,
c40fae95 TL	125	.type = MT_DEVICE
	126	},
	127	{
cc26b3b0 SMK	128	.virtual = L4_34XX_VIRT,
	129	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	130	.length = L4_34XX_SIZE,
c40fae95 TL	131	.type = MT_DEVICE
c40fae95 TL	132	},
cc26b3b0 SMK	133	{
	134	.virtual = OMAP34XX_GPMC_VIRT,
	135	.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
	136	.length = OMAP34XX_GPMC_SIZE,
1dbae815	137	.type = MT_DEVICE
cc26b3b0 SMK	138	},
	139	{
	140	.virtual = OMAP343X_SMS_VIRT,
	141	.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
	142	.length = OMAP343X_SMS_SIZE,
	143	.type = MT_DEVICE
	144	},
	145	{
	146	.virtual = OMAP343X_SDRC_VIRT,
	147	.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
	148	.length = OMAP343X_SDRC_SIZE,
1dbae815	149	.type = MT_DEVICE
cc26b3b0 SMK	150	},
	151	{
	152	.virtual = L4_PER_34XX_VIRT,
	153	.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
	154	.length = L4_PER_34XX_SIZE,
	155	.type = MT_DEVICE
	156	},
	157	{
	158	.virtual = L4_EMU_34XX_VIRT,
	159	.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
	160	.length = L4_EMU_34XX_SIZE,
	161	.type = MT_DEVICE
	162	},
a4f57b81 TL	163	#if defined(CONFIG_DEBUG_LL) && \
	164	(defined(CONFIG_MACH_OMAP_ZOOM2) \|\| defined(CONFIG_MACH_OMAP_ZOOM3))
	165	{
	166	.virtual = ZOOM_UART_VIRT,
	167	.pfn = __phys_to_pfn(ZOOM_UART_BASE),
	168	.length = SZ_1M,
	169	.type = MT_DEVICE
	170	},
	171	#endif
1dbae815	172	};
cc26b3b0	173	#endif
01001712	174
a920360f HP	175	#ifdef CONFIG_SOC_OMAPTI81XX
a920360f HP	176	static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146 AM	177	{
	178	.virtual = L4_34XX_VIRT,
	179	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	180	.length = L4_34XX_SIZE,
	181	.type = MT_DEVICE
	182	}
	183	};
	184	#endif
	185
	186	#ifdef CONFIG_SOC_OMAPAM33XX
	187	static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712 HP	188	{
	189	.virtual = L4_34XX_VIRT,
	190	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	191	.length = L4_34XX_SIZE,
	192	.type = MT_DEVICE
	193	},
1e6cb146 AM	194	{
	195	.virtual = L4_WK_AM33XX_VIRT,
	196	.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
	197	.length = L4_WK_AM33XX_SIZE,
	198	.type = MT_DEVICE
	199	}
01001712 HP	200	};
	201	#endif
	202
44169075 SS	203	#ifdef CONFIG_ARCH_OMAP4
	204	static struct map_desc omap44xx_io_desc[] __initdata = {
	205	{
	206	.virtual = L3_44XX_VIRT,
	207	.pfn = __phys_to_pfn(L3_44XX_PHYS),
	208	.length = L3_44XX_SIZE,
	209	.type = MT_DEVICE,
	210	},
	211	{
	212	.virtual = L4_44XX_VIRT,
	213	.pfn = __phys_to_pfn(L4_44XX_PHYS),
	214	.length = L4_44XX_SIZE,
	215	.type = MT_DEVICE,
	216	},
44169075 SS	217	{
	218	.virtual = OMAP44XX_GPMC_VIRT,
	219	.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
	220	.length = OMAP44XX_GPMC_SIZE,
	221	.type = MT_DEVICE,
	222	},
f5d2d659 SS	223	{
	224	.virtual = OMAP44XX_EMIF1_VIRT,
	225	.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
	226	.length = OMAP44XX_EMIF1_SIZE,
	227	.type = MT_DEVICE,
	228	},
	229	{
	230	.virtual = OMAP44XX_EMIF2_VIRT,
	231	.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
	232	.length = OMAP44XX_EMIF2_SIZE,
	233	.type = MT_DEVICE,
	234	},
	235	{
	236	.virtual = OMAP44XX_DMM_VIRT,
	237	.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
	238	.length = OMAP44XX_DMM_SIZE,
	239	.type = MT_DEVICE,
	240	},
44169075 SS	241	{
	242	.virtual = L4_PER_44XX_VIRT,
	243	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
	244	.length = L4_PER_44XX_SIZE,
	245	.type = MT_DEVICE,
	246	},
	247	{
	248	.virtual = L4_EMU_44XX_VIRT,
	249	.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
	250	.length = L4_EMU_44XX_SIZE,
	251	.type = MT_DEVICE,
	252	},
137d105d SS	253	#ifdef CONFIG_OMAP4_ERRATA_I688
	254	{
	255	.virtual = OMAP4_SRAM_VA,
	256	.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
	257	.length = PAGE_SIZE,
	258	.type = MT_MEMORY_SO,
	259	},
	260	#endif
	261
44169075 SS	262	};
44169075 SS	263	#endif
1dbae815	264
59b479e0	265	#ifdef CONFIG_SOC_OMAP2420
8185e468	266	void __init omap242x_map_common_io(void)
1dbae815	267	{
cc26b3b0 SMK	268	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
cc26b3b0 SMK	269	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0	270	}
cc26b3b0 SMK	271	#endif
cc26b3b0 SMK	272
59b479e0	273	#ifdef CONFIG_SOC_OMAP2430
8185e468	274	void __init omap243x_map_common_io(void)
6fbd55d0	275	{
cc26b3b0 SMK	276	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
cc26b3b0 SMK	277	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0	278	}
cc26b3b0 SMK	279	#endif
cc26b3b0 SMK	280
a8eb7ca0	281	#ifdef CONFIG_ARCH_OMAP3
8185e468	282	void __init omap34xx_map_common_io(void)
6fbd55d0	283	{
cc26b3b0	284	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0	285	}
cc26b3b0	286	#endif
120db2cb	287
a920360f HP	288	#ifdef CONFIG_SOC_OMAPTI81XX
a920360f HP	289	void __init omapti81xx_map_common_io(void)
01001712	290	{
a920360f	291	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712 HP	292	}
	293	#endif
	294
1e6cb146 AM	295	#ifdef CONFIG_SOC_OMAPAM33XX
1e6cb146 AM	296	void __init omapam33xx_map_common_io(void)
01001712	297	{
1e6cb146	298	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712 HP	299	}
	300	#endif
	301
6fbd55d0	302	#ifdef CONFIG_ARCH_OMAP4
8185e468	303	void __init omap44xx_map_common_io(void)
6fbd55d0	304	{
44169075	305	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e	306	omap_barriers_init();
120db2cb	307	}
6fbd55d0	308	#endif
120db2cb	309
2f135eaf PW	310	/*
	311	* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
	312	*
	313	* Sets the CORE DPLL3 M2 divider to the same value that it's at
	314	* currently. This has the effect of setting the SDRC SDRAM AC timing
	315	* registers to the values currently defined by the kernel. Currently
	316	* only defined for OMAP3; will return 0 if called on OMAP2. Returns
	317	* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
	318	* or passes along the return value of clk_set_rate().
	319	*/
	320	static int __init _omap2_init_reprogram_sdrc(void)
	321	{
	322	struct clk *dpll3_m2_ck;
	323	int v = -EINVAL;
	324	long rate;
	325
	326	if (!cpu_is_omap34xx())
	327	return 0;
	328
	329	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec	330	if (IS_ERR(dpll3_m2_ck))
2f135eaf PW	331	return -EINVAL;
	332
	333	rate = clk_get_rate(dpll3_m2_ck);
	334	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	335	v = clk_set_rate(dpll3_m2_ck, rate);
	336	if (v)
	337	pr_err("dpll3_m2_clk rate change failed: %d\n", v);
	338
	339	clk_put(dpll3_m2_ck);
	340
	341	return v;
	342	}
	343
2092e5cc PW	344	static int _set_hwmod_postsetup_state(struct omap_hwmod oh, void data)
	345	{
	346	return omap_hwmod_set_postsetup_state(oh, (u8 )data);
	347	}
	348
7b250aff	349	static void __init omap_common_init_early(void)
120db2cb	350	{
df80442d	351	omap_init_consistent_dma_size();
7b250aff	352	}
2092e5cc	353
7b250aff TL	354	static void __init omap_hwmod_init_postsetup(void)
	355	{
	356	u8 postsetup_state;
2092e5cc PW	357
	358	/* Set the default postsetup state for all hwmods */
	359	#ifdef CONFIG_PM_RUNTIME
	360	postsetup_state = _HWMOD_STATE_IDLE;
	361	#else
	362	postsetup_state = _HWMOD_STATE_ENABLED;
	363	#endif
	364	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08	365
ff2516fb PW	366	/*
	367	* Set the default postsetup state for unusual modules (like
	368	* MPU WDT).
	369	*
	370	* The postsetup_state is not actually used until
	371	* omap_hwmod_late_init(), so boards that desire full watchdog
	372	* coverage of kernel initialization can reprogram the
	373	* postsetup_state between the calls to
a4ca9dbe	374	* omap2_init_common_infra() and omap_sdrc_init().
ff2516fb PW	375	*
	376	* XXX ideally we could detect whether the MPU WDT was currently
	377	* enabled here and make this conditional
	378	*/
	379	postsetup_state = _HWMOD_STATE_DISABLED;
	380	omap_hwmod_for_each_by_class("wd_timer",
	381	_set_hwmod_postsetup_state,
	382	&postsetup_state);
	383
53da4ce2	384	omap_pm_if_early_init();
4805734b PW	385	}
4805734b PW	386
16110798	387	#ifdef CONFIG_SOC_OMAP2420
8f5b5a41 TL	388	void __init omap2420_init_early(void)
8f5b5a41 TL	389	{
4c3cf901	390	omap2_set_globals_242x();
4de34f35	391	omap2xxx_check_revision();
7b250aff TL	392	omap_common_init_early();
	393	omap2xxx_voltagedomains_init();
	394	omap242x_powerdomains_init();
	395	omap242x_clockdomains_init();
	396	omap2420_hwmod_init();
	397	omap_hwmod_init_postsetup();
	398	omap2420_clk_init();
8f5b5a41	399	}
16110798	400	#endif
8f5b5a41	401
16110798	402	#ifdef CONFIG_SOC_OMAP2430
8f5b5a41 TL	403	void __init omap2430_init_early(void)
8f5b5a41 TL	404	{
4c3cf901	405	omap2_set_globals_243x();
4de34f35	406	omap2xxx_check_revision();
7b250aff TL	407	omap_common_init_early();
	408	omap2xxx_voltagedomains_init();
	409	omap243x_powerdomains_init();
	410	omap243x_clockdomains_init();
	411	omap2430_hwmod_init();
	412	omap_hwmod_init_postsetup();
	413	omap2430_clk_init();
	414	}
c4e2d245	415	#endif
7b250aff TL	416
	417	/*
	418	* Currently only board-omap3beagle.c should call this because of the
	419	* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
	420	*/
c4e2d245	421	#ifdef CONFIG_ARCH_OMAP3
7b250aff TL	422	void __init omap3_init_early(void)
7b250aff TL	423	{
4c3cf901	424	omap2_set_globals_3xxx();
4de34f35 VH	425	omap3xxx_check_revision();
4de34f35 VH	426	omap3xxx_check_features();
7b250aff TL	427	omap_common_init_early();
	428	omap3xxx_voltagedomains_init();
	429	omap3xxx_powerdomains_init();
	430	omap3xxx_clockdomains_init();
	431	omap3xxx_hwmod_init();
	432	omap_hwmod_init_postsetup();
	433	omap3xxx_clk_init();
8f5b5a41 TL	434	}
	435
	436	void __init omap3430_init_early(void)
	437	{
7b250aff	438	omap3_init_early();
8f5b5a41 TL	439	}
	440
	441	void __init omap35xx_init_early(void)
	442	{
7b250aff	443	omap3_init_early();
8f5b5a41 TL	444	}
	445
	446	void __init omap3630_init_early(void)
	447	{
7b250aff	448	omap3_init_early();
8f5b5a41 TL	449	}
	450
	451	void __init am35xx_init_early(void)
	452	{
7b250aff	453	omap3_init_early();
8f5b5a41 TL	454	}
8f5b5a41 TL	455
a920360f	456	void __init ti81xx_init_early(void)
8f5b5a41	457	{
a920360f	458	omap2_set_globals_ti81xx();
4de34f35 VH	459	omap3xxx_check_revision();
4de34f35 VH	460	ti81xx_check_features();
4c3cf901 TL	461	omap_common_init_early();
	462	omap3xxx_voltagedomains_init();
	463	omap3xxx_powerdomains_init();
	464	omap3xxx_clockdomains_init();
	465	omap3xxx_hwmod_init();
	466	omap_hwmod_init_postsetup();
	467	omap3xxx_clk_init();
8f5b5a41	468	}
c4e2d245	469	#endif
8f5b5a41	470
c4e2d245	471	#ifdef CONFIG_ARCH_OMAP4
8f5b5a41 TL	472	void __init omap4430_init_early(void)
8f5b5a41 TL	473	{
4c3cf901	474	omap2_set_globals_443x();
4de34f35 VH	475	omap4xxx_check_revision();
4de34f35 VH	476	omap4xxx_check_features();
7b250aff TL	477	omap_common_init_early();
	478	omap44xx_voltagedomains_init();
	479	omap44xx_powerdomains_init();
	480	omap44xx_clockdomains_init();
	481	omap44xx_hwmod_init();
	482	omap_hwmod_init_postsetup();
	483	omap4xxx_clk_init();
8f5b5a41	484	}
c4e2d245	485	#endif
8f5b5a41	486
a4ca9dbe	487	void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b PW	488	struct omap_sdrc_params *sdrc_cs1)
4805734b PW	489	{
a66cb345 TL	490	omap_sram_init();
a66cb345 TL	491
01001712	492	if (cpu_is_omap24xx() \|\| omap3_has_sdrc()) {
aa4b1f6e KH	493	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
	494	_omap2_init_reprogram_sdrc();
	495	}
1dbae815	496	}