projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAP: hwmod: allow omap_hwmod_late_init() caller to skip module idle in _setup()
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
1dbae815
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
2f135eaf 24#include <linux/clk.h>
91773a00 25#include <linux/omapfb.h>
1dbae815 26
120db2cb 27#include <asm/tlb.h>
120db2cb
TL		 28
29#include <asm/mach/map.h>
30
ce491cf8 31#include <plat/mux.h>
ce491cf8
TL		 32#include <plat/sram.h>
33#include <plat/sdrc.h>
34#include <plat/gpmc.h>
35#include <plat/serial.h>
afedec18 36#include <plat/vram.h>
646e3ed1 37
e80a9729 38#include "clock2xxx.h"
657ebfad 39#include "clock3xxx.h"
e80a9729 40#include "clock44xx.h"
1dbae815 41
ce491cf8
TL		 42#include <plat/omap-pm.h>
43#include <plat/powerdomain.h>
9717100f 44#include "powerdomains.h"
1dbae815 45
ce491cf8 46#include <plat/clockdomain.h>
801954d3 47#include "clockdomains.h"
ce491cf8 48#include <plat/omap_hwmod.h>
02bfc030 49
1dbae815
TL		 50/*
51 * The machine specific code may provide the extra mapping besides the
52 * default mapping provided here.
53 */
cc26b3b0 54
088ef950 55#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 56static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 57 {
58 .virtual = L3_24XX_VIRT,
59 .pfn = __phys_to_pfn(L3_24XX_PHYS),
60 .length = L3_24XX_SIZE,
61 .type = MT_DEVICE
62 },
09f21ed4 63 {
cc26b3b0
SMK		 64 .virtual = L4_24XX_VIRT,
65 .pfn = __phys_to_pfn(L4_24XX_PHYS),
66 .length = L4_24XX_SIZE,
67 .type = MT_DEVICE
09f21ed4 68 },
cc26b3b0
SMK		 69};
70
71#ifdef CONFIG_ARCH_OMAP2420
72static struct map_desc omap242x_io_desc[] __initdata = {
73 {
7adb9987
PW		 74 .virtual = DSP_MEM_2420_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
76 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 77 .type = MT_DEVICE
78 },
79 {
7adb9987
PW		 80 .virtual = DSP_IPI_2420_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
82 .length = DSP_IPI_2420_SIZE,
cc26b3b0 83 .type = MT_DEVICE
09f21ed4 84 },
cc26b3b0 85 {
7adb9987
PW		 86 .virtual = DSP_MMU_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
88 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 89 .type = MT_DEVICE
90 },
91};
92
93#endif
94
72d0f1c3 95#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0 96static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 97 {
98 .virtual = L4_WK_243X_VIRT,
99 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
100 .length = L4_WK_243X_SIZE,
101 .type = MT_DEVICE
102 },
103 {
104 .virtual = OMAP243X_GPMC_VIRT,
105 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
106 .length = OMAP243X_GPMC_SIZE,
107 .type = MT_DEVICE
108 },
cc26b3b0
SMK		 109 {
110 .virtual = OMAP243X_SDRC_VIRT,
111 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
112 .length = OMAP243X_SDRC_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_SMS_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
118 .length = OMAP243X_SMS_SIZE,
119 .type = MT_DEVICE
120 },
121};
72d0f1c3 122#endif
72d0f1c3 123#endif
cc26b3b0 124
a8eb7ca0 125#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 126static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 127 {
cc26b3b0
SMK		 128 .virtual = L3_34XX_VIRT,
129 .pfn = __phys_to_pfn(L3_34XX_PHYS),
130 .length = L3_34XX_SIZE,
c40fae95
TL		 131 .type = MT_DEVICE
132 },
133 {
cc26b3b0
SMK		 134 .virtual = L4_34XX_VIRT,
135 .pfn = __phys_to_pfn(L4_34XX_PHYS),
136 .length = L4_34XX_SIZE,
c40fae95
TL		 137 .type = MT_DEVICE
138 },
cc26b3b0
SMK		 139 {
140 .virtual = OMAP34XX_GPMC_VIRT,
141 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
142 .length = OMAP34XX_GPMC_SIZE,
1dbae815 143 .type = MT_DEVICE
cc26b3b0
SMK		 144 },
145 {
146 .virtual = OMAP343X_SMS_VIRT,
147 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
148 .length = OMAP343X_SMS_SIZE,
149 .type = MT_DEVICE
150 },
151 {
152 .virtual = OMAP343X_SDRC_VIRT,
153 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
154 .length = OMAP343X_SDRC_SIZE,
1dbae815 155 .type = MT_DEVICE
cc26b3b0
SMK		 156 },
157 {
158 .virtual = L4_PER_34XX_VIRT,
159 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
160 .length = L4_PER_34XX_SIZE,
161 .type = MT_DEVICE
162 },
163 {
164 .virtual = L4_EMU_34XX_VIRT,
165 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
166 .length = L4_EMU_34XX_SIZE,
167 .type = MT_DEVICE
168 },
a4f57b81
TL		 169#if defined(CONFIG_DEBUG_LL) && \
170 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
171 {
172 .virtual = ZOOM_UART_VIRT,
173 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
174 .length = SZ_1M,
175 .type = MT_DEVICE
176 },
177#endif
1dbae815 178};
cc26b3b0 179#endif
44169075
SS		 180#ifdef CONFIG_ARCH_OMAP4
181static struct map_desc omap44xx_io_desc[] __initdata = {
182 {
183 .virtual = L3_44XX_VIRT,
184 .pfn = __phys_to_pfn(L3_44XX_PHYS),
185 .length = L3_44XX_SIZE,
186 .type = MT_DEVICE,
187 },
188 {
189 .virtual = L4_44XX_VIRT,
190 .pfn = __phys_to_pfn(L4_44XX_PHYS),
191 .length = L4_44XX_SIZE,
192 .type = MT_DEVICE,
193 },
44169075
SS		 194 {
195 .virtual = OMAP44XX_GPMC_VIRT,
196 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
197 .length = OMAP44XX_GPMC_SIZE,
198 .type = MT_DEVICE,
199 },
f5d2d659
SS		 200 {
201 .virtual = OMAP44XX_EMIF1_VIRT,
202 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
203 .length = OMAP44XX_EMIF1_SIZE,
204 .type = MT_DEVICE,
205 },
206 {
207 .virtual = OMAP44XX_EMIF2_VIRT,
208 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
209 .length = OMAP44XX_EMIF2_SIZE,
210 .type = MT_DEVICE,
211 },
212 {
213 .virtual = OMAP44XX_DMM_VIRT,
214 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
215 .length = OMAP44XX_DMM_SIZE,
216 .type = MT_DEVICE,
217 },
44169075
SS		 218 {
219 .virtual = L4_PER_44XX_VIRT,
220 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
221 .length = L4_PER_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
224 {
225 .virtual = L4_EMU_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
227 .length = L4_EMU_44XX_SIZE,
228 .type = MT_DEVICE,
229 },
230};
231#endif
1dbae815 232
6fbd55d0
TL		 233static void __init _omap2_map_common_io(void)
234{
235 /* Normally devicemaps_init() would flush caches and tlb after
236 * mdesc->map_io(), but we must also do it here because of the CPU
237 * revision check below.
238 */
239 local_flush_tlb_all();
240 flush_cache_all();
241
242 omap2_check_revision();
243 omap_sram_init();
244 omapfb_reserve_sdram();
245 omap_vram_reserve_sdram();
246}
247
248#ifdef CONFIG_ARCH_OMAP2420
8185e468 249void __init omap242x_map_common_io(void)
1dbae815 250{
cc26b3b0
SMK		 251 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
252 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0
TL		 253 _omap2_map_common_io();
254}
cc26b3b0
SMK		 255#endif
256
6fbd55d0 257#ifdef CONFIG_ARCH_OMAP2430
8185e468 258void __init omap243x_map_common_io(void)
6fbd55d0 259{
cc26b3b0
SMK		 260 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
261 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0
TL		 262 _omap2_map_common_io();
263}
cc26b3b0
SMK		 264#endif
265
a8eb7ca0 266#ifdef CONFIG_ARCH_OMAP3
8185e468 267void __init omap34xx_map_common_io(void)
6fbd55d0 268{
cc26b3b0 269 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0
TL		 270 _omap2_map_common_io();
271}
cc26b3b0 272#endif
120db2cb 273
6fbd55d0 274#ifdef CONFIG_ARCH_OMAP4
8185e468 275void __init omap44xx_map_common_io(void)
6fbd55d0 276{
44169075 277 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
6fbd55d0 278 _omap2_map_common_io();
120db2cb 279}
6fbd55d0 280#endif
120db2cb 281
2f135eaf
PW		 282/*
283 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
284 *
285 * Sets the CORE DPLL3 M2 divider to the same value that it's at
286 * currently. This has the effect of setting the SDRC SDRAM AC timing
287 * registers to the values currently defined by the kernel. Currently
288 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
289 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
290 * or passes along the return value of clk_set_rate().
291 */
292static int __init _omap2_init_reprogram_sdrc(void)
293{
294 struct clk *dpll3_m2_ck;
295 int v = -EINVAL;
296 long rate;
297
298 if (!cpu_is_omap34xx())
299 return 0;
300
301 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
302 if (!dpll3_m2_ck)
303 return -EINVAL;
304
305 rate = clk_get_rate(dpll3_m2_ck);
306 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
307 v = clk_set_rate(dpll3_m2_ck, rate);
308 if (v)
309 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
310
311 clk_put(dpll3_m2_ck);
312
313 return v;
314}
315
58cda884
JP		 316void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
317 struct omap_sdrc_params *sdrc_cs1)
120db2cb 318{
97d60162
PW		 319 u8 skip_setup_idle = 0;
320
3a759f09 321 pwrdm_init(powerdomains_omap);
55ed9694 322 clkdm_init(clockdomains_omap, clkdm_autodeps);
7359154e
PW		 323 if (cpu_is_omap242x())
324 omap2420_hwmod_init();
325 else if (cpu_is_omap243x())
326 omap2430_hwmod_init();
327 else if (cpu_is_omap34xx())
328 omap3xxx_hwmod_init();
61f04ee8 329 omap2_mux_init();
7359154e 330 /* The OPP tables have to be registered before a clk init */
c0407a96 331 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
e80a9729 332
81b34fbe
PW		 333 if (cpu_is_omap2420())
334 omap2420_clk_init();
335 else if (cpu_is_omap2430())
336 omap2430_clk_init();
e80a9729
PW		 337 else if (cpu_is_omap34xx())
338 omap3xxx_clk_init();
339 else if (cpu_is_omap44xx())
340 omap4xxx_clk_init();
341 else
342 pr_err("Could not init clock framework - unknown CPU\n");
343
b3c6df3a 344 omap_serial_early_init();
97d60162
PW		 345
346#ifndef CONFIG_PM_RUNTIME
347 skip_setup_idle = 1;
348#endif
aa4b1f6e 349 if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
97d60162
PW		 350 omap_hwmod_late_init(skip_setup_idle);
351
c0407a96 352 omap_pm_if_init();
aa4b1f6e
KH		 353 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
354 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
355 _omap2_init_reprogram_sdrc();
356 }
4bbbc1ad 357 gpmc_init();
1dbae815 358}
Linux kernel - Deliverables
This page took 0.392824 seconds and 5 git commands to generate.