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ARM: OMAP2+: clock: remove dead definitions from the clock header file
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
1d5aef49 40#include "omap-pm.h"
3e6ece13 41#include "sdrc.h"
b6a4226c 42#include "control.h"
3d82cbbb 43#include "serial.h"
bf027ca1 44#include "sram.h"
c4ceedcb
PW		 45#include "cm2xxx.h"
46#include "cm3xxx.h"
7632a02f 47#include "cm33xx.h"
ab6c9bbf 48#include "cm44xx.h"
d9a16f9a
PW		 49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
63a293e0
PW		 53#include "prm2xxx.h"
54#include "prm3xxx.h"
d9bbe84f 55#include "prm33xx.h"
63a293e0 56#include "prm44xx.h"
69a1e7a1 57#include "opp2xxx.h"
02bfc030 58
ff931c82 59/*
cfa9667d 60 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 61 * clock initializations
62 */
cfa9667d 63static int (*omap_clk_soc_init)(void);
ff931c82 64
1dbae815
TL		 65/*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
cc26b3b0 69
e48f814e 70#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 71static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
09f21ed4 78 {
cc26b3b0
SMK		 79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
09f21ed4 83 },
cc26b3b0
SMK		 84};
85
59b479e0 86#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 87static struct map_desc omap242x_io_desc[] __initdata = {
88 {
7adb9987
PW		 89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 92 .type = MT_DEVICE
93 },
94 {
7adb9987
PW		 95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
cc26b3b0 98 .type = MT_DEVICE
09f21ed4 99 },
cc26b3b0 100 {
7adb9987
PW		 101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 104 .type = MT_DEVICE
105 },
106};
107
108#endif
109
59b479e0 110#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 111static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
cc26b3b0
SMK		 124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136};
72d0f1c3 137#endif
72d0f1c3 138#endif
cc26b3b0 139
a8eb7ca0 140#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 141static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 142 {
cc26b3b0
SMK		 143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
c40fae95
TL		 146 .type = MT_DEVICE
147 },
148 {
cc26b3b0
SMK		 149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
c40fae95
TL		 152 .type = MT_DEVICE
153 },
cc26b3b0
SMK		 154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
1dbae815 158 .type = MT_DEVICE
cc26b3b0
SMK		 159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
1dbae815 170 .type = MT_DEVICE
cc26b3b0
SMK		 171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
1dbae815 184};
cc26b3b0 185#endif
01001712 186
33959553 187#ifdef CONFIG_SOC_TI81XX
a920360f 188static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195};
196#endif
197
addb154a 198#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 199static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
1e6cb146
AM		 206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
01001712
HP		 212};
213#endif
214
44169075
SS		 215#ifdef CONFIG_ARCH_OMAP4
216static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
44169075
SS		 229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
44169075
SS		 235};
236#endif
1dbae815 237
a3a9384a 238#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
05e152c7
S		 239static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264};
265#endif
266
59b479e0 267#ifdef CONFIG_SOC_OMAP2420
b6a4226c 268void __init omap242x_map_io(void)
1dbae815 269{
cc26b3b0
SMK		 270 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
271 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 272}
cc26b3b0
SMK		 273#endif
274
59b479e0 275#ifdef CONFIG_SOC_OMAP2430
b6a4226c 276void __init omap243x_map_io(void)
6fbd55d0 277{
cc26b3b0
SMK		 278 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
279 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 280}
cc26b3b0
SMK		 281#endif
282
a8eb7ca0 283#ifdef CONFIG_ARCH_OMAP3
b6a4226c 284void __init omap3_map_io(void)
6fbd55d0 285{
cc26b3b0 286 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 287}
cc26b3b0 288#endif
120db2cb 289
33959553 290#ifdef CONFIG_SOC_TI81XX
b6a4226c 291void __init ti81xx_map_io(void)
01001712 292{
a920360f 293 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 294}
295#endif
296
addb154a 297#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 298void __init am33xx_map_io(void)
01001712 299{
1e6cb146 300 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 301}
302#endif
303
6fbd55d0 304#ifdef CONFIG_ARCH_OMAP4
b6a4226c 305void __init omap4_map_io(void)
6fbd55d0 306{
44169075 307 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
120db2cb 308}
6fbd55d0 309#endif
120db2cb 310
a3a9384a 311#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
b6a4226c 312void __init omap5_map_io(void)
05e152c7
S		 313{
314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
315}
316#endif
2f135eaf
PW		 317/*
318 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
319 *
320 * Sets the CORE DPLL3 M2 divider to the same value that it's at
321 * currently. This has the effect of setting the SDRC SDRAM AC timing
322 * registers to the values currently defined by the kernel. Currently
323 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
324 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
325 * or passes along the return value of clk_set_rate().
326 */
327static int __init _omap2_init_reprogram_sdrc(void)
328{
329 struct clk *dpll3_m2_ck;
330 int v = -EINVAL;
331 long rate;
332
333 if (!cpu_is_omap34xx())
334 return 0;
335
336 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 337 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 338 return -EINVAL;
339
340 rate = clk_get_rate(dpll3_m2_ck);
341 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
342 v = clk_set_rate(dpll3_m2_ck, rate);
343 if (v)
344 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
345
346 clk_put(dpll3_m2_ck);
347
348 return v;
349}
350
2092e5cc
PW		 351static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
352{
353 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
354}
355
7b250aff
TL		 356static void __init omap_hwmod_init_postsetup(void)
357{
358 u8 postsetup_state;
2092e5cc
PW		 359
360 /* Set the default postsetup state for all hwmods */
bf7c5449 361#ifdef CONFIG_PM
2092e5cc
PW		 362 postsetup_state = _HWMOD_STATE_IDLE;
363#else
364 postsetup_state = _HWMOD_STATE_ENABLED;
365#endif
366 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 367
53da4ce2 368 omap_pm_if_early_init();
4805734b
PW		 369}
370
069d0a78 371static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 372{
373 omap_mux_late_init();
374 omap2_common_pm_late_init();
6770b211 375 omap_soc_device_init();
4ed12be0
RB		 376}
377
16110798 378#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 379void __init omap2420_init_early(void)
380{
b6a4226c
PW		 381 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
382 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
383 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
2208bf11 384 omap2_control_base_init();
4de34f35 385 omap2xxx_check_revision();
ab7b2ffc 386 omap2_prcm_base_init();
7b250aff
TL		 387 omap2xxx_voltagedomains_init();
388 omap242x_powerdomains_init();
389 omap242x_clockdomains_init();
390 omap2420_hwmod_init();
391 omap_hwmod_init_postsetup();
6a194a6e
TK		 392 omap_clk_soc_init = omap2420_dt_clk_init;
393 rate_table = omap2420_rate_table;
8f5b5a41 394}
bbd707ac
SG		 395
396void __init omap2420_init_late(void)
397{
4ed12be0 398 omap_common_late_init();
bbd707ac 399 omap2_pm_init();
23fb8ba3 400 omap2_clk_enable_autoidle_all();
bbd707ac 401}
16110798 402#endif
8f5b5a41 403
16110798 404#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 405void __init omap2430_init_early(void)
406{
b6a4226c
PW		 407 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
408 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
409 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
2208bf11 410 omap2_control_base_init();
4de34f35 411 omap2xxx_check_revision();
ab7b2ffc 412 omap2_prcm_base_init();
7b250aff
TL		 413 omap2xxx_voltagedomains_init();
414 omap243x_powerdomains_init();
415 omap243x_clockdomains_init();
416 omap2430_hwmod_init();
417 omap_hwmod_init_postsetup();
6a194a6e
TK		 418 omap_clk_soc_init = omap2430_dt_clk_init;
419 rate_table = omap2430_rate_table;
7b250aff 420}
bbd707ac
SG		 421
422void __init omap2430_init_late(void)
423{
4ed12be0 424 omap_common_late_init();
bbd707ac 425 omap2_pm_init();
23fb8ba3 426 omap2_clk_enable_autoidle_all();
bbd707ac 427}
c4e2d245 428#endif
7b250aff
TL		 429
430/*
431 * Currently only board-omap3beagle.c should call this because of the
432 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
433 */
c4e2d245 434#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 435void __init omap3_init_early(void)
436{
b6a4226c
PW		 437 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
438 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
439 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
2208bf11
TK		 440 /* XXX: remove these once OMAP3 is DT only */
441 if (!of_have_populated_dt()) {
442 omap2_set_globals_control(
efde2346 443 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
2208bf11
TK		 444 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
445 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
446 NULL);
447 }
448 omap2_control_base_init();
4de34f35
VH		 449 omap3xxx_check_revision();
450 omap3xxx_check_features();
ab7b2ffc 451 omap2_prcm_base_init();
425dc8b2
TK		 452 /* XXX: remove these once OMAP3 is DT only */
453 if (!of_have_populated_dt()) {
454 omap3xxx_prm_init(NULL);
455 omap3xxx_cm_init(NULL);
456 }
7b250aff
TL		 457 omap3xxx_voltagedomains_init();
458 omap3xxx_powerdomains_init();
459 omap3xxx_clockdomains_init();
460 omap3xxx_hwmod_init();
461 omap_hwmod_init_postsetup();
eded36fe 462 if (!of_have_populated_dt()) {
2208bf11 463 omap3_control_legacy_iomap_init();
eded36fe
TK		 464 if (soc_is_am35xx())
465 omap_clk_soc_init = am35xx_clk_legacy_init;
466 else if (cpu_is_omap3630())
467 omap_clk_soc_init = omap36xx_clk_legacy_init;
468 else if (omap_rev() == OMAP3430_REV_ES1_0)
469 omap_clk_soc_init = omap3430es1_clk_legacy_init;
470 else
471 omap_clk_soc_init = omap3430_clk_legacy_init;
472 }
8f5b5a41
TL		 473}
474
475void __init omap3430_init_early(void)
476{
7b250aff 477 omap3_init_early();
3e049157
TK		 478 if (of_have_populated_dt())
479 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 480}
481
482void __init omap35xx_init_early(void)
483{
7b250aff 484 omap3_init_early();
3e049157
TK		 485 if (of_have_populated_dt())
486 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 487}
488
489void __init omap3630_init_early(void)
490{
7b250aff 491 omap3_init_early();
3e049157
TK		 492 if (of_have_populated_dt())
493 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 494}
495
496void __init am35xx_init_early(void)
497{
7b250aff 498 omap3_init_early();
3e049157
TK		 499 if (of_have_populated_dt())
500 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 501}
502
bbd707ac
SG		 503void __init omap3_init_late(void)
504{
4ed12be0 505 omap_common_late_init();
bbd707ac 506 omap3_pm_init();
23fb8ba3 507 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 508}
509
510void __init omap3430_init_late(void)
511{
4ed12be0 512 omap_common_late_init();
bbd707ac 513 omap3_pm_init();
23fb8ba3 514 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 515}
516
517void __init omap35xx_init_late(void)
518{
4ed12be0 519 omap_common_late_init();
bbd707ac 520 omap3_pm_init();
23fb8ba3 521 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 522}
523
524void __init omap3630_init_late(void)
525{
4ed12be0 526 omap_common_late_init();
bbd707ac 527 omap3_pm_init();
23fb8ba3 528 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 529}
530
531void __init am35xx_init_late(void)
532{
4ed12be0 533 omap_common_late_init();
bbd707ac 534 omap3_pm_init();
23fb8ba3 535 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 536}
537
538void __init ti81xx_init_late(void)
539{
4ed12be0 540 omap_common_late_init();
23fb8ba3 541 omap2_clk_enable_autoidle_all();
bbd707ac 542}
c4e2d245 543#endif
8f5b5a41 544
a64459c4
AM		 545#ifdef CONFIG_SOC_TI81XX
546void __init ti814x_init_early(void)
547{
548 omap2_set_globals_tap(TI814X_CLASS,
549 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 550 omap2_control_base_init();
a64459c4
AM		 551 omap3xxx_check_revision();
552 ti81xx_check_features();
ab7b2ffc 553 omap2_prcm_base_init();
a64459c4
AM		 554 omap3xxx_voltagedomains_init();
555 omap3xxx_powerdomains_init();
556 ti81xx_clockdomains_init();
4d38bd12 557 ti81xx_hwmod_init();
a64459c4
AM		 558 omap_hwmod_init_postsetup();
559 if (of_have_populated_dt())
560 omap_clk_soc_init = ti81xx_dt_clk_init;
561}
562
563void __init ti816x_init_early(void)
564{
565 omap2_set_globals_tap(TI816X_CLASS,
566 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 567 omap2_control_base_init();
a64459c4
AM		 568 omap3xxx_check_revision();
569 ti81xx_check_features();
ab7b2ffc 570 omap2_prcm_base_init();
a64459c4
AM		 571 omap3xxx_voltagedomains_init();
572 omap3xxx_powerdomains_init();
573 ti81xx_clockdomains_init();
4d38bd12 574 ti81xx_hwmod_init();
a64459c4
AM		 575 omap_hwmod_init_postsetup();
576 if (of_have_populated_dt())
577 omap_clk_soc_init = ti81xx_dt_clk_init;
578}
579#endif
580
08f30989
AM		 581#ifdef CONFIG_SOC_AM33XX
582void __init am33xx_init_early(void)
583{
b6a4226c
PW		 584 omap2_set_globals_tap(AM335X_CLASS,
585 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 586 omap2_control_base_init();
08f30989 587 omap3xxx_check_revision();
7bcad170 588 am33xx_check_features();
ab7b2ffc 589 omap2_prcm_base_init();
3f0ea764 590 am33xx_powerdomains_init();
9c80f3aa 591 am33xx_clockdomains_init();
a2cfc509
VH		 592 am33xx_hwmod_init();
593 omap_hwmod_init_postsetup();
149c09d3 594 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 595}
765e7a06
NM		 596
597void __init am33xx_init_late(void)
598{
599 omap_common_late_init();
600}
08f30989
AM		 601#endif
602
c5107027
AM		 603#ifdef CONFIG_SOC_AM43XX
604void __init am43xx_init_early(void)
605{
606 omap2_set_globals_tap(AM335X_CLASS,
607 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 608 omap2_control_base_init();
c5107027 609 omap3xxx_check_revision();
7a2e0513 610 am33xx_check_features();
ab7b2ffc 611 omap2_prcm_base_init();
8835cf6e
A		 612 am43xx_powerdomains_init();
613 am43xx_clockdomains_init();
614 am43xx_hwmod_init();
615 omap_hwmod_init_postsetup();
d941f86f 616 omap_l2_cache_init();
d22031e2 617 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 618}
765e7a06
NM		 619
620void __init am43xx_init_late(void)
621{
622 omap_common_late_init();
623}
c5107027
AM		 624#endif
625
c4e2d245 626#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 627void __init omap4430_init_early(void)
628{
b6a4226c
PW		 629 omap2_set_globals_tap(OMAP443X_CLASS,
630 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
d9a16f9a 631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
ca125b5e 632 omap2_control_base_init();
4de34f35
VH		 633 omap4xxx_check_revision();
634 omap4xxx_check_features();
ab7b2ffc 635 omap2_prcm_base_init();
de70af49 636 omap4_pm_init_early();
7b250aff
TL		 637 omap44xx_voltagedomains_init();
638 omap44xx_powerdomains_init();
639 omap44xx_clockdomains_init();
640 omap44xx_hwmod_init();
641 omap_hwmod_init_postsetup();
b39b14e6 642 omap_l2_cache_init();
c8c88d85 643 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 644}
bbd707ac
SG		 645
646void __init omap4430_init_late(void)
647{
4ed12be0 648 omap_common_late_init();
bbd707ac 649 omap4_pm_init();
23fb8ba3 650 omap2_clk_enable_autoidle_all();
bbd707ac 651}
c4e2d245 652#endif
8f5b5a41 653
05e152c7
S		 654#ifdef CONFIG_SOC_OMAP5
655void __init omap5_init_early(void)
656{
b6a4226c
PW		 657 omap2_set_globals_tap(OMAP54XX_CLASS,
658 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
d9a16f9a 659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 660 omap2_control_base_init();
628ed471 661 omap4_pm_init_early();
ab7b2ffc 662 omap2_prcm_base_init();
05e152c7 663 omap5xxx_check_revision();
e4020aa9
SS		 664 omap54xx_voltagedomains_init();
665 omap54xx_powerdomains_init();
666 omap54xx_clockdomains_init();
667 omap54xx_hwmod_init();
668 omap_hwmod_init_postsetup();
cfa9667d 669 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 670}
765e7a06
NM		 671
672void __init omap5_init_late(void)
673{
674 omap_common_late_init();
628ed471
SS		 675 omap4_pm_init();
676 omap2_clk_enable_autoidle_all();
765e7a06 677}
05e152c7
S		 678#endif
679
a3a9384a
S		 680#ifdef CONFIG_SOC_DRA7XX
681void __init dra7xx_init_early(void)
682{
683 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
a3a9384a 684 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 685 omap2_control_base_init();
6af16a1d 686 omap4_pm_init_early();
ab7b2ffc 687 omap2_prcm_base_init();
733d20ee 688 dra7xxx_check_revision();
7de516a6
A		 689 dra7xx_powerdomains_init();
690 dra7xx_clockdomains_init();
691 dra7xx_hwmod_init();
692 omap_hwmod_init_postsetup();
f1cf498e 693 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 694}
765e7a06
NM		 695
696void __init dra7xx_init_late(void)
697{
698 omap_common_late_init();
6af16a1d
RN		 699 omap4_pm_init();
700 omap2_clk_enable_autoidle_all();
765e7a06 701}
a3a9384a
S		 702#endif
703
704
a4ca9dbe 705void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 706 struct omap_sdrc_params *sdrc_cs1)
707{
a66cb345
TL		 708 omap_sram_init();
709
01001712 710 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 711 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
712 _omap2_init_reprogram_sdrc();
713 }
1dbae815 714}
cfa9667d
TK		 715
716int __init omap_clk_init(void)
717{
718 int ret = 0;
719
720 if (!omap_clk_soc_init)
721 return 0;
722
8111e010
TK		 723 ti_clk_init_features();
724
eded36fe 725 if (of_have_populated_dt()) {
fe87414f
TK		 726 ret = omap_control_init();
727 if (ret)
728 return ret;
729
3a1a388e 730 ret = omap_prcm_init();
eded36fe
TK		 731 if (ret)
732 return ret;
c08ee14c 733
eded36fe 734 of_clk_init(NULL);
c08ee14c 735
eded36fe 736 ti_dt_clk_init_retry_clks();
c08ee14c 737
eded36fe
TK		 738 ti_dt_clockdomains_setup();
739 }
c08ee14c
TK		 740
741 ret = omap_clk_soc_init();
cfa9667d
TK		 742
743 return ret;
744}
Linux kernel - Deliverables
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