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ARM: OMAP: Map SRAM later on with ioremap_exec()
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
1dbae815
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
2f135eaf 24#include <linux/clk.h>
91773a00 25#include <linux/omapfb.h>
1dbae815 26
120db2cb 27#include <asm/tlb.h>
120db2cb
TL		 28
29#include <asm/mach/map.h>
30
ce491cf8
TL		 31#include <plat/sram.h>
32#include <plat/sdrc.h>
ce491cf8 33#include <plat/serial.h>
646e3ed1 34
e80a9729 35#include "clock2xxx.h"
657ebfad 36#include "clock3xxx.h"
e80a9729 37#include "clock44xx.h"
1dbae815 38
a66cb345 39#include <plat/common.h>
ce491cf8 40#include <plat/omap-pm.h>
81a60482 41#include "voltage.h"
72e06d08 42#include "powerdomain.h"
1dbae815 43
1540f214 44#include "clockdomain.h"
ce491cf8 45#include <plat/omap_hwmod.h>
5d190c40 46#include <plat/multi.h>
02bfc030 47
1dbae815
TL		 48/*
49 * The machine specific code may provide the extra mapping besides the
50 * default mapping provided here.
51 */
cc26b3b0 52
088ef950 53#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 54static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 55 {
56 .virtual = L3_24XX_VIRT,
57 .pfn = __phys_to_pfn(L3_24XX_PHYS),
58 .length = L3_24XX_SIZE,
59 .type = MT_DEVICE
60 },
09f21ed4 61 {
cc26b3b0
SMK		 62 .virtual = L4_24XX_VIRT,
63 .pfn = __phys_to_pfn(L4_24XX_PHYS),
64 .length = L4_24XX_SIZE,
65 .type = MT_DEVICE
09f21ed4 66 },
cc26b3b0
SMK		 67};
68
59b479e0 69#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 70static struct map_desc omap242x_io_desc[] __initdata = {
71 {
7adb9987
PW		 72 .virtual = DSP_MEM_2420_VIRT,
73 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
74 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 75 .type = MT_DEVICE
76 },
77 {
7adb9987
PW		 78 .virtual = DSP_IPI_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
80 .length = DSP_IPI_2420_SIZE,
cc26b3b0 81 .type = MT_DEVICE
09f21ed4 82 },
cc26b3b0 83 {
7adb9987
PW		 84 .virtual = DSP_MMU_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
86 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 87 .type = MT_DEVICE
88 },
89};
90
91#endif
92
59b479e0 93#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 94static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 95 {
96 .virtual = L4_WK_243X_VIRT,
97 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
98 .length = L4_WK_243X_SIZE,
99 .type = MT_DEVICE
100 },
101 {
102 .virtual = OMAP243X_GPMC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
104 .length = OMAP243X_GPMC_SIZE,
105 .type = MT_DEVICE
106 },
cc26b3b0
SMK		 107 {
108 .virtual = OMAP243X_SDRC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
110 .length = OMAP243X_SDRC_SIZE,
111 .type = MT_DEVICE
112 },
113 {
114 .virtual = OMAP243X_SMS_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
116 .length = OMAP243X_SMS_SIZE,
117 .type = MT_DEVICE
118 },
119};
72d0f1c3 120#endif
72d0f1c3 121#endif
cc26b3b0 122
a8eb7ca0 123#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 124static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 125 {
cc26b3b0
SMK		 126 .virtual = L3_34XX_VIRT,
127 .pfn = __phys_to_pfn(L3_34XX_PHYS),
128 .length = L3_34XX_SIZE,
c40fae95
TL		 129 .type = MT_DEVICE
130 },
131 {
cc26b3b0
SMK		 132 .virtual = L4_34XX_VIRT,
133 .pfn = __phys_to_pfn(L4_34XX_PHYS),
134 .length = L4_34XX_SIZE,
c40fae95
TL		 135 .type = MT_DEVICE
136 },
cc26b3b0
SMK		 137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
1dbae815 141 .type = MT_DEVICE
cc26b3b0
SMK		 142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
1dbae815 153 .type = MT_DEVICE
cc26b3b0
SMK		 154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
a4f57b81
TL		 167#if defined(CONFIG_DEBUG_LL) && \
168 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
169 {
170 .virtual = ZOOM_UART_VIRT,
171 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
172 .length = SZ_1M,
173 .type = MT_DEVICE
174 },
175#endif
1dbae815 176};
cc26b3b0 177#endif
01001712
HP		 178
179#ifdef CONFIG_SOC_OMAPTI816X
180static struct map_desc omapti816x_io_desc[] __initdata = {
181 {
182 .virtual = L4_34XX_VIRT,
183 .pfn = __phys_to_pfn(L4_34XX_PHYS),
184 .length = L4_34XX_SIZE,
185 .type = MT_DEVICE
186 },
187};
188#endif
189
44169075
SS		 190#ifdef CONFIG_ARCH_OMAP4
191static struct map_desc omap44xx_io_desc[] __initdata = {
192 {
193 .virtual = L3_44XX_VIRT,
194 .pfn = __phys_to_pfn(L3_44XX_PHYS),
195 .length = L3_44XX_SIZE,
196 .type = MT_DEVICE,
197 },
198 {
199 .virtual = L4_44XX_VIRT,
200 .pfn = __phys_to_pfn(L4_44XX_PHYS),
201 .length = L4_44XX_SIZE,
202 .type = MT_DEVICE,
203 },
44169075
SS		 204 {
205 .virtual = OMAP44XX_GPMC_VIRT,
206 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
207 .length = OMAP44XX_GPMC_SIZE,
208 .type = MT_DEVICE,
209 },
f5d2d659
SS		 210 {
211 .virtual = OMAP44XX_EMIF1_VIRT,
212 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
213 .length = OMAP44XX_EMIF1_SIZE,
214 .type = MT_DEVICE,
215 },
216 {
217 .virtual = OMAP44XX_EMIF2_VIRT,
218 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
219 .length = OMAP44XX_EMIF2_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
223 .virtual = OMAP44XX_DMM_VIRT,
224 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
225 .length = OMAP44XX_DMM_SIZE,
226 .type = MT_DEVICE,
227 },
44169075
SS		 228 {
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
234 {
235 .virtual = L4_EMU_44XX_VIRT,
236 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
237 .length = L4_EMU_44XX_SIZE,
238 .type = MT_DEVICE,
239 },
240};
241#endif
1dbae815 242
59b479e0 243#ifdef CONFIG_SOC_OMAP2420
8185e468 244void __init omap242x_map_common_io(void)
1dbae815 245{
cc26b3b0
SMK		 246 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
247 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 248}
cc26b3b0
SMK		 249#endif
250
59b479e0 251#ifdef CONFIG_SOC_OMAP2430
8185e468 252void __init omap243x_map_common_io(void)
6fbd55d0 253{
cc26b3b0
SMK		 254 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
255 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 256}
cc26b3b0
SMK		 257#endif
258
a8eb7ca0 259#ifdef CONFIG_ARCH_OMAP3
8185e468 260void __init omap34xx_map_common_io(void)
6fbd55d0 261{
cc26b3b0 262 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 263}
cc26b3b0 264#endif
120db2cb 265
01001712
HP		 266#ifdef CONFIG_SOC_OMAPTI816X
267void __init omapti816x_map_common_io(void)
268{
269 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
01001712
HP		 270}
271#endif
272
6fbd55d0 273#ifdef CONFIG_ARCH_OMAP4
8185e468 274void __init omap44xx_map_common_io(void)
6fbd55d0 275{
44169075 276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
120db2cb 277}
6fbd55d0 278#endif
120db2cb 279
2f135eaf
PW		 280/*
281 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
282 *
283 * Sets the CORE DPLL3 M2 divider to the same value that it's at
284 * currently. This has the effect of setting the SDRC SDRAM AC timing
285 * registers to the values currently defined by the kernel. Currently
286 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
287 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
288 * or passes along the return value of clk_set_rate().
289 */
290static int __init _omap2_init_reprogram_sdrc(void)
291{
292 struct clk *dpll3_m2_ck;
293 int v = -EINVAL;
294 long rate;
295
296 if (!cpu_is_omap34xx())
297 return 0;
298
299 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 300 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 301 return -EINVAL;
302
303 rate = clk_get_rate(dpll3_m2_ck);
304 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
305 v = clk_set_rate(dpll3_m2_ck, rate);
306 if (v)
307 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
308
309 clk_put(dpll3_m2_ck);
310
311 return v;
312}
313
2092e5cc
PW		 314static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
315{
316 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
317}
318
741e3a89 319/* See irq.c, omap4-common.c and entry-macro.S */
9f9605c2
RK		 320void __iomem *omap_irq_base;
321
7b250aff 322static void __init omap_common_init_early(void)
120db2cb 323{
7b250aff 324 omap2_check_revision();
7b250aff 325}
2092e5cc 326
7b250aff
TL		 327static void __init omap_hwmod_init_postsetup(void)
328{
329 u8 postsetup_state;
2092e5cc
PW		 330
331 /* Set the default postsetup state for all hwmods */
332#ifdef CONFIG_PM_RUNTIME
333 postsetup_state = _HWMOD_STATE_IDLE;
334#else
335 postsetup_state = _HWMOD_STATE_ENABLED;
336#endif
337 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 338
ff2516fb
PW		 339 /*
340 * Set the default postsetup state for unusual modules (like
341 * MPU WDT).
342 *
343 * The postsetup_state is not actually used until
344 * omap_hwmod_late_init(), so boards that desire full watchdog
345 * coverage of kernel initialization can reprogram the
346 * postsetup_state between the calls to
a4ca9dbe 347 * omap2_init_common_infra() and omap_sdrc_init().
ff2516fb
PW		 348 *
349 * XXX ideally we could detect whether the MPU WDT was currently
350 * enabled here and make this conditional
351 */
352 postsetup_state = _HWMOD_STATE_DISABLED;
353 omap_hwmod_for_each_by_class("wd_timer",
354 _set_hwmod_postsetup_state,
355 &postsetup_state);
356
53da4ce2 357 omap_pm_if_early_init();
4805734b
PW		 358}
359
8f5b5a41
TL		 360void __init omap2420_init_early(void)
361{
7b250aff
TL		 362 omap_common_init_early();
363 omap2xxx_voltagedomains_init();
364 omap242x_powerdomains_init();
365 omap242x_clockdomains_init();
366 omap2420_hwmod_init();
367 omap_hwmod_init_postsetup();
368 omap2420_clk_init();
8f5b5a41
TL		 369}
370
371void __init omap2430_init_early(void)
372{
7b250aff
TL		 373 omap_common_init_early();
374 omap2xxx_voltagedomains_init();
375 omap243x_powerdomains_init();
376 omap243x_clockdomains_init();
377 omap2430_hwmod_init();
378 omap_hwmod_init_postsetup();
379 omap2430_clk_init();
380}
381
382/*
383 * Currently only board-omap3beagle.c should call this because of the
384 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
385 */
386void __init omap3_init_early(void)
387{
388 omap_common_init_early();
389 omap3xxx_voltagedomains_init();
390 omap3xxx_powerdomains_init();
391 omap3xxx_clockdomains_init();
392 omap3xxx_hwmod_init();
393 omap_hwmod_init_postsetup();
394 omap3xxx_clk_init();
8f5b5a41
TL		 395}
396
397void __init omap3430_init_early(void)
398{
7b250aff 399 omap3_init_early();
8f5b5a41
TL		 400}
401
402void __init omap35xx_init_early(void)
403{
7b250aff 404 omap3_init_early();
8f5b5a41
TL		 405}
406
407void __init omap3630_init_early(void)
408{
7b250aff 409 omap3_init_early();
8f5b5a41
TL		 410}
411
412void __init am35xx_init_early(void)
413{
7b250aff 414 omap3_init_early();
8f5b5a41
TL		 415}
416
417void __init ti816x_init_early(void)
418{
7b250aff 419 omap3_init_early();
8f5b5a41
TL		 420}
421
422void __init omap4430_init_early(void)
423{
7b250aff
TL		 424 omap_common_init_early();
425 omap44xx_voltagedomains_init();
426 omap44xx_powerdomains_init();
427 omap44xx_clockdomains_init();
428 omap44xx_hwmod_init();
429 omap_hwmod_init_postsetup();
430 omap4xxx_clk_init();
8f5b5a41
TL		 431}
432
a4ca9dbe 433void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 434 struct omap_sdrc_params *sdrc_cs1)
435{
a66cb345
TL		 436 omap_sram_init();
437
01001712 438 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 439 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
440 _omap2_init_reprogram_sdrc();
441 }
1dbae815 442}
df1e9d1c
TL		 443
444/*
445 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
446 */
447
448u8 omap_readb(u32 pa)
449{
450 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
451}
452EXPORT_SYMBOL(omap_readb);
453
454u16 omap_readw(u32 pa)
455{
456 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
457}
458EXPORT_SYMBOL(omap_readw);
459
460u32 omap_readl(u32 pa)
461{
462 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
463}
464EXPORT_SYMBOL(omap_readl);
465
466void omap_writeb(u8 v, u32 pa)
467{
468 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
469}
470EXPORT_SYMBOL(omap_writeb);
471
472void omap_writew(u16 v, u32 pa)
473{
474 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
475}
476EXPORT_SYMBOL(omap_writew);
477
478void omap_writel(u32 v, u32 pa)
479{
480 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
481}
482EXPORT_SYMBOL(omap_writel);
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