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ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready()
[deliverable/linux.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
2b6c4e73 28#include <plat-omap/dma-omap.h>
ee0839c2 29
622297fd 30#include "../plat-omap/sram.h"
b6a4226c 31#include <plat/prcm.h>
622297fd 32
dc843280 33#include "omap_hwmod.h"
dbc04161 34#include "soc.h"
ee0839c2 35#include "iomap.h"
81a60482 36#include "voltage.h"
72e06d08 37#include "powerdomain.h"
1540f214 38#include "clockdomain.h"
4e65331c 39#include "common.h"
e30384ab 40#include "clock.h"
ee0839c2
TL		 41#include "clock2xxx.h"
42#include "clock3xxx.h"
43#include "clock44xx.h"
1d5aef49 44#include "omap-pm.h"
3e6ece13 45#include "sdrc.h"
b6a4226c 46#include "control.h"
3d82cbbb 47#include "serial.h"
02bfc030 48
1dbae815
TL		 49/*
50 * The machine specific code may provide the extra mapping besides the
51 * default mapping provided here.
52 */
cc26b3b0 53
e48f814e 54#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 55static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 56 {
57 .virtual = L3_24XX_VIRT,
58 .pfn = __phys_to_pfn(L3_24XX_PHYS),
59 .length = L3_24XX_SIZE,
60 .type = MT_DEVICE
61 },
09f21ed4 62 {
cc26b3b0
SMK		 63 .virtual = L4_24XX_VIRT,
64 .pfn = __phys_to_pfn(L4_24XX_PHYS),
65 .length = L4_24XX_SIZE,
66 .type = MT_DEVICE
09f21ed4 67 },
cc26b3b0
SMK		 68};
69
59b479e0 70#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 71static struct map_desc omap242x_io_desc[] __initdata = {
72 {
7adb9987
PW		 73 .virtual = DSP_MEM_2420_VIRT,
74 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
75 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 76 .type = MT_DEVICE
77 },
78 {
7adb9987
PW		 79 .virtual = DSP_IPI_2420_VIRT,
80 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
81 .length = DSP_IPI_2420_SIZE,
cc26b3b0 82 .type = MT_DEVICE
09f21ed4 83 },
cc26b3b0 84 {
7adb9987
PW		 85 .virtual = DSP_MMU_2420_VIRT,
86 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
87 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 88 .type = MT_DEVICE
89 },
90};
91
92#endif
93
59b479e0 94#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 95static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 96 {
97 .virtual = L4_WK_243X_VIRT,
98 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
99 .length = L4_WK_243X_SIZE,
100 .type = MT_DEVICE
101 },
102 {
103 .virtual = OMAP243X_GPMC_VIRT,
104 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
105 .length = OMAP243X_GPMC_SIZE,
106 .type = MT_DEVICE
107 },
cc26b3b0
SMK		 108 {
109 .virtual = OMAP243X_SDRC_VIRT,
110 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
111 .length = OMAP243X_SDRC_SIZE,
112 .type = MT_DEVICE
113 },
114 {
115 .virtual = OMAP243X_SMS_VIRT,
116 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
117 .length = OMAP243X_SMS_SIZE,
118 .type = MT_DEVICE
119 },
120};
72d0f1c3 121#endif
72d0f1c3 122#endif
cc26b3b0 123
a8eb7ca0 124#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 125static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 126 {
cc26b3b0
SMK		 127 .virtual = L3_34XX_VIRT,
128 .pfn = __phys_to_pfn(L3_34XX_PHYS),
129 .length = L3_34XX_SIZE,
c40fae95
TL		 130 .type = MT_DEVICE
131 },
132 {
cc26b3b0
SMK		 133 .virtual = L4_34XX_VIRT,
134 .pfn = __phys_to_pfn(L4_34XX_PHYS),
135 .length = L4_34XX_SIZE,
c40fae95
TL		 136 .type = MT_DEVICE
137 },
cc26b3b0
SMK		 138 {
139 .virtual = OMAP34XX_GPMC_VIRT,
140 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
141 .length = OMAP34XX_GPMC_SIZE,
1dbae815 142 .type = MT_DEVICE
cc26b3b0
SMK		 143 },
144 {
145 .virtual = OMAP343X_SMS_VIRT,
146 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
147 .length = OMAP343X_SMS_SIZE,
148 .type = MT_DEVICE
149 },
150 {
151 .virtual = OMAP343X_SDRC_VIRT,
152 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
153 .length = OMAP343X_SDRC_SIZE,
1dbae815 154 .type = MT_DEVICE
cc26b3b0
SMK		 155 },
156 {
157 .virtual = L4_PER_34XX_VIRT,
158 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
159 .length = L4_PER_34XX_SIZE,
160 .type = MT_DEVICE
161 },
162 {
163 .virtual = L4_EMU_34XX_VIRT,
164 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
165 .length = L4_EMU_34XX_SIZE,
166 .type = MT_DEVICE
167 },
a4f57b81
TL		 168#if defined(CONFIG_DEBUG_LL) && \
169 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
170 {
171 .virtual = ZOOM_UART_VIRT,
172 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
173 .length = SZ_1M,
174 .type = MT_DEVICE
175 },
176#endif
1dbae815 177};
cc26b3b0 178#endif
01001712 179
33959553 180#ifdef CONFIG_SOC_TI81XX
a920360f 181static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 182 {
183 .virtual = L4_34XX_VIRT,
184 .pfn = __phys_to_pfn(L4_34XX_PHYS),
185 .length = L4_34XX_SIZE,
186 .type = MT_DEVICE
187 }
188};
189#endif
190
bb6abcf4 191#ifdef CONFIG_SOC_AM33XX
1e6cb146 192static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 193 {
194 .virtual = L4_34XX_VIRT,
195 .pfn = __phys_to_pfn(L4_34XX_PHYS),
196 .length = L4_34XX_SIZE,
197 .type = MT_DEVICE
198 },
1e6cb146
AM		 199 {
200 .virtual = L4_WK_AM33XX_VIRT,
201 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
202 .length = L4_WK_AM33XX_SIZE,
203 .type = MT_DEVICE
204 }
01001712
HP		 205};
206#endif
207
44169075
SS		 208#ifdef CONFIG_ARCH_OMAP4
209static struct map_desc omap44xx_io_desc[] __initdata = {
210 {
211 .virtual = L3_44XX_VIRT,
212 .pfn = __phys_to_pfn(L3_44XX_PHYS),
213 .length = L3_44XX_SIZE,
214 .type = MT_DEVICE,
215 },
216 {
217 .virtual = L4_44XX_VIRT,
218 .pfn = __phys_to_pfn(L4_44XX_PHYS),
219 .length = L4_44XX_SIZE,
220 .type = MT_DEVICE,
221 },
44169075
SS		 222 {
223 .virtual = L4_PER_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
225 .length = L4_PER_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
137d105d
SS		 228#ifdef CONFIG_OMAP4_ERRATA_I688
229 {
230 .virtual = OMAP4_SRAM_VA,
231 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
232 .length = PAGE_SIZE,
233 .type = MT_MEMORY_SO,
234 },
235#endif
236
44169075
SS		 237};
238#endif
1dbae815 239
05e152c7
S		 240#ifdef CONFIG_SOC_OMAP5
241static struct map_desc omap54xx_io_desc[] __initdata = {
242 {
243 .virtual = L3_54XX_VIRT,
244 .pfn = __phys_to_pfn(L3_54XX_PHYS),
245 .length = L3_54XX_SIZE,
246 .type = MT_DEVICE,
247 },
248 {
249 .virtual = L4_54XX_VIRT,
250 .pfn = __phys_to_pfn(L4_54XX_PHYS),
251 .length = L4_54XX_SIZE,
252 .type = MT_DEVICE,
253 },
254 {
255 .virtual = L4_WK_54XX_VIRT,
256 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
257 .length = L4_WK_54XX_SIZE,
258 .type = MT_DEVICE,
259 },
260 {
261 .virtual = L4_PER_54XX_VIRT,
262 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
263 .length = L4_PER_54XX_SIZE,
264 .type = MT_DEVICE,
265 },
266};
267#endif
268
59b479e0 269#ifdef CONFIG_SOC_OMAP2420
b6a4226c 270void __init omap242x_map_io(void)
1dbae815 271{
cc26b3b0
SMK		 272 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
273 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 274}
cc26b3b0
SMK		 275#endif
276
59b479e0 277#ifdef CONFIG_SOC_OMAP2430
b6a4226c 278void __init omap243x_map_io(void)
6fbd55d0 279{
cc26b3b0
SMK		 280 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
281 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 282}
cc26b3b0
SMK		 283#endif
284
a8eb7ca0 285#ifdef CONFIG_ARCH_OMAP3
b6a4226c 286void __init omap3_map_io(void)
6fbd55d0 287{
cc26b3b0 288 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 289}
cc26b3b0 290#endif
120db2cb 291
33959553 292#ifdef CONFIG_SOC_TI81XX
b6a4226c 293void __init ti81xx_map_io(void)
01001712 294{
a920360f 295 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 296}
297#endif
298
bb6abcf4 299#ifdef CONFIG_SOC_AM33XX
b6a4226c 300void __init am33xx_map_io(void)
01001712 301{
1e6cb146 302 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 303}
304#endif
305
6fbd55d0 306#ifdef CONFIG_ARCH_OMAP4
b6a4226c 307void __init omap4_map_io(void)
6fbd55d0 308{
44169075 309 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 310 omap_barriers_init();
120db2cb 311}
6fbd55d0 312#endif
120db2cb 313
05e152c7 314#ifdef CONFIG_SOC_OMAP5
b6a4226c 315void __init omap5_map_io(void)
05e152c7
S		 316{
317 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
318}
319#endif
2f135eaf
PW		 320/*
321 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
322 *
323 * Sets the CORE DPLL3 M2 divider to the same value that it's at
324 * currently. This has the effect of setting the SDRC SDRAM AC timing
325 * registers to the values currently defined by the kernel. Currently
326 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
327 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
328 * or passes along the return value of clk_set_rate().
329 */
330static int __init _omap2_init_reprogram_sdrc(void)
331{
332 struct clk *dpll3_m2_ck;
333 int v = -EINVAL;
334 long rate;
335
336 if (!cpu_is_omap34xx())
337 return 0;
338
339 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 340 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 341 return -EINVAL;
342
343 rate = clk_get_rate(dpll3_m2_ck);
344 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
345 v = clk_set_rate(dpll3_m2_ck, rate);
346 if (v)
347 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
348
349 clk_put(dpll3_m2_ck);
350
351 return v;
352}
353
2092e5cc
PW		 354static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
355{
356 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
357}
358
7b250aff 359static void __init omap_common_init_early(void)
120db2cb 360{
df80442d 361 omap_init_consistent_dma_size();
7b250aff 362}
2092e5cc 363
7b250aff
TL		 364static void __init omap_hwmod_init_postsetup(void)
365{
366 u8 postsetup_state;
2092e5cc
PW		 367
368 /* Set the default postsetup state for all hwmods */
369#ifdef CONFIG_PM_RUNTIME
370 postsetup_state = _HWMOD_STATE_IDLE;
371#else
372 postsetup_state = _HWMOD_STATE_ENABLED;
373#endif
374 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 375
53da4ce2 376 omap_pm_if_early_init();
4805734b
PW		 377}
378
16110798 379#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 380void __init omap2420_init_early(void)
381{
b6a4226c
PW		 382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
385 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
386 NULL);
387 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
388 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
389 NULL, NULL);
4de34f35 390 omap2xxx_check_revision();
7b250aff
TL		 391 omap_common_init_early();
392 omap2xxx_voltagedomains_init();
393 omap242x_powerdomains_init();
394 omap242x_clockdomains_init();
395 omap2420_hwmod_init();
396 omap_hwmod_init_postsetup();
397 omap2420_clk_init();
8f5b5a41 398}
bbd707ac
SG		 399
400void __init omap2420_init_late(void)
401{
402 omap_mux_late_init();
403 omap2_common_pm_late_init();
404 omap2_pm_init();
405}
16110798 406#endif
8f5b5a41 407
16110798 408#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 409void __init omap2430_init_early(void)
410{
b6a4226c
PW		 411 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
412 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
413 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
414 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
415 NULL);
416 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
417 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
418 NULL, NULL);
4de34f35 419 omap2xxx_check_revision();
7b250aff
TL		 420 omap_common_init_early();
421 omap2xxx_voltagedomains_init();
422 omap243x_powerdomains_init();
423 omap243x_clockdomains_init();
424 omap2430_hwmod_init();
425 omap_hwmod_init_postsetup();
426 omap2430_clk_init();
427}
bbd707ac
SG		 428
429void __init omap2430_init_late(void)
430{
431 omap_mux_late_init();
432 omap2_common_pm_late_init();
433 omap2_pm_init();
434}
c4e2d245 435#endif
7b250aff
TL		 436
437/*
438 * Currently only board-omap3beagle.c should call this because of the
439 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
440 */
c4e2d245 441#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 442void __init omap3_init_early(void)
443{
b6a4226c
PW		 444 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
445 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
446 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
447 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
448 NULL);
449 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
450 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
451 NULL, NULL);
4de34f35
VH		 452 omap3xxx_check_revision();
453 omap3xxx_check_features();
7b250aff
TL		 454 omap_common_init_early();
455 omap3xxx_voltagedomains_init();
456 omap3xxx_powerdomains_init();
457 omap3xxx_clockdomains_init();
458 omap3xxx_hwmod_init();
459 omap_hwmod_init_postsetup();
460 omap3xxx_clk_init();
8f5b5a41
TL		 461}
462
463void __init omap3430_init_early(void)
464{
7b250aff 465 omap3_init_early();
8f5b5a41
TL		 466}
467
468void __init omap35xx_init_early(void)
469{
7b250aff 470 omap3_init_early();
8f5b5a41
TL		 471}
472
473void __init omap3630_init_early(void)
474{
7b250aff 475 omap3_init_early();
8f5b5a41
TL		 476}
477
478void __init am35xx_init_early(void)
479{
7b250aff 480 omap3_init_early();
8f5b5a41
TL		 481}
482
a920360f 483void __init ti81xx_init_early(void)
8f5b5a41 484{
b6a4226c
PW		 485 omap2_set_globals_tap(OMAP343X_CLASS,
486 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
487 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
488 NULL);
489 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
490 OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
491 NULL, NULL);
4de34f35
VH		 492 omap3xxx_check_revision();
493 ti81xx_check_features();
4c3cf901
TL		 494 omap_common_init_early();
495 omap3xxx_voltagedomains_init();
496 omap3xxx_powerdomains_init();
497 omap3xxx_clockdomains_init();
498 omap3xxx_hwmod_init();
499 omap_hwmod_init_postsetup();
500 omap3xxx_clk_init();
8f5b5a41 501}
bbd707ac
SG		 502
503void __init omap3_init_late(void)
504{
505 omap_mux_late_init();
506 omap2_common_pm_late_init();
507 omap3_pm_init();
508}
509
510void __init omap3430_init_late(void)
511{
512 omap_mux_late_init();
513 omap2_common_pm_late_init();
514 omap3_pm_init();
515}
516
517void __init omap35xx_init_late(void)
518{
519 omap_mux_late_init();
520 omap2_common_pm_late_init();
521 omap3_pm_init();
522}
523
524void __init omap3630_init_late(void)
525{
526 omap_mux_late_init();
527 omap2_common_pm_late_init();
528 omap3_pm_init();
529}
530
531void __init am35xx_init_late(void)
532{
533 omap_mux_late_init();
534 omap2_common_pm_late_init();
535 omap3_pm_init();
536}
537
538void __init ti81xx_init_late(void)
539{
540 omap_mux_late_init();
541 omap2_common_pm_late_init();
542 omap3_pm_init();
543}
c4e2d245 544#endif
8f5b5a41 545
08f30989
AM		 546#ifdef CONFIG_SOC_AM33XX
547void __init am33xx_init_early(void)
548{
b6a4226c
PW		 549 omap2_set_globals_tap(AM335X_CLASS,
550 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
551 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
552 NULL);
553 omap2_set_globals_prcm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
554 AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
555 NULL, NULL);
08f30989
AM		 556 omap3xxx_check_revision();
557 ti81xx_check_features();
558 omap_common_init_early();
ce3fc89a 559 am33xx_voltagedomains_init();
3f0ea764 560 am33xx_powerdomains_init();
9c80f3aa 561 am33xx_clockdomains_init();
a2cfc509
VH		 562 am33xx_hwmod_init();
563 omap_hwmod_init_postsetup();
e30384ab 564 am33xx_clk_init();
08f30989
AM		 565}
566#endif
567
c4e2d245 568#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 569void __init omap4430_init_early(void)
570{
b6a4226c
PW		 571 omap2_set_globals_tap(OMAP443X_CLASS,
572 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
573 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
574 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
575 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
576 OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
577 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
578 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
4de34f35
VH		 579 omap4xxx_check_revision();
580 omap4xxx_check_features();
7b250aff
TL		 581 omap_common_init_early();
582 omap44xx_voltagedomains_init();
583 omap44xx_powerdomains_init();
584 omap44xx_clockdomains_init();
585 omap44xx_hwmod_init();
586 omap_hwmod_init_postsetup();
587 omap4xxx_clk_init();
8f5b5a41 588}
bbd707ac
SG		 589
590void __init omap4430_init_late(void)
591{
592 omap_mux_late_init();
593 omap2_common_pm_late_init();
594 omap4_pm_init();
595}
c4e2d245 596#endif
8f5b5a41 597
05e152c7
S		 598#ifdef CONFIG_SOC_OMAP5
599void __init omap5_init_early(void)
600{
b6a4226c
PW		 601 omap2_set_globals_tap(OMAP54XX_CLASS,
602 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
603 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
604 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
605 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
606 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
607 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
608 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
05e152c7
S		 609 omap5xxx_check_revision();
610 omap_common_init_early();
611}
612#endif
613
a4ca9dbe 614void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 615 struct omap_sdrc_params *sdrc_cs1)
616{
a66cb345
TL		 617 omap_sram_init();
618
01001712 619 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 620 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
621 _omap2_init_reprogram_sdrc();
622 }
1dbae815 623}
Linux kernel - Deliverables
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