Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/irq.c |
1dbae815 TL |
3 | * |
4 | * Interrupt handler for OMAP2 boards. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
52fa2120 | 14 | #include <linux/module.h> |
1dbae815 | 15 | #include <linux/init.h> |
1dbae815 | 16 | #include <linux/interrupt.h> |
2e7509e5 | 17 | #include <linux/io.h> |
ee0839c2 | 18 | |
2db14997 | 19 | #include <asm/exception.h> |
1dbae815 | 20 | #include <asm/mach/irq.h> |
52fa2120 BC |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
c4082d49 | 24 | #include <linux/of_irq.h> |
1dbae815 | 25 | |
dbc04161 | 26 | #include "soc.h" |
ee0839c2 | 27 | #include "iomap.h" |
e2ed89fc | 28 | #include "common.h" |
2e7509e5 PW |
29 | |
30 | /* selected INTC register offsets */ | |
31 | ||
32 | #define INTC_REVISION 0x0000 | |
33 | #define INTC_SYSCONFIG 0x0010 | |
34 | #define INTC_SYSSTATUS 0x0014 | |
6ccc4c0d | 35 | #define INTC_SIR 0x0040 |
2e7509e5 | 36 | #define INTC_CONTROL 0x0048 |
0addd61b RN |
37 | #define INTC_PROTECTION 0x004C |
38 | #define INTC_IDLE 0x0050 | |
39 | #define INTC_THRESHOLD 0x0068 | |
40 | #define INTC_MIR0 0x0084 | |
2e7509e5 PW |
41 | #define INTC_MIR_CLEAR0 0x0088 |
42 | #define INTC_MIR_SET0 0x008c | |
43 | #define INTC_PENDING_IRQ0 0x0098 | |
11983656 FB |
44 | #define INTC_PENDING_IRQ1 0x00b8 |
45 | #define INTC_PENDING_IRQ2 0x00d8 | |
46 | #define INTC_PENDING_IRQ3 0x00f8 | |
33c7c7b7 | 47 | #define INTC_ILR0 0x0100 |
1dbae815 | 48 | |
2db14997 MZ |
49 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) |
50 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | |
2db14997 | 51 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
a88ab430 | 52 | #define INTCPS_NR_ILR_REGS 128 |
3003ce3e | 53 | #define INTCPS_NR_MIR_REGS 3 |
2db14997 | 54 | |
1dbae815 TL |
55 | /* |
56 | * OMAP2 has a number of different interrupt controllers, each interrupt | |
57 | * controller is identified as its own "bank". Register definitions are | |
58 | * fairly consistent for each bank, but not all registers are implemented | |
59 | * for each bank.. when in doubt, consult the TRM. | |
60 | */ | |
1dbae815 | 61 | |
52fa2120 | 62 | static struct irq_domain *domain; |
176da6c7 | 63 | static void __iomem *omap_irq_base; |
421b090c | 64 | static int omap_nr_irqs = 96; |
52fa2120 | 65 | |
0addd61b RN |
66 | /* Structure to save interrupt controller context */ |
67 | struct omap3_intc_regs { | |
68 | u32 sysconfig; | |
69 | u32 protection; | |
70 | u32 idle; | |
71 | u32 threshold; | |
a88ab430 | 72 | u32 ilr[INTCPS_NR_ILR_REGS]; |
0addd61b RN |
73 | u32 mir[INTCPS_NR_MIR_REGS]; |
74 | }; | |
75 | ||
2e7509e5 | 76 | /* INTC bank register get/set */ |
71be00c9 | 77 | static void intc_writel(u32 reg, u32 val) |
2e7509e5 | 78 | { |
71be00c9 | 79 | writel_relaxed(val, omap_irq_base + reg); |
2e7509e5 PW |
80 | } |
81 | ||
71be00c9 | 82 | static u32 intc_readl(u32 reg) |
2e7509e5 | 83 | { |
71be00c9 | 84 | return readl_relaxed(omap_irq_base + reg); |
2e7509e5 PW |
85 | } |
86 | ||
1dbae815 | 87 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
df303477 | 88 | static void omap_ack_irq(struct irq_data *d) |
1dbae815 | 89 | { |
71be00c9 | 90 | intc_writel(INTC_CONTROL, 0x1); |
1dbae815 TL |
91 | } |
92 | ||
df303477 | 93 | static void omap_mask_ack_irq(struct irq_data *d) |
1dbae815 | 94 | { |
667a11fa | 95 | irq_gc_mask_disable_reg(d); |
df303477 | 96 | omap_ack_irq(d); |
1dbae815 TL |
97 | } |
98 | ||
a88ab430 | 99 | static void __init omap_irq_soft_reset(void) |
1dbae815 TL |
100 | { |
101 | unsigned long tmp; | |
102 | ||
71be00c9 | 103 | tmp = intc_readl(INTC_REVISION) & 0xff; |
a88ab430 | 104 | |
7852ec05 | 105 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
a88ab430 | 106 | omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); |
1dbae815 | 107 | |
71be00c9 | 108 | tmp = intc_readl(INTC_SYSCONFIG); |
1dbae815 | 109 | tmp |= 1 << 1; /* soft reset */ |
71be00c9 | 110 | intc_writel(INTC_SYSCONFIG, tmp); |
1dbae815 | 111 | |
71be00c9 | 112 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
1dbae815 | 113 | /* Wait for reset to complete */; |
375e12ab JY |
114 | |
115 | /* Enable autoidle */ | |
71be00c9 | 116 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
1dbae815 TL |
117 | } |
118 | ||
94434535 JH |
119 | int omap_irq_pending(void) |
120 | { | |
a88ab430 | 121 | int irq; |
94434535 | 122 | |
a88ab430 FB |
123 | for (irq = 0; irq < omap_nr_irqs; irq += 32) |
124 | if (intc_readl(INTC_PENDING_IRQ0 + | |
125 | ((irq >> 5) << 5))) | |
126 | return 1; | |
94434535 JH |
127 | return 0; |
128 | } | |
129 | ||
667a11fa TL |
130 | static __init void |
131 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |
132 | { | |
133 | struct irq_chip_generic *gc; | |
134 | struct irq_chip_type *ct; | |
135 | ||
136 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, | |
137 | handle_level_irq); | |
138 | ct = gc->chip_types; | |
139 | ct->chip.irq_ack = omap_mask_ack_irq; | |
140 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
141 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
e3c83c2d | 142 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
667a11fa | 143 | |
667a11fa TL |
144 | ct->regs.enable = INTC_MIR_CLEAR0; |
145 | ct->regs.disable = INTC_MIR_SET0; | |
146 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
147 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
148 | } | |
149 | ||
52fa2120 BC |
150 | static void __init omap_init_irq(u32 base, int nr_irqs, |
151 | struct device_node *node) | |
1dbae815 | 152 | { |
a88ab430 | 153 | int j, irq_base; |
1dbae815 | 154 | |
741e3a89 TL |
155 | omap_irq_base = ioremap(base, SZ_4K); |
156 | if (WARN_ON(!omap_irq_base)) | |
157 | return; | |
158 | ||
421b090c FB |
159 | omap_nr_irqs = nr_irqs; |
160 | ||
52fa2120 BC |
161 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
162 | if (irq_base < 0) { | |
163 | pr_warn("Couldn't allocate IRQ numbers\n"); | |
164 | irq_base = 0; | |
165 | } | |
166 | ||
167 | domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | |
a88ab430 | 168 | &irq_domain_simple_ops, NULL); |
1dbae815 | 169 | |
a88ab430 | 170 | omap_irq_soft_reset(); |
667a11fa | 171 | |
a88ab430 FB |
172 | for (j = 0; j < omap_nr_irqs; j += 32) |
173 | omap_alloc_gc(omap_irq_base + j, j + irq_base, 32); | |
1dbae815 TL |
174 | } |
175 | ||
741e3a89 TL |
176 | void __init omap2_init_irq(void) |
177 | { | |
52fa2120 | 178 | omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); |
741e3a89 TL |
179 | } |
180 | ||
181 | void __init omap3_init_irq(void) | |
182 | { | |
52fa2120 | 183 | omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); |
741e3a89 TL |
184 | } |
185 | ||
a920360f | 186 | void __init ti81xx_init_irq(void) |
741e3a89 | 187 | { |
52fa2120 | 188 | omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); |
741e3a89 TL |
189 | } |
190 | ||
2db14997 MZ |
191 | static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) |
192 | { | |
193 | u32 irqnr; | |
698b4853 | 194 | int handled_irq = 0; |
2db14997 MZ |
195 | |
196 | do { | |
11983656 | 197 | irqnr = intc_readl(INTC_PENDING_IRQ0); |
2db14997 MZ |
198 | if (irqnr) |
199 | goto out; | |
200 | ||
11983656 | 201 | irqnr = intc_readl(INTC_PENDING_IRQ1); |
2db14997 MZ |
202 | if (irqnr) |
203 | goto out; | |
204 | ||
11983656 | 205 | irqnr = intc_readl(INTC_PENDING_IRQ2); |
0bebda68 | 206 | #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX) |
2db14997 MZ |
207 | if (irqnr) |
208 | goto out; | |
11983656 | 209 | irqnr = intc_readl(INTC_PENDING_IRQ3); |
2db14997 MZ |
210 | #endif |
211 | ||
212 | out: | |
213 | if (!irqnr) | |
214 | break; | |
215 | ||
11983656 | 216 | irqnr = intc_readl(INTC_SIR); |
2db14997 MZ |
217 | irqnr &= ACTIVEIRQ_MASK; |
218 | ||
52fa2120 BC |
219 | if (irqnr) { |
220 | irqnr = irq_find_mapping(domain, irqnr); | |
2db14997 | 221 | handle_IRQ(irqnr, regs); |
698b4853 | 222 | handled_irq = 1; |
52fa2120 | 223 | } |
2db14997 | 224 | } while (irqnr); |
698b4853 SS |
225 | |
226 | /* If an irq is masked or deasserted while active, we will | |
227 | * keep ending up here with no irq handled. So remove it from | |
228 | * the INTC with an ack.*/ | |
229 | if (!handled_irq) | |
230 | omap_ack_irq(NULL); | |
2db14997 MZ |
231 | } |
232 | ||
233 | asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) | |
234 | { | |
235 | void __iomem *base_addr = OMAP2_IRQ_BASE; | |
236 | omap_intc_handle_irq(base_addr, regs); | |
237 | } | |
238 | ||
c4082d49 | 239 | int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
240 | struct device_node *parent) |
241 | { | |
242 | struct resource res; | |
b56f2cb7 | 243 | u32 nr_irq = 96; |
52fa2120 BC |
244 | |
245 | if (WARN_ON(!node)) | |
246 | return -ENODEV; | |
247 | ||
248 | if (of_address_to_resource(node, 0, &res)) { | |
249 | WARN(1, "unable to get intc registers\n"); | |
250 | return -EINVAL; | |
251 | } | |
252 | ||
b56f2cb7 V |
253 | if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) |
254 | pr_warn("unable to get intc-size, default to %d\n", nr_irq); | |
52fa2120 | 255 | |
b56f2cb7 | 256 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
52fa2120 BC |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
31957609 | 261 | static const struct of_device_id irq_match[] __initconst = { |
c4082d49 S |
262 | { .compatible = "ti,omap2-intc", .data = intc_of_init, }, |
263 | { } | |
264 | }; | |
265 | ||
266 | void __init omap_intc_of_init(void) | |
267 | { | |
268 | of_irq_init(irq_match); | |
269 | } | |
270 | ||
08f30989 | 271 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
a88ab430 | 272 | static struct omap3_intc_regs intc_context; |
ee23b93d | 273 | |
0addd61b RN |
274 | void omap_intc_save_context(void) |
275 | { | |
a88ab430 FB |
276 | int i; |
277 | ||
278 | intc_context.sysconfig = | |
279 | intc_readl(INTC_SYSCONFIG); | |
280 | intc_context.protection = | |
281 | intc_readl(INTC_PROTECTION); | |
282 | intc_context.idle = | |
283 | intc_readl(INTC_IDLE); | |
284 | intc_context.threshold = | |
285 | intc_readl(INTC_THRESHOLD); | |
286 | ||
287 | for (i = 0; i < omap_nr_irqs; i++) | |
288 | intc_context.ilr[i] = | |
289 | intc_readl((INTC_ILR0 + 0x4 * i)); | |
290 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
291 | intc_context.mir[i] = | |
292 | intc_readl(INTC_MIR0 + (0x20 * i)); | |
0addd61b RN |
293 | } |
294 | ||
295 | void omap_intc_restore_context(void) | |
296 | { | |
a88ab430 FB |
297 | int i; |
298 | ||
299 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | |
300 | intc_writel(INTC_PROTECTION, intc_context.protection); | |
301 | intc_writel(INTC_IDLE, intc_context.idle); | |
302 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | |
303 | ||
304 | for (i = 0; i < omap_nr_irqs; i++) | |
305 | intc_writel(INTC_ILR0 + 0x4 * i, | |
306 | intc_context.ilr[i]); | |
307 | ||
308 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
309 | intc_writel(INTC_MIR0 + 0x20 * i, | |
310 | intc_context.mir[i]); | |
0addd61b RN |
311 | /* MIRs are saved and restore with other PRCM registers */ |
312 | } | |
2bbe3af3 TK |
313 | |
314 | void omap3_intc_suspend(void) | |
315 | { | |
316 | /* A pending interrupt would prevent OMAP from entering suspend */ | |
a7022d60 | 317 | omap_ack_irq(NULL); |
2bbe3af3 | 318 | } |
f18cc2ff TK |
319 | |
320 | void omap3_intc_prepare_idle(void) | |
321 | { | |
447b8da5 JP |
322 | /* |
323 | * Disable autoidle as it can stall interrupt controller, | |
324 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | |
325 | */ | |
71be00c9 | 326 | intc_writel(INTC_SYSCONFIG, 0); |
f18cc2ff TK |
327 | } |
328 | ||
329 | void omap3_intc_resume_idle(void) | |
330 | { | |
331 | /* Re-enable autoidle */ | |
71be00c9 | 332 | intc_writel(INTC_SYSCONFIG, 1); |
f18cc2ff | 333 | } |
2db14997 MZ |
334 | |
335 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) | |
336 | { | |
337 | void __iomem *base_addr = OMAP3_IRQ_BASE; | |
338 | omap_intc_handle_irq(base_addr, regs); | |
339 | } | |
0addd61b | 340 | #endif /* CONFIG_ARCH_OMAP3 */ |