Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/irq.c |
1dbae815 TL |
3 | * |
4 | * Interrupt handler for OMAP2 boards. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
52fa2120 | 14 | #include <linux/module.h> |
1dbae815 | 15 | #include <linux/init.h> |
1dbae815 | 16 | #include <linux/interrupt.h> |
2e7509e5 | 17 | #include <linux/io.h> |
ee0839c2 | 18 | |
2db14997 | 19 | #include <asm/exception.h> |
1dbae815 | 20 | #include <asm/mach/irq.h> |
52fa2120 BC |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
c4082d49 | 24 | #include <linux/of_irq.h> |
1dbae815 | 25 | |
dbc04161 | 26 | #include "soc.h" |
e2ed89fc | 27 | #include "common.h" |
b65ecd46 | 28 | #include "../../drivers/irqchip/irqchip.h" |
2e7509e5 PW |
29 | |
30 | /* selected INTC register offsets */ | |
31 | ||
32 | #define INTC_REVISION 0x0000 | |
33 | #define INTC_SYSCONFIG 0x0010 | |
34 | #define INTC_SYSSTATUS 0x0014 | |
6ccc4c0d | 35 | #define INTC_SIR 0x0040 |
2e7509e5 | 36 | #define INTC_CONTROL 0x0048 |
0addd61b RN |
37 | #define INTC_PROTECTION 0x004C |
38 | #define INTC_IDLE 0x0050 | |
39 | #define INTC_THRESHOLD 0x0068 | |
40 | #define INTC_MIR0 0x0084 | |
2e7509e5 PW |
41 | #define INTC_MIR_CLEAR0 0x0088 |
42 | #define INTC_MIR_SET0 0x008c | |
43 | #define INTC_PENDING_IRQ0 0x0098 | |
11983656 FB |
44 | #define INTC_PENDING_IRQ1 0x00b8 |
45 | #define INTC_PENDING_IRQ2 0x00d8 | |
46 | #define INTC_PENDING_IRQ3 0x00f8 | |
33c7c7b7 | 47 | #define INTC_ILR0 0x0100 |
1dbae815 | 48 | |
2db14997 | 49 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
a88ab430 | 50 | #define INTCPS_NR_ILR_REGS 128 |
3003ce3e | 51 | #define INTCPS_NR_MIR_REGS 3 |
2db14997 | 52 | |
1dbae815 TL |
53 | /* |
54 | * OMAP2 has a number of different interrupt controllers, each interrupt | |
55 | * controller is identified as its own "bank". Register definitions are | |
56 | * fairly consistent for each bank, but not all registers are implemented | |
57 | * for each bank.. when in doubt, consult the TRM. | |
58 | */ | |
1dbae815 | 59 | |
0addd61b | 60 | /* Structure to save interrupt controller context */ |
272a8b04 | 61 | struct omap_intc_regs { |
0addd61b RN |
62 | u32 sysconfig; |
63 | u32 protection; | |
64 | u32 idle; | |
65 | u32 threshold; | |
a88ab430 | 66 | u32 ilr[INTCPS_NR_ILR_REGS]; |
0addd61b RN |
67 | u32 mir[INTCPS_NR_MIR_REGS]; |
68 | }; | |
131b48c0 FB |
69 | static struct omap_intc_regs intc_context; |
70 | ||
71 | static struct irq_domain *domain; | |
72 | static void __iomem *omap_irq_base; | |
73 | static int omap_nr_irqs = 96; | |
0addd61b | 74 | |
2e7509e5 | 75 | /* INTC bank register get/set */ |
71be00c9 | 76 | static void intc_writel(u32 reg, u32 val) |
2e7509e5 | 77 | { |
71be00c9 | 78 | writel_relaxed(val, omap_irq_base + reg); |
2e7509e5 PW |
79 | } |
80 | ||
71be00c9 | 81 | static u32 intc_readl(u32 reg) |
2e7509e5 | 82 | { |
71be00c9 | 83 | return readl_relaxed(omap_irq_base + reg); |
2e7509e5 PW |
84 | } |
85 | ||
131b48c0 FB |
86 | void omap_intc_save_context(void) |
87 | { | |
88 | int i; | |
89 | ||
90 | intc_context.sysconfig = | |
91 | intc_readl(INTC_SYSCONFIG); | |
92 | intc_context.protection = | |
93 | intc_readl(INTC_PROTECTION); | |
94 | intc_context.idle = | |
95 | intc_readl(INTC_IDLE); | |
96 | intc_context.threshold = | |
97 | intc_readl(INTC_THRESHOLD); | |
98 | ||
99 | for (i = 0; i < omap_nr_irqs; i++) | |
100 | intc_context.ilr[i] = | |
101 | intc_readl((INTC_ILR0 + 0x4 * i)); | |
102 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
103 | intc_context.mir[i] = | |
104 | intc_readl(INTC_MIR0 + (0x20 * i)); | |
105 | } | |
106 | ||
107 | void omap_intc_restore_context(void) | |
108 | { | |
109 | int i; | |
110 | ||
111 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | |
112 | intc_writel(INTC_PROTECTION, intc_context.protection); | |
113 | intc_writel(INTC_IDLE, intc_context.idle); | |
114 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | |
115 | ||
116 | for (i = 0; i < omap_nr_irqs; i++) | |
117 | intc_writel(INTC_ILR0 + 0x4 * i, | |
118 | intc_context.ilr[i]); | |
119 | ||
120 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | |
121 | intc_writel(INTC_MIR0 + 0x20 * i, | |
122 | intc_context.mir[i]); | |
123 | /* MIRs are saved and restore with other PRCM registers */ | |
124 | } | |
125 | ||
126 | void omap3_intc_prepare_idle(void) | |
127 | { | |
128 | /* | |
129 | * Disable autoidle as it can stall interrupt controller, | |
130 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | |
131 | */ | |
132 | intc_writel(INTC_SYSCONFIG, 0); | |
133 | } | |
134 | ||
135 | void omap3_intc_resume_idle(void) | |
136 | { | |
137 | /* Re-enable autoidle */ | |
138 | intc_writel(INTC_SYSCONFIG, 1); | |
139 | } | |
140 | ||
1dbae815 | 141 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
df303477 | 142 | static void omap_ack_irq(struct irq_data *d) |
1dbae815 | 143 | { |
71be00c9 | 144 | intc_writel(INTC_CONTROL, 0x1); |
1dbae815 TL |
145 | } |
146 | ||
df303477 | 147 | static void omap_mask_ack_irq(struct irq_data *d) |
1dbae815 | 148 | { |
667a11fa | 149 | irq_gc_mask_disable_reg(d); |
df303477 | 150 | omap_ack_irq(d); |
1dbae815 TL |
151 | } |
152 | ||
a88ab430 | 153 | static void __init omap_irq_soft_reset(void) |
1dbae815 TL |
154 | { |
155 | unsigned long tmp; | |
156 | ||
71be00c9 | 157 | tmp = intc_readl(INTC_REVISION) & 0xff; |
a88ab430 | 158 | |
7852ec05 | 159 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
a88ab430 | 160 | omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); |
1dbae815 | 161 | |
71be00c9 | 162 | tmp = intc_readl(INTC_SYSCONFIG); |
1dbae815 | 163 | tmp |= 1 << 1; /* soft reset */ |
71be00c9 | 164 | intc_writel(INTC_SYSCONFIG, tmp); |
1dbae815 | 165 | |
71be00c9 | 166 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
1dbae815 | 167 | /* Wait for reset to complete */; |
375e12ab JY |
168 | |
169 | /* Enable autoidle */ | |
71be00c9 | 170 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
1dbae815 TL |
171 | } |
172 | ||
94434535 JH |
173 | int omap_irq_pending(void) |
174 | { | |
a88ab430 | 175 | int irq; |
94434535 | 176 | |
a88ab430 FB |
177 | for (irq = 0; irq < omap_nr_irqs; irq += 32) |
178 | if (intc_readl(INTC_PENDING_IRQ0 + | |
179 | ((irq >> 5) << 5))) | |
180 | return 1; | |
94434535 JH |
181 | return 0; |
182 | } | |
183 | ||
131b48c0 FB |
184 | void omap3_intc_suspend(void) |
185 | { | |
186 | /* A pending interrupt would prevent OMAP from entering suspend */ | |
187 | omap_ack_irq(NULL); | |
188 | } | |
189 | ||
667a11fa TL |
190 | static __init void |
191 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |
192 | { | |
193 | struct irq_chip_generic *gc; | |
194 | struct irq_chip_type *ct; | |
195 | ||
196 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, | |
197 | handle_level_irq); | |
198 | ct = gc->chip_types; | |
199 | ct->chip.irq_ack = omap_mask_ack_irq; | |
200 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | |
201 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | |
e3c83c2d | 202 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
667a11fa | 203 | |
667a11fa TL |
204 | ct->regs.enable = INTC_MIR_CLEAR0; |
205 | ct->regs.disable = INTC_MIR_SET0; | |
206 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
207 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
208 | } | |
209 | ||
52fa2120 BC |
210 | static void __init omap_init_irq(u32 base, int nr_irqs, |
211 | struct device_node *node) | |
1dbae815 | 212 | { |
a88ab430 | 213 | int j, irq_base; |
1dbae815 | 214 | |
741e3a89 TL |
215 | omap_irq_base = ioremap(base, SZ_4K); |
216 | if (WARN_ON(!omap_irq_base)) | |
217 | return; | |
218 | ||
421b090c FB |
219 | omap_nr_irqs = nr_irqs; |
220 | ||
52fa2120 BC |
221 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
222 | if (irq_base < 0) { | |
223 | pr_warn("Couldn't allocate IRQ numbers\n"); | |
224 | irq_base = 0; | |
225 | } | |
226 | ||
227 | domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | |
a88ab430 | 228 | &irq_domain_simple_ops, NULL); |
1dbae815 | 229 | |
a88ab430 | 230 | omap_irq_soft_reset(); |
667a11fa | 231 | |
a88ab430 FB |
232 | for (j = 0; j < omap_nr_irqs; j += 32) |
233 | omap_alloc_gc(omap_irq_base + j, j + irq_base, 32); | |
1dbae815 TL |
234 | } |
235 | ||
2aced892 FB |
236 | static asmlinkage void __exception_irq_entry |
237 | omap_intc_handle_irq(struct pt_regs *regs) | |
2db14997 MZ |
238 | { |
239 | u32 irqnr; | |
698b4853 | 240 | int handled_irq = 0; |
2db14997 MZ |
241 | |
242 | do { | |
11983656 | 243 | irqnr = intc_readl(INTC_PENDING_IRQ0); |
2db14997 MZ |
244 | if (irqnr) |
245 | goto out; | |
246 | ||
11983656 | 247 | irqnr = intc_readl(INTC_PENDING_IRQ1); |
2db14997 MZ |
248 | if (irqnr) |
249 | goto out; | |
250 | ||
11983656 | 251 | irqnr = intc_readl(INTC_PENDING_IRQ2); |
0bebda68 | 252 | #if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX) |
2db14997 MZ |
253 | if (irqnr) |
254 | goto out; | |
11983656 | 255 | irqnr = intc_readl(INTC_PENDING_IRQ3); |
2db14997 MZ |
256 | #endif |
257 | ||
258 | out: | |
259 | if (!irqnr) | |
260 | break; | |
261 | ||
11983656 | 262 | irqnr = intc_readl(INTC_SIR); |
2db14997 MZ |
263 | irqnr &= ACTIVEIRQ_MASK; |
264 | ||
52fa2120 BC |
265 | if (irqnr) { |
266 | irqnr = irq_find_mapping(domain, irqnr); | |
2db14997 | 267 | handle_IRQ(irqnr, regs); |
698b4853 | 268 | handled_irq = 1; |
52fa2120 | 269 | } |
2db14997 | 270 | } while (irqnr); |
698b4853 SS |
271 | |
272 | /* If an irq is masked or deasserted while active, we will | |
273 | * keep ending up here with no irq handled. So remove it from | |
274 | * the INTC with an ack.*/ | |
275 | if (!handled_irq) | |
276 | omap_ack_irq(NULL); | |
2db14997 MZ |
277 | } |
278 | ||
a4d3c5d9 FB |
279 | void __init omap2_init_irq(void) |
280 | { | |
281 | omap_init_irq(OMAP24XX_IC_BASE, 96, NULL); | |
2aced892 | 282 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
283 | } |
284 | ||
285 | void __init omap3_init_irq(void) | |
286 | { | |
287 | omap_init_irq(OMAP34XX_IC_BASE, 96, NULL); | |
2aced892 | 288 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
289 | } |
290 | ||
291 | void __init ti81xx_init_irq(void) | |
292 | { | |
293 | omap_init_irq(OMAP34XX_IC_BASE, 128, NULL); | |
2aced892 | 294 | set_handle_irq(omap_intc_handle_irq); |
a4d3c5d9 FB |
295 | } |
296 | ||
00b6b031 | 297 | static int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
298 | struct device_node *parent) |
299 | { | |
300 | struct resource res; | |
b56f2cb7 | 301 | u32 nr_irq = 96; |
52fa2120 BC |
302 | |
303 | if (WARN_ON(!node)) | |
304 | return -ENODEV; | |
305 | ||
306 | if (of_address_to_resource(node, 0, &res)) { | |
307 | WARN(1, "unable to get intc registers\n"); | |
308 | return -EINVAL; | |
309 | } | |
310 | ||
470f30de FB |
311 | if (of_device_is_compatible(node, "ti,am33xx-intc")) |
312 | nr_irq = 128; | |
313 | ||
b56f2cb7 | 314 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
52fa2120 | 315 | |
2aced892 | 316 | set_handle_irq(omap_intc_handle_irq); |
b15c76b7 | 317 | |
52fa2120 BC |
318 | return 0; |
319 | } | |
320 | ||
a35db9a4 FB |
321 | IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); |
322 | IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); | |
323 | IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); |