[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_ILR0		0x0100
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32

#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
#define INTCPS_NR_MIR_REGS	3
#define INTCPS_NR_IRQS		96

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

static struct irq_domain *domain;
static void __iomem *omap_irq_base;
static int omap_nr_irqs = 96;

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */
static void intc_writel(u32 reg, u32 val)
{
	writel_relaxed(val, omap_irq_base + reg);
}

static u32 intc_readl(u32 reg)
{
	return readl_relaxed(omap_irq_base + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_writel(INTC_CONTROL, 0x1);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_readl(INTC_REVISION) & 0xff;
	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
		bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_readl(INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_writel(INTC_SYSCONFIG, tmp);

	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1 << 0);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_readl(INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static void __init omap_init_irq(u32 base, int nr_irqs,
				 struct device_node *node)
{
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return;

	omap_nr_irqs = nr_irqs;

	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
				       &irq_domain_simple_ops, NULL);

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		bank->nr_irqs = nr_irqs;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			pr_err("Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (j = 0; j < bank->nr_irqs; j += 32)
			omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	pr_info("Total of %ld interrupts on %d active controller%s\n",
		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

void __init omap2_init_irq(void)
{
	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
}

void __init omap3_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
}

void __init ti81xx_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
}

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
	u32 irqnr;
	int handled_irq = 0;

	do {
		irqnr = readl_relaxed(base_addr + 0x98);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xb8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xd8);
#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
		if (irqnr)
			goto out;
		irqnr = readl_relaxed(base_addr + 0xf8);
#endif

out:
		if (!irqnr)
			break;

		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
			irqnr = irq_find_mapping(domain, irqnr);
			handle_IRQ(irqnr, regs);
			handled_irq = 1;
		}
	} while (irqnr);

	/* If an irq is masked or deasserted while active, we will
	 * keep ending up here with no irq handled. So remove it from
	 * the INTC with an ack.*/
	if (!handled_irq)
		omap_ack_irq(NULL);
}

asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP2_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}

int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	struct resource res;
	u32 nr_irq = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_address_to_resource(node, 0, &res)) {
		WARN(1, "unable to get intc registers\n");
		return -EINVAL;
	}

	if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
		pr_warn("unable to get intc-size, default to %d\n", nr_irq);

	omap_init_irq(res.start, nr_irq, of_node_get(node));

	return 0;
}

static const struct of_device_id irq_match[] __initconst = {
	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
	{ }
};

void __init omap_intc_of_init(void)
{
	of_irq_init(irq_match);
}

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		intc_context[ind].sysconfig =
			intc_readl(INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_readl(INTC_PROTECTION);
		intc_context[ind].idle =
			intc_readl(INTC_IDLE);
		intc_context[ind].threshold =
			intc_readl(INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_readl((INTC_ILR0 + 0x4 * i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_readl(INTC_MIR0 + (0x20 * i));
	}
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		intc_writel(INTC_SYSCONFIG, intc_context[ind].sysconfig);
		intc_writel(INTC_PROTECTION, intc_context[ind].protection);
		intc_writel(INTC_IDLE, intc_context[ind].idle);
		intc_writel(INTC_THRESHOLD, intc_context[ind].threshold);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_writel(INTC_ILR0 + 0x4 * i,
					intc_context[ind].ilr[i]);
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_writel(INTC_MIR0 + 0x20 * i,
				intc_context[ind].mir[i]);
	}
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_writel(INTC_SYSCONFIG, 0);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1);
}

asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP3_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}
#endif /* CONFIG_ARCH_OMAP3 */
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
1dbae815	20	#include <asm/mach/irq.h>
52fa2120 BC	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
c4082d49	24	#include <linux/of_irq.h>
1dbae815	25
dbc04161	26	#include "soc.h"
ee0839c2	27	#include "iomap.h"
e2ed89fc	28	#include "common.h"
2e7509e5 PW	29
	30	/* selected INTC register offsets */
	31
	32	#define INTC_REVISION 0x0000
	33	#define INTC_SYSCONFIG 0x0010
	34	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	35	#define INTC_SIR 0x0040
2e7509e5	36	#define INTC_CONTROL 0x0048
0addd61b RN	37	#define INTC_PROTECTION 0x004C
	38	#define INTC_IDLE 0x0050
	39	#define INTC_THRESHOLD 0x0068
	40	#define INTC_MIR0 0x0084
2e7509e5 PW	41	#define INTC_MIR_CLEAR0 0x0088
	42	#define INTC_MIR_SET0 0x008c
	43	#define INTC_PENDING_IRQ0 0x0098
33c7c7b7	44	#define INTC_ILR0 0x0100
2e7509e5 PW	45	/* Number of IRQ state bits in each MIR register */
2e7509e5 PW	46	#define IRQ_BITS_PER_REG 32
1dbae815	47
2db14997 MZ	48	#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
	49	#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
	50	#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
	51	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
3003ce3e TL	52	#define INTCPS_NR_MIR_REGS 3
3003ce3e TL	53	#define INTCPS_NR_IRQS 96
2db14997	54
1dbae815 TL	55	/*
	56	* OMAP2 has a number of different interrupt controllers, each interrupt
	57	* controller is identified as its own "bank". Register definitions are
	58	* fairly consistent for each bank, but not all registers are implemented
	59	* for each bank.. when in doubt, consult the TRM.
	60	*/
	61	static struct omap_irq_bank {
e8a91c95	62	void __iomem *base_reg;
1dbae815 TL	63	unsigned int nr_irqs;
	64	} __attribute__ ((aligned(4))) irq_banks[] = {
	65	{
	66	/* MPU INTC */
1dbae815	67	.nr_irqs = 96,
646e3ed1	68	},
1dbae815 TL	69	};
1dbae815 TL	70
52fa2120	71	static struct irq_domain *domain;
176da6c7	72	static void __iomem *omap_irq_base;
421b090c	73	static int omap_nr_irqs = 96;
52fa2120	74
0addd61b RN	75	/* Structure to save interrupt controller context */
	76	struct omap3_intc_regs {
	77	u32 sysconfig;
	78	u32 protection;
	79	u32 idle;
	80	u32 threshold;
	81	u32 ilr[INTCPS_NR_IRQS];
	82	u32 mir[INTCPS_NR_MIR_REGS];
	83	};
	84
2e7509e5	85	/* INTC bank register get/set */
71be00c9	86	static void intc_writel(u32 reg, u32 val)
2e7509e5	87	{
71be00c9	88	writel_relaxed(val, omap_irq_base + reg);
2e7509e5 PW	89	}
2e7509e5 PW	90
71be00c9	91	static u32 intc_readl(u32 reg)
2e7509e5	92	{
71be00c9	93	return readl_relaxed(omap_irq_base + reg);
2e7509e5 PW	94	}
2e7509e5 PW	95
1dbae815	96	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	97	static void omap_ack_irq(struct irq_data *d)
1dbae815	98	{
71be00c9	99	intc_writel(INTC_CONTROL, 0x1);
1dbae815 TL	100	}
1dbae815 TL	101
df303477	102	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	103	{
667a11fa	104	irq_gc_mask_disable_reg(d);
df303477	105	omap_ack_irq(d);
1dbae815 TL	106	}
1dbae815 TL	107
1dbae815 TL	108	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	109	{
	110	unsigned long tmp;
	111
71be00c9	112	tmp = intc_readl(INTC_REVISION) & 0xff;
7852ec05 PW	113	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
7852ec05 PW	114	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
1dbae815	115
71be00c9	116	tmp = intc_readl(INTC_SYSCONFIG);
1dbae815	117	tmp \|= 1 << 1; /* soft reset */
71be00c9	118	intc_writel(INTC_SYSCONFIG, tmp);
1dbae815	119
71be00c9	120	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
1dbae815	121	/* Wait for reset to complete */;
375e12ab JY	122
375e12ab JY	123	/* Enable autoidle */
71be00c9	124	intc_writel(INTC_SYSCONFIG, 1 << 0);
1dbae815 TL	125	}
1dbae815 TL	126
94434535 JH	127	int omap_irq_pending(void)
	128	{
	129	int i;
	130
	131	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	132	struct omap_irq_bank *bank = irq_banks + i;
	133	int irq;
	134
	135	for (irq = 0; irq < bank->nr_irqs; irq += 32)
71be00c9	136	if (intc_readl(INTC_PENDING_IRQ0 +
94434535 JH	137	((irq >> 5) << 5)))
	138	return 1;
	139	}
	140	return 0;
	141	}
	142
667a11fa TL	143	static __init void
	144	omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
	145	{
	146	struct irq_chip_generic *gc;
	147	struct irq_chip_type *ct;
	148
	149	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
	150	handle_level_irq);
	151	ct = gc->chip_types;
	152	ct->chip.irq_ack = omap_mask_ack_irq;
	153	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	154	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
e3c83c2d	155	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
667a11fa	156
667a11fa TL	157	ct->regs.enable = INTC_MIR_CLEAR0;
	158	ct->regs.disable = INTC_MIR_SET0;
	159	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	160	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	161	}
	162
52fa2120 BC	163	static void __init omap_init_irq(u32 base, int nr_irqs,
52fa2120 BC	164	struct device_node *node)
1dbae815	165	{
4b1135a2	166	unsigned long nr_of_irqs = 0;
1dbae815	167	unsigned int nr_banks = 0;
52fa2120	168	int i, j, irq_base;
1dbae815	169
741e3a89 TL	170	omap_irq_base = ioremap(base, SZ_4K);
	171	if (WARN_ON(!omap_irq_base))
	172	return;
	173
421b090c FB	174	omap_nr_irqs = nr_irqs;
421b090c FB	175
52fa2120 BC	176	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	177	if (irq_base < 0) {
	178	pr_warn("Couldn't allocate IRQ numbers\n");
	179	irq_base = 0;
	180	}
	181
	182	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
	183	&irq_domain_simple_ops, NULL);
	184
1dbae815 TL	185	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	186	struct omap_irq_bank *bank = irq_banks + i;
	187
741e3a89	188	bank->nr_irqs = nr_irqs;
01001712	189
1b26fe86 TL	190	/* Static mapping, never released */
	191	bank->base_reg = ioremap(base, SZ_4K);
	192	if (!bank->base_reg) {
52fa2120	193	pr_err("Could not ioremap irq bank%i\n", i);
1b26fe86 TL	194	continue;
1b26fe86 TL	195	}
2e7509e5	196
1dbae815 TL	197	omap_irq_bank_init_one(bank);
1dbae815 TL	198
5c30cdfa	199	for (j = 0; j < bank->nr_irqs; j += 32)
52fa2120	200	omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
667a11fa	201
4b1135a2	202	nr_of_irqs += bank->nr_irqs;
1dbae815 TL	203	nr_banks++;
	204	}
	205
52fa2120 BC	206	pr_info("Total of %ld interrupts on %d active controller%s\n",
52fa2120 BC	207	nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
1dbae815 TL	208	}
1dbae815 TL	209
741e3a89 TL	210	void __init omap2_init_irq(void)
741e3a89 TL	211	{
52fa2120	212	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
741e3a89 TL	213	}
	214
	215	void __init omap3_init_irq(void)
	216	{
52fa2120	217	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
741e3a89 TL	218	}
741e3a89 TL	219
a920360f	220	void __init ti81xx_init_irq(void)
741e3a89	221	{
52fa2120	222	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
741e3a89 TL	223	}
741e3a89 TL	224
2db14997 MZ	225	static inline void omap_intc_handle_irq(void __iomem base_addr, struct pt_regs regs)
	226	{
	227	u32 irqnr;
698b4853	228	int handled_irq = 0;
2db14997 MZ	229
	230	do {
	231	irqnr = readl_relaxed(base_addr + 0x98);
	232	if (irqnr)
	233	goto out;
	234
	235	irqnr = readl_relaxed(base_addr + 0xb8);
	236	if (irqnr)
	237	goto out;
	238
	239	irqnr = readl_relaxed(base_addr + 0xd8);
0bebda68	240	#if IS_ENABLED(CONFIG_SOC_TI81XX) \|\| IS_ENABLED(CONFIG_SOC_AM33XX)
2db14997 MZ	241	if (irqnr)
	242	goto out;
	243	irqnr = readl_relaxed(base_addr + 0xf8);
	244	#endif
	245
	246	out:
	247	if (!irqnr)
	248	break;
	249
	250	irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
	251	irqnr &= ACTIVEIRQ_MASK;
	252
52fa2120 BC	253	if (irqnr) {
52fa2120 BC	254	irqnr = irq_find_mapping(domain, irqnr);
2db14997	255	handle_IRQ(irqnr, regs);
698b4853	256	handled_irq = 1;
52fa2120	257	}
2db14997	258	} while (irqnr);
698b4853 SS	259
	260	/* If an irq is masked or deasserted while active, we will
	261	* keep ending up here with no irq handled. So remove it from
	262	* the INTC with an ack.*/
	263	if (!handled_irq)
	264	omap_ack_irq(NULL);
2db14997 MZ	265	}
	266
	267	asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
	268	{
	269	void __iomem *base_addr = OMAP2_IRQ_BASE;
	270	omap_intc_handle_irq(base_addr, regs);
	271	}
	272
c4082d49	273	int __init intc_of_init(struct device_node *node,
52fa2120 BC	274	struct device_node *parent)
	275	{
	276	struct resource res;
b56f2cb7	277	u32 nr_irq = 96;
52fa2120 BC	278
	279	if (WARN_ON(!node))
	280	return -ENODEV;
	281
	282	if (of_address_to_resource(node, 0, &res)) {
	283	WARN(1, "unable to get intc registers\n");
	284	return -EINVAL;
	285	}
	286
b56f2cb7 V	287	if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
b56f2cb7 V	288	pr_warn("unable to get intc-size, default to %d\n", nr_irq);
52fa2120	289
b56f2cb7	290	omap_init_irq(res.start, nr_irq, of_node_get(node));
52fa2120 BC	291
	292	return 0;
	293	}
	294
31957609	295	static const struct of_device_id irq_match[] __initconst = {
c4082d49 S	296	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
	297	{ }
	298	};
	299
	300	void __init omap_intc_of_init(void)
	301	{
	302	of_irq_init(irq_match);
	303	}
	304
08f30989	305	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_SOC_AM33XX)
ee23b93d FB	306	static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
ee23b93d FB	307
0addd61b RN	308	void omap_intc_save_context(void)
	309	{
	310	int ind = 0, i = 0;
	311	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
0addd61b	312	intc_context[ind].sysconfig =
71be00c9	313	intc_readl(INTC_SYSCONFIG);
0addd61b	314	intc_context[ind].protection =
71be00c9	315	intc_readl(INTC_PROTECTION);
0addd61b	316	intc_context[ind].idle =
71be00c9	317	intc_readl(INTC_IDLE);
0addd61b	318	intc_context[ind].threshold =
71be00c9	319	intc_readl(INTC_THRESHOLD);
0addd61b RN	320	for (i = 0; i < INTCPS_NR_IRQS; i++)
0addd61b RN	321	intc_context[ind].ilr[i] =
71be00c9	322	intc_readl((INTC_ILR0 + 0x4 * i));
0addd61b RN	323	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
0addd61b RN	324	intc_context[ind].mir[i] =
71be00c9	325	intc_readl(INTC_MIR0 + (0x20 * i));
0addd61b RN	326	}
	327	}
	328
	329	void omap_intc_restore_context(void)
	330	{
	331	int ind = 0, i = 0;
	332
	333	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
71be00c9 FB	334	intc_writel(INTC_SYSCONFIG, intc_context[ind].sysconfig);
	335	intc_writel(INTC_PROTECTION, intc_context[ind].protection);
	336	intc_writel(INTC_IDLE, intc_context[ind].idle);
	337	intc_writel(INTC_THRESHOLD, intc_context[ind].threshold);
0addd61b	338	for (i = 0; i < INTCPS_NR_IRQS; i++)
71be00c9 FB	339	intc_writel(INTC_ILR0 + 0x4 * i,
71be00c9 FB	340	intc_context[ind].ilr[i]);
0addd61b	341	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
71be00c9 FB	342	intc_writel(INTC_MIR0 + 0x20 * i,
71be00c9 FB	343	intc_context[ind].mir[i]);
0addd61b RN	344	}
	345	/* MIRs are saved and restore with other PRCM registers */
	346	}
2bbe3af3 TK	347
	348	void omap3_intc_suspend(void)
	349	{
	350	/* A pending interrupt would prevent OMAP from entering suspend */
a7022d60	351	omap_ack_irq(NULL);
2bbe3af3	352	}
f18cc2ff TK	353
	354	void omap3_intc_prepare_idle(void)
	355	{
447b8da5 JP	356	/*
	357	* Disable autoidle as it can stall interrupt controller,
	358	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	359	*/
71be00c9	360	intc_writel(INTC_SYSCONFIG, 0);
f18cc2ff TK	361	}
	362
	363	void omap3_intc_resume_idle(void)
	364	{
	365	/* Re-enable autoidle */
71be00c9	366	intc_writel(INTC_SYSCONFIG, 1);
f18cc2ff	367	}
2db14997 MZ	368
	369	asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
	370	{
	371	void __iomem *base_addr = OMAP3_IRQ_BASE;
	372	omap_intc_handle_irq(base_addr, regs);
	373	}
0addd61b	374	#endif /* CONFIG_ARCH_OMAP3 */