[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <mach/hardware.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/io.h>

#define INTC_REVISION	0x0000
#define INTC_SYSCONFIG	0x0010
#define INTC_SYSSTATUS	0x0014
#define INTC_CONTROL	0x0048
#define INTC_MIR_CLEAR0	0x0088
#define INTC_MIR_SET0	0x008c

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.base_reg	= 0,
		.nr_irqs	= 96,
	},
};

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(unsigned int irq)
{
	__raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
}

static void omap_mask_irq(unsigned int irq)
{
	int offset = (irq >> 5) << 5;

	if (irq >= 64) {
		irq %= 64;
	} else if (irq >= 32) {
		irq %= 32;
	}

	__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
}

static void omap_unmask_irq(unsigned int irq)
{
	int offset = (irq >> 5) << 5;

	if (irq >= 64) {
		irq %= 64;
	} else if (irq >= 32) {
		irq %= 32;
	}

	__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
}

static void omap_mask_ack_irq(unsigned int irq)
{
	omap_mask_irq(irq);
	omap_ack_irq(irq);
}

static struct irq_chip omap_irq_chip = {
	.name	= "INTC",
	.ack	= omap_mask_ack_irq,
	.mask	= omap_mask_irq,
	.unmask	= omap_unmask_irq,
};

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	__raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);

	while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	__raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
}

void __init omap_init_irq(void)
{
	unsigned long nr_irqs = 0;
	unsigned int nr_banks = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		if (cpu_is_omap24xx())
			bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE);
		omap_irq_bank_init_one(bank);

		nr_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");

	for (i = 0; i < nr_irqs; i++) {
		set_irq_chip(i, &omap_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
1dbae815	15	#include <linux/interrupt.h>
a09e64fb	16	#include <mach/hardware.h>
1dbae815 TL	17	#include <asm/mach/irq.h>
	18	#include <asm/irq.h>
	19	#include <asm/io.h>
	20
	21	#define INTC_REVISION 0x0000
	22	#define INTC_SYSCONFIG 0x0010
	23	#define INTC_SYSSTATUS 0x0014
	24	#define INTC_CONTROL 0x0048
	25	#define INTC_MIR_CLEAR0 0x0088
	26	#define INTC_MIR_SET0 0x008c
	27
	28	/*
	29	* OMAP2 has a number of different interrupt controllers, each interrupt
	30	* controller is identified as its own "bank". Register definitions are
	31	* fairly consistent for each bank, but not all registers are implemented
	32	* for each bank.. when in doubt, consult the TRM.
	33	*/
	34	static struct omap_irq_bank {
e8a91c95	35	void __iomem *base_reg;
1dbae815 TL	36	unsigned int nr_irqs;
	37	} __attribute__ ((aligned(4))) irq_banks[] = {
	38	{
	39	/* MPU INTC */
646e3ed1	40	.base_reg = 0,
1dbae815	41	.nr_irqs = 96,
646e3ed1	42	},
1dbae815 TL	43	};
	44
	45	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
	46	static void omap_ack_irq(unsigned int irq)
	47	{
375e12ab	48	__raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
1dbae815 TL	49	}
	50
	51	static void omap_mask_irq(unsigned int irq)
	52	{
	53	int offset = (irq >> 5) << 5;
	54
	55	if (irq >= 64) {
	56	irq %= 64;
	57	} else if (irq >= 32) {
	58	irq %= 32;
	59	}
	60
375e12ab	61	__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
1dbae815 TL	62	}
	63
	64	static void omap_unmask_irq(unsigned int irq)
	65	{
	66	int offset = (irq >> 5) << 5;
	67
	68	if (irq >= 64) {
	69	irq %= 64;
	70	} else if (irq >= 32) {
	71	irq %= 32;
	72	}
	73
375e12ab	74	__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
1dbae815 TL	75	}
	76
	77	static void omap_mask_ack_irq(unsigned int irq)
	78	{
	79	omap_mask_irq(irq);
	80	omap_ack_irq(irq);
	81	}
	82
38c677cb DB	83	static struct irq_chip omap_irq_chip = {
38c677cb DB	84	.name = "INTC",
1dbae815 TL	85	.ack = omap_mask_ack_irq,
	86	.mask = omap_mask_irq,
	87	.unmask = omap_unmask_irq,
	88	};
	89
	90	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	91	{
	92	unsigned long tmp;
	93
375e12ab	94	tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
e8a91c95	95	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
1dbae815 TL	96	"(revision %ld.%ld) with %d interrupts\n",
	97	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
	98
375e12ab	99	tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
1dbae815	100	tmp \|= 1 << 1; /* soft reset */
375e12ab	101	__raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
1dbae815	102
375e12ab	103	while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
1dbae815	104	/* Wait for reset to complete */;
375e12ab JY	105
	106	/* Enable autoidle */
	107	__raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
1dbae815 TL	108	}
	109
	110	void __init omap_init_irq(void)
	111	{
	112	unsigned long nr_irqs = 0;
	113	unsigned int nr_banks = 0;
	114	int i;
	115
	116	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	117	struct omap_irq_bank *bank = irq_banks + i;
	118
646e3ed1 TL	119	if (cpu_is_omap24xx())
646e3ed1 TL	120	bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE);
1dbae815 TL	121	omap_irq_bank_init_one(bank);
	122
	123	nr_irqs += bank->nr_irqs;
	124	nr_banks++;
	125	}
	126
	127	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	128	nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
	129
	130	for (i = 0; i < nr_irqs; i++) {
	131	set_irq_chip(i, &omap_irq_chip);
10dd5ce2	132	set_irq_handler(i, handle_level_irq);
1dbae815 TL	133	set_irq_flags(i, IRQF_VALID);
	134	}
	135	}
	136