[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach/irq.h>


/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

	ct->regs.ack = INTC_CONTROL;
	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

void __init omap_init_irq(void)
{
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		unsigned long base = 0;
		struct omap_irq_bank *bank = irq_banks + i;

		if (cpu_is_omap24xx())
			base = OMAP24XX_IC_BASE;
		else if (cpu_is_omap34xx())
			base = OMAP34XX_IC_BASE;

		BUG_ON(!base);

		if (cpu_is_ti816x())
			bank->nr_irqs = 128;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
			omap_alloc_gc(bank->base_reg + j, i, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
#endif /* CONFIG_ARCH_OMAP3 */
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
1dbae815	15	#include <linux/interrupt.h>
2e7509e5	16	#include <linux/io.h>
a09e64fb	17	#include <mach/hardware.h>
1dbae815	18	#include <asm/mach/irq.h>
1dbae815	19
2e7509e5 PW	20
	21	/* selected INTC register offsets */
	22
	23	#define INTC_REVISION 0x0000
	24	#define INTC_SYSCONFIG 0x0010
	25	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	26	#define INTC_SIR 0x0040
2e7509e5	27	#define INTC_CONTROL 0x0048
0addd61b RN	28	#define INTC_PROTECTION 0x004C
	29	#define INTC_IDLE 0x0050
	30	#define INTC_THRESHOLD 0x0068
	31	#define INTC_MIR0 0x0084
2e7509e5 PW	32	#define INTC_MIR_CLEAR0 0x0088
	33	#define INTC_MIR_SET0 0x008c
	34	#define INTC_PENDING_IRQ0 0x0098
2e7509e5 PW	35	/* Number of IRQ state bits in each MIR register */
2e7509e5 PW	36	#define IRQ_BITS_PER_REG 32
1dbae815 TL	37
	38	/*
	39	* OMAP2 has a number of different interrupt controllers, each interrupt
	40	* controller is identified as its own "bank". Register definitions are
	41	* fairly consistent for each bank, but not all registers are implemented
	42	* for each bank.. when in doubt, consult the TRM.
	43	*/
	44	static struct omap_irq_bank {
e8a91c95	45	void __iomem *base_reg;
1dbae815 TL	46	unsigned int nr_irqs;
	47	} __attribute__ ((aligned(4))) irq_banks[] = {
	48	{
	49	/* MPU INTC */
1dbae815	50	.nr_irqs = 96,
646e3ed1	51	},
1dbae815 TL	52	};
1dbae815 TL	53
0addd61b RN	54	/* Structure to save interrupt controller context */
	55	struct omap3_intc_regs {
	56	u32 sysconfig;
	57	u32 protection;
	58	u32 idle;
	59	u32 threshold;
	60	u32 ilr[INTCPS_NR_IRQS];
	61	u32 mir[INTCPS_NR_MIR_REGS];
	62	};
	63
2e7509e5 PW	64	/* INTC bank register get/set */
	65
	66	static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
	67	{
	68	__raw_writel(val, bank->base_reg + reg);
	69	}
	70
	71	static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
	72	{
	73	return __raw_readl(bank->base_reg + reg);
	74	}
	75
1dbae815	76	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	77	static void omap_ack_irq(struct irq_data *d)
1dbae815	78	{
2e7509e5	79	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
1dbae815 TL	80	}
1dbae815 TL	81
df303477	82	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	83	{
667a11fa	84	irq_gc_mask_disable_reg(d);
df303477	85	omap_ack_irq(d);
1dbae815 TL	86	}
1dbae815 TL	87
1dbae815 TL	88	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	89	{
	90	unsigned long tmp;
	91
2e7509e5	92	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
e8a91c95	93	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
1dbae815 TL	94	"(revision %ld.%ld) with %d interrupts\n",
	95	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
	96
2e7509e5	97	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
1dbae815	98	tmp \|= 1 << 1; /* soft reset */
2e7509e5	99	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
1dbae815	100
2e7509e5	101	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
1dbae815	102	/* Wait for reset to complete */;
375e12ab JY	103
375e12ab JY	104	/* Enable autoidle */
2e7509e5	105	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
1dbae815 TL	106	}
1dbae815 TL	107
94434535 JH	108	int omap_irq_pending(void)
	109	{
	110	int i;
	111
	112	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	113	struct omap_irq_bank *bank = irq_banks + i;
	114	int irq;
	115
	116	for (irq = 0; irq < bank->nr_irqs; irq += 32)
	117	if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
	118	((irq >> 5) << 5)))
	119	return 1;
	120	}
	121	return 0;
	122	}
	123
667a11fa TL	124	static __init void
	125	omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
	126	{
	127	struct irq_chip_generic *gc;
	128	struct irq_chip_type *ct;
	129
	130	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
	131	handle_level_irq);
	132	ct = gc->chip_types;
	133	ct->chip.irq_ack = omap_mask_ack_irq;
	134	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	135	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	136
	137	ct->regs.ack = INTC_CONTROL;
	138	ct->regs.enable = INTC_MIR_CLEAR0;
	139	ct->regs.disable = INTC_MIR_SET0;
	140	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	141	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	142	}
	143
1dbae815 TL	144	void __init omap_init_irq(void)
1dbae815 TL	145	{
4b1135a2	146	unsigned long nr_of_irqs = 0;
1dbae815	147	unsigned int nr_banks = 0;
667a11fa	148	int i, j;
1dbae815 TL	149
1dbae815 TL	150	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
74005a2b	151	unsigned long base = 0;
1dbae815 TL	152	struct omap_irq_bank *bank = irq_banks + i;
1dbae815 TL	153
646e3ed1	154	if (cpu_is_omap24xx())
1b26fe86	155	base = OMAP24XX_IC_BASE;
cc26b3b0	156	else if (cpu_is_omap34xx())
1b26fe86 TL	157	base = OMAP34XX_IC_BASE;
1b26fe86 TL	158
74005a2b KH	159	BUG_ON(!base);
74005a2b KH	160
01001712 HP	161	if (cpu_is_ti816x())
	162	bank->nr_irqs = 128;
	163
1b26fe86 TL	164	/* Static mapping, never released */
	165	bank->base_reg = ioremap(base, SZ_4K);
	166	if (!bank->base_reg) {
	167	printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
	168	continue;
	169	}
2e7509e5	170
1dbae815 TL	171	omap_irq_bank_init_one(bank);
1dbae815 TL	172
667a11fa TL	173	for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
	174	omap_alloc_gc(bank->base_reg + j, i, 32);
	175
4b1135a2	176	nr_of_irqs += bank->nr_irqs;
1dbae815 TL	177	nr_banks++;
	178	}
	179
	180	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
4b1135a2	181	nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
1dbae815 TL	182	}
1dbae815 TL	183
0addd61b	184	#ifdef CONFIG_ARCH_OMAP3
ee23b93d FB	185	static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
ee23b93d FB	186
0addd61b RN	187	void omap_intc_save_context(void)
	188	{
	189	int ind = 0, i = 0;
	190	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	191	struct omap_irq_bank *bank = irq_banks + ind;
	192	intc_context[ind].sysconfig =
	193	intc_bank_read_reg(bank, INTC_SYSCONFIG);
	194	intc_context[ind].protection =
	195	intc_bank_read_reg(bank, INTC_PROTECTION);
	196	intc_context[ind].idle =
	197	intc_bank_read_reg(bank, INTC_IDLE);
	198	intc_context[ind].threshold =
	199	intc_bank_read_reg(bank, INTC_THRESHOLD);
	200	for (i = 0; i < INTCPS_NR_IRQS; i++)
	201	intc_context[ind].ilr[i] =
2329e7cc	202	intc_bank_read_reg(bank, (0x100 + 0x4*i));
0addd61b RN	203	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	204	intc_context[ind].mir[i] =
	205	intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
	206	(0x20 * i));
	207	}
	208	}
	209
	210	void omap_intc_restore_context(void)
	211	{
	212	int ind = 0, i = 0;
	213
	214	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	215	struct omap_irq_bank *bank = irq_banks + ind;
	216	intc_bank_write_reg(intc_context[ind].sysconfig,
	217	bank, INTC_SYSCONFIG);
	218	intc_bank_write_reg(intc_context[ind].sysconfig,
	219	bank, INTC_SYSCONFIG);
	220	intc_bank_write_reg(intc_context[ind].protection,
	221	bank, INTC_PROTECTION);
	222	intc_bank_write_reg(intc_context[ind].idle,
	223	bank, INTC_IDLE);
	224	intc_bank_write_reg(intc_context[ind].threshold,
	225	bank, INTC_THRESHOLD);
	226	for (i = 0; i < INTCPS_NR_IRQS; i++)
	227	intc_bank_write_reg(intc_context[ind].ilr[i],
2329e7cc	228	bank, (0x100 + 0x4*i));
0addd61b RN	229	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	230	intc_bank_write_reg(intc_context[ind].mir[i],
	231	&irq_banks[0], INTC_MIR0 + (0x20 * i));
	232	}
	233	/* MIRs are saved and restore with other PRCM registers */
	234	}
2bbe3af3 TK	235
	236	void omap3_intc_suspend(void)
	237	{
	238	/* A pending interrupt would prevent OMAP from entering suspend */
	239	omap_ack_irq(0);
	240	}
f18cc2ff TK	241
	242	void omap3_intc_prepare_idle(void)
	243	{
447b8da5 JP	244	/*
	245	* Disable autoidle as it can stall interrupt controller,
	246	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	247	*/
f18cc2ff TK	248	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
	249	}
	250
	251	void omap3_intc_resume_idle(void)
	252	{
	253	/* Re-enable autoidle */
	254	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
	255	}
0addd61b	256	#endif /* CONFIG_ARCH_OMAP3 */