Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * linux/arch/arm/mach-omap2/irq.c |
1dbae815 TL |
3 | * |
4 | * Interrupt handler for OMAP2 boards. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
1dbae815 | 15 | #include <linux/interrupt.h> |
2e7509e5 | 16 | #include <linux/io.h> |
a09e64fb | 17 | #include <mach/hardware.h> |
1dbae815 | 18 | #include <asm/mach/irq.h> |
1dbae815 | 19 | |
2e7509e5 PW |
20 | |
21 | /* selected INTC register offsets */ | |
22 | ||
23 | #define INTC_REVISION 0x0000 | |
24 | #define INTC_SYSCONFIG 0x0010 | |
25 | #define INTC_SYSSTATUS 0x0014 | |
6ccc4c0d | 26 | #define INTC_SIR 0x0040 |
2e7509e5 PW |
27 | #define INTC_CONTROL 0x0048 |
28 | #define INTC_MIR_CLEAR0 0x0088 | |
29 | #define INTC_MIR_SET0 0x008c | |
30 | #define INTC_PENDING_IRQ0 0x0098 | |
31 | ||
32 | /* Number of IRQ state bits in each MIR register */ | |
33 | #define IRQ_BITS_PER_REG 32 | |
1dbae815 TL |
34 | |
35 | /* | |
36 | * OMAP2 has a number of different interrupt controllers, each interrupt | |
37 | * controller is identified as its own "bank". Register definitions are | |
38 | * fairly consistent for each bank, but not all registers are implemented | |
39 | * for each bank.. when in doubt, consult the TRM. | |
40 | */ | |
41 | static struct omap_irq_bank { | |
e8a91c95 | 42 | void __iomem *base_reg; |
1dbae815 TL |
43 | unsigned int nr_irqs; |
44 | } __attribute__ ((aligned(4))) irq_banks[] = { | |
45 | { | |
46 | /* MPU INTC */ | |
646e3ed1 | 47 | .base_reg = 0, |
1dbae815 | 48 | .nr_irqs = 96, |
646e3ed1 | 49 | }, |
1dbae815 TL |
50 | }; |
51 | ||
2e7509e5 PW |
52 | /* INTC bank register get/set */ |
53 | ||
54 | static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) | |
55 | { | |
56 | __raw_writel(val, bank->base_reg + reg); | |
57 | } | |
58 | ||
59 | static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) | |
60 | { | |
61 | return __raw_readl(bank->base_reg + reg); | |
62 | } | |
63 | ||
6ccc4c0d TL |
64 | static int previous_irq; |
65 | ||
66 | /* | |
67 | * On 34xx we can get occasional spurious interrupts if the ack from | |
68 | * an interrupt handler does not get posted before we unmask. Warn about | |
69 | * the interrupt handlers that need to flush posted writes. | |
70 | */ | |
71 | static int omap_check_spurious(unsigned int irq) | |
72 | { | |
73 | u32 sir, spurious; | |
74 | ||
75 | sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); | |
76 | spurious = sir >> 6; | |
77 | ||
78 | if (spurious > 1) { | |
79 | printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " | |
80 | "posted write for irq %i\n", | |
81 | irq, sir, previous_irq); | |
82 | return spurious; | |
83 | } | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
1dbae815 TL |
88 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
89 | static void omap_ack_irq(unsigned int irq) | |
90 | { | |
2e7509e5 | 91 | intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); |
1dbae815 TL |
92 | } |
93 | ||
94 | static void omap_mask_irq(unsigned int irq) | |
95 | { | |
2e7509e5 | 96 | int offset = irq & (~(IRQ_BITS_PER_REG - 1)); |
1dbae815 | 97 | |
6ccc4c0d TL |
98 | if (cpu_is_omap34xx()) { |
99 | int spurious = 0; | |
100 | ||
101 | /* | |
102 | * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because | |
103 | * it is the highest irq number? | |
104 | */ | |
105 | if (irq == INT_34XX_GPT12_IRQ) | |
106 | spurious = omap_check_spurious(irq); | |
107 | ||
108 | if (!spurious) | |
109 | previous_irq = irq; | |
110 | } | |
111 | ||
2e7509e5 | 112 | irq &= (IRQ_BITS_PER_REG - 1); |
1dbae815 | 113 | |
2e7509e5 | 114 | intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); |
1dbae815 TL |
115 | } |
116 | ||
117 | static void omap_unmask_irq(unsigned int irq) | |
118 | { | |
2e7509e5 | 119 | int offset = irq & (~(IRQ_BITS_PER_REG - 1)); |
1dbae815 | 120 | |
2e7509e5 | 121 | irq &= (IRQ_BITS_PER_REG - 1); |
1dbae815 | 122 | |
2e7509e5 | 123 | intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset); |
1dbae815 TL |
124 | } |
125 | ||
126 | static void omap_mask_ack_irq(unsigned int irq) | |
127 | { | |
128 | omap_mask_irq(irq); | |
129 | omap_ack_irq(irq); | |
130 | } | |
131 | ||
38c677cb DB |
132 | static struct irq_chip omap_irq_chip = { |
133 | .name = "INTC", | |
1dbae815 TL |
134 | .ack = omap_mask_ack_irq, |
135 | .mask = omap_mask_irq, | |
136 | .unmask = omap_unmask_irq, | |
5461af5a | 137 | .disable = omap_mask_irq, |
1dbae815 TL |
138 | }; |
139 | ||
140 | static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) | |
141 | { | |
142 | unsigned long tmp; | |
143 | ||
2e7509e5 | 144 | tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; |
e8a91c95 | 145 | printk(KERN_INFO "IRQ: Found an INTC at 0x%p " |
1dbae815 TL |
146 | "(revision %ld.%ld) with %d interrupts\n", |
147 | bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); | |
148 | ||
2e7509e5 | 149 | tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); |
1dbae815 | 150 | tmp |= 1 << 1; /* soft reset */ |
2e7509e5 | 151 | intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); |
1dbae815 | 152 | |
2e7509e5 | 153 | while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) |
1dbae815 | 154 | /* Wait for reset to complete */; |
375e12ab JY |
155 | |
156 | /* Enable autoidle */ | |
2e7509e5 | 157 | intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); |
1dbae815 TL |
158 | } |
159 | ||
160 | void __init omap_init_irq(void) | |
161 | { | |
4b1135a2 | 162 | unsigned long nr_of_irqs = 0; |
1dbae815 TL |
163 | unsigned int nr_banks = 0; |
164 | int i; | |
165 | ||
166 | for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { | |
167 | struct omap_irq_bank *bank = irq_banks + i; | |
168 | ||
646e3ed1 | 169 | if (cpu_is_omap24xx()) |
2e7509e5 | 170 | bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); |
cc26b3b0 SMK |
171 | else if (cpu_is_omap34xx()) |
172 | bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE); | |
2e7509e5 | 173 | |
1dbae815 TL |
174 | omap_irq_bank_init_one(bank); |
175 | ||
4b1135a2 | 176 | nr_of_irqs += bank->nr_irqs; |
1dbae815 TL |
177 | nr_banks++; |
178 | } | |
179 | ||
180 | printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", | |
4b1135a2 | 181 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); |
1dbae815 | 182 | |
4b1135a2 | 183 | for (i = 0; i < nr_of_irqs; i++) { |
1dbae815 | 184 | set_irq_chip(i, &omap_irq_chip); |
10dd5ce2 | 185 | set_irq_handler(i, handle_level_irq); |
1dbae815 TL |
186 | set_irq_flags(i, IRQF_VALID); |
187 | } | |
188 | } | |
189 |