[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <mach/hardware.h>

#include "iomap.h"
#include "common.h"

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32

#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

static struct irq_domain *domain;

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static void __init omap_init_irq(u32 base, int nr_irqs,
				 struct device_node *node)
{
	void __iomem *omap_irq_base;
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return;

	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
				       &irq_domain_simple_ops, NULL);

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		bank->nr_irqs = nr_irqs;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			pr_err("Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (j = 0; j < bank->nr_irqs; j += 32)
			omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	pr_info("Total of %ld interrupts on %d active controller%s\n",
		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

void __init omap2_init_irq(void)
{
	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
}

void __init omap3_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
}

void __init ti81xx_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
}

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
	u32 irqnr;

	do {
		irqnr = readl_relaxed(base_addr + 0x98);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xb8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xd8);
#ifdef CONFIG_SOC_TI81XX
		if (irqnr)
			goto out;
		irqnr = readl_relaxed(base_addr + 0xf8);
#endif

out:
		if (!irqnr)
			break;

		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
			irqnr = irq_find_mapping(domain, irqnr);
			handle_IRQ(irqnr, regs);
		}
	} while (irqnr);
}

asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP2_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}

int __init omap_intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	struct resource res;
	u32 nr_irqs = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_address_to_resource(node, 0, &res)) {
		WARN(1, "unable to get intc registers\n");
		return -EINVAL;
	}

	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
		pr_warn("unable to get intc-size, default to %d\n", nr_irqs);

	omap_init_irq(res.start, nr_irqs, of_node_get(node));

	return 0;
}

#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}

asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP3_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}
#endif /* CONFIG_ARCH_OMAP3 */
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
1dbae815	20	#include <asm/mach/irq.h>
52fa2120 BC	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
1dbae815	24
ee0839c2 TL	25	#include <mach/hardware.h>
	26
	27	#include "iomap.h"
e2ed89fc	28	#include "common.h"
2e7509e5 PW	29
	30	/* selected INTC register offsets */
	31
	32	#define INTC_REVISION 0x0000
	33	#define INTC_SYSCONFIG 0x0010
	34	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	35	#define INTC_SIR 0x0040
2e7509e5	36	#define INTC_CONTROL 0x0048
0addd61b RN	37	#define INTC_PROTECTION 0x004C
	38	#define INTC_IDLE 0x0050
	39	#define INTC_THRESHOLD 0x0068
	40	#define INTC_MIR0 0x0084
2e7509e5 PW	41	#define INTC_MIR_CLEAR0 0x0088
	42	#define INTC_MIR_SET0 0x008c
	43	#define INTC_PENDING_IRQ0 0x0098
2e7509e5 PW	44	/* Number of IRQ state bits in each MIR register */
2e7509e5 PW	45	#define IRQ_BITS_PER_REG 32
1dbae815	46
2db14997 MZ	47	#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
	48	#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
	49	#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
	50	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
	51
1dbae815 TL	52	/*
	53	* OMAP2 has a number of different interrupt controllers, each interrupt
	54	* controller is identified as its own "bank". Register definitions are
	55	* fairly consistent for each bank, but not all registers are implemented
	56	* for each bank.. when in doubt, consult the TRM.
	57	*/
	58	static struct omap_irq_bank {
e8a91c95	59	void __iomem *base_reg;
1dbae815 TL	60	unsigned int nr_irqs;
	61	} __attribute__ ((aligned(4))) irq_banks[] = {
	62	{
	63	/* MPU INTC */
1dbae815	64	.nr_irqs = 96,
646e3ed1	65	},
1dbae815 TL	66	};
1dbae815 TL	67
52fa2120 BC	68	static struct irq_domain *domain;
52fa2120 BC	69
0addd61b RN	70	/* Structure to save interrupt controller context */
	71	struct omap3_intc_regs {
	72	u32 sysconfig;
	73	u32 protection;
	74	u32 idle;
	75	u32 threshold;
	76	u32 ilr[INTCPS_NR_IRQS];
	77	u32 mir[INTCPS_NR_MIR_REGS];
	78	};
	79
2e7509e5 PW	80	/* INTC bank register get/set */
	81
	82	static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
	83	{
	84	__raw_writel(val, bank->base_reg + reg);
	85	}
	86
	87	static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
	88	{
	89	return __raw_readl(bank->base_reg + reg);
	90	}
	91
1dbae815	92	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	93	static void omap_ack_irq(struct irq_data *d)
1dbae815	94	{
2e7509e5	95	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
1dbae815 TL	96	}
1dbae815 TL	97
df303477	98	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	99	{
667a11fa	100	irq_gc_mask_disable_reg(d);
df303477	101	omap_ack_irq(d);
1dbae815 TL	102	}
1dbae815 TL	103
1dbae815 TL	104	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	105	{
	106	unsigned long tmp;
	107
2e7509e5	108	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
e8a91c95	109	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
1dbae815 TL	110	"(revision %ld.%ld) with %d interrupts\n",
	111	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
	112
2e7509e5	113	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
1dbae815	114	tmp \|= 1 << 1; /* soft reset */
2e7509e5	115	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
1dbae815	116
2e7509e5	117	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
1dbae815	118	/* Wait for reset to complete */;
375e12ab JY	119
375e12ab JY	120	/* Enable autoidle */
2e7509e5	121	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
1dbae815 TL	122	}
1dbae815 TL	123
94434535 JH	124	int omap_irq_pending(void)
	125	{
	126	int i;
	127
	128	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	129	struct omap_irq_bank *bank = irq_banks + i;
	130	int irq;
	131
	132	for (irq = 0; irq < bank->nr_irqs; irq += 32)
	133	if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
	134	((irq >> 5) << 5)))
	135	return 1;
	136	}
	137	return 0;
	138	}
	139
667a11fa TL	140	static __init void
	141	omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
	142	{
	143	struct irq_chip_generic *gc;
	144	struct irq_chip_type *ct;
	145
	146	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
	147	handle_level_irq);
	148	ct = gc->chip_types;
	149	ct->chip.irq_ack = omap_mask_ack_irq;
	150	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	151	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	152
667a11fa TL	153	ct->regs.enable = INTC_MIR_CLEAR0;
	154	ct->regs.disable = INTC_MIR_SET0;
	155	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	156	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	157	}
	158
52fa2120 BC	159	static void __init omap_init_irq(u32 base, int nr_irqs,
52fa2120 BC	160	struct device_node *node)
1dbae815	161	{
ab65be26	162	void __iomem *omap_irq_base;
4b1135a2	163	unsigned long nr_of_irqs = 0;
1dbae815	164	unsigned int nr_banks = 0;
52fa2120	165	int i, j, irq_base;
1dbae815	166
741e3a89 TL	167	omap_irq_base = ioremap(base, SZ_4K);
	168	if (WARN_ON(!omap_irq_base))
	169	return;
	170
52fa2120 BC	171	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	172	if (irq_base < 0) {
	173	pr_warn("Couldn't allocate IRQ numbers\n");
	174	irq_base = 0;
	175	}
	176
	177	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
	178	&irq_domain_simple_ops, NULL);
	179
1dbae815 TL	180	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	181	struct omap_irq_bank *bank = irq_banks + i;
	182
741e3a89	183	bank->nr_irqs = nr_irqs;
01001712	184
1b26fe86 TL	185	/* Static mapping, never released */
	186	bank->base_reg = ioremap(base, SZ_4K);
	187	if (!bank->base_reg) {
52fa2120	188	pr_err("Could not ioremap irq bank%i\n", i);
1b26fe86 TL	189	continue;
1b26fe86 TL	190	}
2e7509e5	191
1dbae815 TL	192	omap_irq_bank_init_one(bank);
1dbae815 TL	193
5c30cdfa	194	for (j = 0; j < bank->nr_irqs; j += 32)
52fa2120	195	omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
667a11fa	196
4b1135a2	197	nr_of_irqs += bank->nr_irqs;
1dbae815 TL	198	nr_banks++;
	199	}
	200
52fa2120 BC	201	pr_info("Total of %ld interrupts on %d active controller%s\n",
52fa2120 BC	202	nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
1dbae815 TL	203	}
1dbae815 TL	204
741e3a89 TL	205	void __init omap2_init_irq(void)
741e3a89 TL	206	{
52fa2120	207	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
741e3a89 TL	208	}
	209
	210	void __init omap3_init_irq(void)
	211	{
52fa2120	212	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
741e3a89 TL	213	}
741e3a89 TL	214
a920360f	215	void __init ti81xx_init_irq(void)
741e3a89	216	{
52fa2120	217	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
741e3a89 TL	218	}
741e3a89 TL	219
2db14997 MZ	220	static inline void omap_intc_handle_irq(void __iomem base_addr, struct pt_regs regs)
	221	{
	222	u32 irqnr;
	223
	224	do {
	225	irqnr = readl_relaxed(base_addr + 0x98);
	226	if (irqnr)
	227	goto out;
	228
	229	irqnr = readl_relaxed(base_addr + 0xb8);
	230	if (irqnr)
	231	goto out;
	232
	233	irqnr = readl_relaxed(base_addr + 0xd8);
33959553	234	#ifdef CONFIG_SOC_TI81XX
2db14997 MZ	235	if (irqnr)
	236	goto out;
	237	irqnr = readl_relaxed(base_addr + 0xf8);
	238	#endif
	239
	240	out:
	241	if (!irqnr)
	242	break;
	243
	244	irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
	245	irqnr &= ACTIVEIRQ_MASK;
	246
52fa2120 BC	247	if (irqnr) {
52fa2120 BC	248	irqnr = irq_find_mapping(domain, irqnr);
2db14997	249	handle_IRQ(irqnr, regs);
52fa2120	250	}
2db14997 MZ	251	} while (irqnr);
	252	}
	253
	254	asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
	255	{
	256	void __iomem *base_addr = OMAP2_IRQ_BASE;
	257	omap_intc_handle_irq(base_addr, regs);
	258	}
	259
52fa2120 BC	260	int __init omap_intc_of_init(struct device_node *node,
	261	struct device_node *parent)
	262	{
	263	struct resource res;
	264	u32 nr_irqs = 96;
	265
	266	if (WARN_ON(!node))
	267	return -ENODEV;
	268
	269	if (of_address_to_resource(node, 0, &res)) {
	270	WARN(1, "unable to get intc registers\n");
	271	return -EINVAL;
	272	}
	273
	274	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
	275	pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
	276
	277	omap_init_irq(res.start, nr_irqs, of_node_get(node));
	278
	279	return 0;
	280	}
	281
0addd61b	282	#ifdef CONFIG_ARCH_OMAP3
ee23b93d FB	283	static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
ee23b93d FB	284
0addd61b RN	285	void omap_intc_save_context(void)
	286	{
	287	int ind = 0, i = 0;
	288	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	289	struct omap_irq_bank *bank = irq_banks + ind;
	290	intc_context[ind].sysconfig =
	291	intc_bank_read_reg(bank, INTC_SYSCONFIG);
	292	intc_context[ind].protection =
	293	intc_bank_read_reg(bank, INTC_PROTECTION);
	294	intc_context[ind].idle =
	295	intc_bank_read_reg(bank, INTC_IDLE);
	296	intc_context[ind].threshold =
	297	intc_bank_read_reg(bank, INTC_THRESHOLD);
	298	for (i = 0; i < INTCPS_NR_IRQS; i++)
	299	intc_context[ind].ilr[i] =
2329e7cc	300	intc_bank_read_reg(bank, (0x100 + 0x4*i));
0addd61b RN	301	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	302	intc_context[ind].mir[i] =
	303	intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
	304	(0x20 * i));
	305	}
	306	}
	307
	308	void omap_intc_restore_context(void)
	309	{
	310	int ind = 0, i = 0;
	311
	312	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	313	struct omap_irq_bank *bank = irq_banks + ind;
	314	intc_bank_write_reg(intc_context[ind].sysconfig,
	315	bank, INTC_SYSCONFIG);
	316	intc_bank_write_reg(intc_context[ind].sysconfig,
	317	bank, INTC_SYSCONFIG);
	318	intc_bank_write_reg(intc_context[ind].protection,
	319	bank, INTC_PROTECTION);
	320	intc_bank_write_reg(intc_context[ind].idle,
	321	bank, INTC_IDLE);
	322	intc_bank_write_reg(intc_context[ind].threshold,
	323	bank, INTC_THRESHOLD);
	324	for (i = 0; i < INTCPS_NR_IRQS; i++)
	325	intc_bank_write_reg(intc_context[ind].ilr[i],
2329e7cc	326	bank, (0x100 + 0x4*i));
0addd61b RN	327	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	328	intc_bank_write_reg(intc_context[ind].mir[i],
	329	&irq_banks[0], INTC_MIR0 + (0x20 * i));
	330	}
	331	/* MIRs are saved and restore with other PRCM registers */
	332	}
2bbe3af3 TK	333
	334	void omap3_intc_suspend(void)
	335	{
	336	/* A pending interrupt would prevent OMAP from entering suspend */
a7022d60	337	omap_ack_irq(NULL);
2bbe3af3	338	}
f18cc2ff TK	339
	340	void omap3_intc_prepare_idle(void)
	341	{
447b8da5 JP	342	/*
	343	* Disable autoidle as it can stall interrupt controller,
	344	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	345	*/
f18cc2ff TK	346	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
	347	}
	348
	349	void omap3_intc_resume_idle(void)
	350	{
	351	/* Re-enable autoidle */
	352	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
	353	}
2db14997 MZ	354
	355	asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
	356	{
	357	void __iomem *base_addr = OMAP3_IRQ_BASE;
	358	omap_intc_handle_irq(base_addr, regs);
	359	}
0addd61b	360	#endif /* CONFIG_ARCH_OMAP3 */