[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "soc.h"
#include "common.h"
#include "../../drivers/irqchip/irqchip.h"

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_PENDING_IRQ1	0x00b8
#define INTC_PENDING_IRQ2	0x00d8
#define INTC_PENDING_IRQ3	0x00f8
#define INTC_ILR0		0x0100

#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
#define INTCPS_NR_ILR_REGS	128
#define INTCPS_NR_MIR_REGS	3

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */

/* Structure to save interrupt controller context */
struct omap_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_ILR_REGS];
	u32 mir[INTCPS_NR_MIR_REGS];
};
static struct omap_intc_regs intc_context;

static struct irq_domain *domain;
static void __iomem *omap_irq_base;
static int omap_nr_pending = 3;
static int omap_nr_irqs = 96;

/* INTC bank register get/set */
static void intc_writel(u32 reg, u32 val)
{
	writel_relaxed(val, omap_irq_base + reg);
}

static u32 intc_readl(u32 reg)
{
	return readl_relaxed(omap_irq_base + reg);
}

void omap_intc_save_context(void)
{
	int i;

	intc_context.sysconfig =
		intc_readl(INTC_SYSCONFIG);
	intc_context.protection =
		intc_readl(INTC_PROTECTION);
	intc_context.idle =
		intc_readl(INTC_IDLE);
	intc_context.threshold =
		intc_readl(INTC_THRESHOLD);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_context.ilr[i] =
			intc_readl((INTC_ILR0 + 0x4 * i));
	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_context.mir[i] =
			intc_readl(INTC_MIR0 + (0x20 * i));
}

void omap_intc_restore_context(void)
{
	int i;

	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	intc_writel(INTC_PROTECTION, intc_context.protection);
	intc_writel(INTC_IDLE, intc_context.idle);
	intc_writel(INTC_THRESHOLD, intc_context.threshold);

	for (i = 0; i < omap_nr_irqs; i++)
		intc_writel(INTC_ILR0 + 0x4 * i,
				intc_context.ilr[i]);

	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_writel(INTC_MIR0 + 0x20 * i,
			intc_context.mir[i]);
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_writel(INTC_SYSCONFIG, 0);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_writel(INTC_CONTROL, 0x1);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_soft_reset(void)
{
	unsigned long tmp;

	tmp = intc_readl(INTC_REVISION) & 0xff;

	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
		omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);

	tmp = intc_readl(INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_writel(INTC_SYSCONFIG, tmp);

	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_writel(INTC_SYSCONFIG, 1 << 0);
}

int omap_irq_pending(void)
{
	int irq;

	for (irq = 0; irq < omap_nr_irqs; irq += 32)
		if (intc_readl(INTC_PENDING_IRQ0 +
					((irq >> 5) << 5)))
			return 1;
	return 0;
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
{
	int ret;
	int i;

	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
			handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
			IRQ_LEVEL, 0);
	if (ret) {
		pr_warn("Failed to allocate irq chips\n");
		return ret;
	}

	for (i = 0; i < omap_nr_pending; i++) {
		struct irq_chip_generic *gc;
		struct irq_chip_type *ct;

		gc = irq_get_domain_generic_chip(d, 32 * i);
		gc->reg_base = base;
		ct = gc->chip_types;

		ct->type = IRQ_TYPE_LEVEL_MASK;
		ct->handler = handle_level_irq;

		ct->chip.irq_ack = omap_mask_ack_irq;
		ct->chip.irq_mask = irq_gc_mask_disable_reg;
		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

		ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

		ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
		ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	}

	return 0;
}

static void __init omap_alloc_gc_legacy(void __iomem *base,
		unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
			handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int __init omap_init_irq_of(struct device_node *node)
{
	int ret;

	omap_irq_base = of_iomap(node, 0);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	domain = irq_domain_add_linear(node, omap_nr_irqs,
			&irq_generic_chip_ops, NULL);

	omap_irq_soft_reset();

	ret = omap_alloc_gc_of(domain, omap_irq_base);
	if (ret < 0)
		irq_domain_remove(domain);

	return ret;
}

static int __init omap_init_irq_legacy(u32 base)
{
	int j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return -ENOMEM;

	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
			&irq_domain_simple_ops, NULL);

	omap_irq_soft_reset();

	for (j = 0; j < omap_nr_irqs; j += 32)
		omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);

	return 0;
}

static int __init omap_init_irq(u32 base, struct device_node *node)
{
	if (node)
		return omap_init_irq_of(node);
	else
		return omap_init_irq_legacy(base);
}

static asmlinkage void __exception_irq_entry
omap_intc_handle_irq(struct pt_regs *regs)
{
	u32 irqnr = 0;
	int handled_irq = 0;
	int i;

	do {
		for (i = 0; i < omap_nr_pending; i++) {
			irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
			if (irqnr)
				goto out;
		}

out:
		if (!irqnr)
			break;

		irqnr = intc_readl(INTC_SIR);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
			irqnr = irq_find_mapping(domain, irqnr);
			handle_IRQ(irqnr, regs);
			handled_irq = 1;
		}
	} while (irqnr);

	/* If an irq is masked or deasserted while active, we will
	 * keep ending up here with no irq handled. So remove it from
	 * the INTC with an ack.*/
	if (!handled_irq)
		omap_ack_irq(NULL);
}

void __init omap2_init_irq(void)
{
	omap_nr_irqs = 96;
	omap_nr_pending = 3;
	omap_init_irq(OMAP24XX_IC_BASE, NULL);
	set_handle_irq(omap_intc_handle_irq);
}

void __init omap3_init_irq(void)
{
	omap_nr_irqs = 96;
	omap_nr_pending = 3;
	omap_init_irq(OMAP34XX_IC_BASE, NULL);
	set_handle_irq(omap_intc_handle_irq);
}

void __init ti81xx_init_irq(void)
{
	omap_nr_irqs = 96;
	omap_nr_pending = 4;
	omap_init_irq(OMAP34XX_IC_BASE, NULL);
	set_handle_irq(omap_intc_handle_irq);
}

static int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	struct resource res;
	int ret;

	omap_nr_pending = 3;
	omap_nr_irqs = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_address_to_resource(node, 0, &res)) {
		WARN(1, "unable to get intc registers\n");
		return -EINVAL;
	}

	if (of_device_is_compatible(node, "ti,am33xx-intc")) {
		omap_nr_irqs = 128;
		omap_nr_pending = 4;
	}

	ret = omap_init_irq(-1, of_node_get(node));
	if (ret < 0)
		return ret;

	set_handle_irq(omap_intc_handle_irq);

	return 0;
}

IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
1dbae815	20	#include <asm/mach/irq.h>
52fa2120 BC	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
c4082d49	24	#include <linux/of_irq.h>
1dbae815	25
dbc04161	26	#include "soc.h"
e2ed89fc	27	#include "common.h"
b65ecd46	28	#include "../../drivers/irqchip/irqchip.h"
2e7509e5 PW	29
	30	/* selected INTC register offsets */
	31
	32	#define INTC_REVISION 0x0000
	33	#define INTC_SYSCONFIG 0x0010
	34	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	35	#define INTC_SIR 0x0040
2e7509e5	36	#define INTC_CONTROL 0x0048
0addd61b RN	37	#define INTC_PROTECTION 0x004C
	38	#define INTC_IDLE 0x0050
	39	#define INTC_THRESHOLD 0x0068
	40	#define INTC_MIR0 0x0084
2e7509e5 PW	41	#define INTC_MIR_CLEAR0 0x0088
	42	#define INTC_MIR_SET0 0x008c
	43	#define INTC_PENDING_IRQ0 0x0098
11983656 FB	44	#define INTC_PENDING_IRQ1 0x00b8
	45	#define INTC_PENDING_IRQ2 0x00d8
	46	#define INTC_PENDING_IRQ3 0x00f8
33c7c7b7	47	#define INTC_ILR0 0x0100
1dbae815	48
2db14997	49	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
a88ab430	50	#define INTCPS_NR_ILR_REGS 128
3003ce3e	51	#define INTCPS_NR_MIR_REGS 3
2db14997	52
1dbae815 TL	53	/*
	54	* OMAP2 has a number of different interrupt controllers, each interrupt
	55	* controller is identified as its own "bank". Register definitions are
	56	* fairly consistent for each bank, but not all registers are implemented
	57	* for each bank.. when in doubt, consult the TRM.
	58	*/
1dbae815	59
0addd61b	60	/* Structure to save interrupt controller context */
272a8b04	61	struct omap_intc_regs {
0addd61b RN	62	u32 sysconfig;
	63	u32 protection;
	64	u32 idle;
	65	u32 threshold;
a88ab430	66	u32 ilr[INTCPS_NR_ILR_REGS];
0addd61b RN	67	u32 mir[INTCPS_NR_MIR_REGS];
0addd61b RN	68	};
131b48c0 FB	69	static struct omap_intc_regs intc_context;
	70
	71	static struct irq_domain *domain;
	72	static void __iomem *omap_irq_base;
52b1e129	73	static int omap_nr_pending = 3;
131b48c0	74	static int omap_nr_irqs = 96;
0addd61b	75
2e7509e5	76	/* INTC bank register get/set */
71be00c9	77	static void intc_writel(u32 reg, u32 val)
2e7509e5	78	{
71be00c9	79	writel_relaxed(val, omap_irq_base + reg);
2e7509e5 PW	80	}
2e7509e5 PW	81
71be00c9	82	static u32 intc_readl(u32 reg)
2e7509e5	83	{
71be00c9	84	return readl_relaxed(omap_irq_base + reg);
2e7509e5 PW	85	}
2e7509e5 PW	86
131b48c0 FB	87	void omap_intc_save_context(void)
	88	{
	89	int i;
	90
	91	intc_context.sysconfig =
	92	intc_readl(INTC_SYSCONFIG);
	93	intc_context.protection =
	94	intc_readl(INTC_PROTECTION);
	95	intc_context.idle =
	96	intc_readl(INTC_IDLE);
	97	intc_context.threshold =
	98	intc_readl(INTC_THRESHOLD);
	99
	100	for (i = 0; i < omap_nr_irqs; i++)
	101	intc_context.ilr[i] =
	102	intc_readl((INTC_ILR0 + 0x4 * i));
	103	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	104	intc_context.mir[i] =
	105	intc_readl(INTC_MIR0 + (0x20 * i));
	106	}
	107
	108	void omap_intc_restore_context(void)
	109	{
	110	int i;
	111
	112	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
	113	intc_writel(INTC_PROTECTION, intc_context.protection);
	114	intc_writel(INTC_IDLE, intc_context.idle);
	115	intc_writel(INTC_THRESHOLD, intc_context.threshold);
	116
	117	for (i = 0; i < omap_nr_irqs; i++)
	118	intc_writel(INTC_ILR0 + 0x4 * i,
	119	intc_context.ilr[i]);
	120
	121	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	122	intc_writel(INTC_MIR0 + 0x20 * i,
	123	intc_context.mir[i]);
	124	/* MIRs are saved and restore with other PRCM registers */
	125	}
	126
	127	void omap3_intc_prepare_idle(void)
	128	{
	129	/*
	130	* Disable autoidle as it can stall interrupt controller,
	131	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	132	*/
	133	intc_writel(INTC_SYSCONFIG, 0);
	134	}
	135
	136	void omap3_intc_resume_idle(void)
	137	{
	138	/* Re-enable autoidle */
	139	intc_writel(INTC_SYSCONFIG, 1);
	140	}
	141
1dbae815	142	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	143	static void omap_ack_irq(struct irq_data *d)
1dbae815	144	{
71be00c9	145	intc_writel(INTC_CONTROL, 0x1);
1dbae815 TL	146	}
1dbae815 TL	147
df303477	148	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	149	{
667a11fa	150	irq_gc_mask_disable_reg(d);
df303477	151	omap_ack_irq(d);
1dbae815 TL	152	}
1dbae815 TL	153
a88ab430	154	static void __init omap_irq_soft_reset(void)
1dbae815 TL	155	{
	156	unsigned long tmp;
	157
71be00c9	158	tmp = intc_readl(INTC_REVISION) & 0xff;
a88ab430	159
7852ec05	160	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
a88ab430	161	omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
1dbae815	162
71be00c9	163	tmp = intc_readl(INTC_SYSCONFIG);
1dbae815	164	tmp \|= 1 << 1; /* soft reset */
71be00c9	165	intc_writel(INTC_SYSCONFIG, tmp);
1dbae815	166
71be00c9	167	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
1dbae815	168	/* Wait for reset to complete */;
375e12ab JY	169
375e12ab JY	170	/* Enable autoidle */
71be00c9	171	intc_writel(INTC_SYSCONFIG, 1 << 0);
1dbae815 TL	172	}
1dbae815 TL	173
94434535 JH	174	int omap_irq_pending(void)
94434535 JH	175	{
a88ab430	176	int irq;
94434535	177
a88ab430 FB	178	for (irq = 0; irq < omap_nr_irqs; irq += 32)
	179	if (intc_readl(INTC_PENDING_IRQ0 +
	180	((irq >> 5) << 5)))
	181	return 1;
94434535 JH	182	return 0;
	183	}
	184
131b48c0 FB	185	void omap3_intc_suspend(void)
	186	{
	187	/* A pending interrupt would prevent OMAP from entering suspend */
	188	omap_ack_irq(NULL);
	189	}
	190
55601c9f FB	191	static int __init omap_alloc_gc_of(struct irq_domain d, void __iomem base)
	192	{
	193	int ret;
	194	int i;
	195
	196	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
	197	handle_level_irq, IRQ_NOREQUEST \| IRQ_NOPROBE,
	198	IRQ_LEVEL, 0);
	199	if (ret) {
	200	pr_warn("Failed to allocate irq chips\n");
	201	return ret;
	202	}
	203
	204	for (i = 0; i < omap_nr_pending; i++) {
	205	struct irq_chip_generic *gc;
	206	struct irq_chip_type *ct;
	207
	208	gc = irq_get_domain_generic_chip(d, 32 * i);
	209	gc->reg_base = base;
	210	ct = gc->chip_types;
	211
	212	ct->type = IRQ_TYPE_LEVEL_MASK;
	213	ct->handler = handle_level_irq;
	214
	215	ct->chip.irq_ack = omap_mask_ack_irq;
	216	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	217	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	218
	219	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
	220
	221	ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
	222	ct->regs.disable = INTC_MIR_SET0 + 32 * i;
	223	}
	224
	225	return 0;
	226	}
	227
	228	static void __init omap_alloc_gc_legacy(void __iomem *base,
	229	unsigned int irq_start, unsigned int num)
667a11fa TL	230	{
	231	struct irq_chip_generic *gc;
	232	struct irq_chip_type *ct;
	233
	234	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
55601c9f	235	handle_level_irq);
667a11fa TL	236	ct = gc->chip_types;
	237	ct->chip.irq_ack = omap_mask_ack_irq;
	238	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	239	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
e3c83c2d	240	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
667a11fa	241
667a11fa TL	242	ct->regs.enable = INTC_MIR_CLEAR0;
	243	ct->regs.disable = INTC_MIR_SET0;
	244	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
55601c9f	245	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
667a11fa TL	246	}
667a11fa TL	247
55601c9f FB	248	static int __init omap_init_irq_of(struct device_node *node)
	249	{
	250	int ret;
	251
	252	omap_irq_base = of_iomap(node, 0);
	253	if (WARN_ON(!omap_irq_base))
	254	return -ENOMEM;
	255
	256	domain = irq_domain_add_linear(node, omap_nr_irqs,
	257	&irq_generic_chip_ops, NULL);
	258
	259	omap_irq_soft_reset();
	260
	261	ret = omap_alloc_gc_of(domain, omap_irq_base);
	262	if (ret < 0)
	263	irq_domain_remove(domain);
	264
	265	return ret;
	266	}
	267
	268	static int __init omap_init_irq_legacy(u32 base)
1dbae815	269	{
a88ab430	270	int j, irq_base;
1dbae815	271
741e3a89 TL	272	omap_irq_base = ioremap(base, SZ_4K);
741e3a89 TL	273	if (WARN_ON(!omap_irq_base))
55601c9f	274	return -ENOMEM;
741e3a89	275
a74f0a17	276	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
52fa2120 BC	277	if (irq_base < 0) {
	278	pr_warn("Couldn't allocate IRQ numbers\n");
	279	irq_base = 0;
	280	}
	281
55601c9f	282	domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
a88ab430	283	&irq_domain_simple_ops, NULL);
1dbae815	284
a88ab430	285	omap_irq_soft_reset();
667a11fa	286
a88ab430	287	for (j = 0; j < omap_nr_irqs; j += 32)
55601c9f FB	288	omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
	289
	290	return 0;
	291	}
	292
	293	static int __init omap_init_irq(u32 base, struct device_node *node)
	294	{
	295	if (node)
	296	return omap_init_irq_of(node);
	297	else
	298	return omap_init_irq_legacy(base);
1dbae815 TL	299	}
1dbae815 TL	300
2aced892 FB	301	static asmlinkage void __exception_irq_entry
2aced892 FB	302	omap_intc_handle_irq(struct pt_regs *regs)
2db14997	303	{
d6a7c5c8	304	u32 irqnr = 0;
698b4853	305	int handled_irq = 0;
d6a7c5c8	306	int i;
2db14997 MZ	307
2db14997 MZ	308	do {
d6a7c5c8 FB	309	for (i = 0; i < omap_nr_pending; i++) {
	310	irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
	311	if (irqnr)
	312	goto out;
	313	}
2db14997 MZ	314
	315	out:
	316	if (!irqnr)
	317	break;
	318
11983656	319	irqnr = intc_readl(INTC_SIR);
2db14997 MZ	320	irqnr &= ACTIVEIRQ_MASK;
2db14997 MZ	321
52fa2120 BC	322	if (irqnr) {
52fa2120 BC	323	irqnr = irq_find_mapping(domain, irqnr);
2db14997	324	handle_IRQ(irqnr, regs);
698b4853	325	handled_irq = 1;
52fa2120	326	}
2db14997	327	} while (irqnr);
698b4853 SS	328
	329	/* If an irq is masked or deasserted while active, we will
	330	* keep ending up here with no irq handled. So remove it from
	331	* the INTC with an ack.*/
	332	if (!handled_irq)
	333	omap_ack_irq(NULL);
2db14997 MZ	334	}
2db14997 MZ	335
a4d3c5d9 FB	336	void __init omap2_init_irq(void)
a4d3c5d9 FB	337	{
a74f0a17	338	omap_nr_irqs = 96;
52b1e129	339	omap_nr_pending = 3;
a74f0a17	340	omap_init_irq(OMAP24XX_IC_BASE, NULL);
2aced892	341	set_handle_irq(omap_intc_handle_irq);
a4d3c5d9 FB	342	}
	343
	344	void __init omap3_init_irq(void)
	345	{
a74f0a17	346	omap_nr_irqs = 96;
52b1e129	347	omap_nr_pending = 3;
a74f0a17	348	omap_init_irq(OMAP34XX_IC_BASE, NULL);
2aced892	349	set_handle_irq(omap_intc_handle_irq);
a4d3c5d9 FB	350	}
	351
	352	void __init ti81xx_init_irq(void)
	353	{
a74f0a17	354	omap_nr_irqs = 96;
52b1e129	355	omap_nr_pending = 4;
a74f0a17	356	omap_init_irq(OMAP34XX_IC_BASE, NULL);
2aced892	357	set_handle_irq(omap_intc_handle_irq);
a4d3c5d9 FB	358	}
a4d3c5d9 FB	359
00b6b031	360	static int __init intc_of_init(struct device_node *node,
52fa2120 BC	361	struct device_node *parent)
	362	{
	363	struct resource res;
55601c9f	364	int ret;
a74f0a17	365
52b1e129	366	omap_nr_pending = 3;
a74f0a17	367	omap_nr_irqs = 96;
52fa2120 BC	368
	369	if (WARN_ON(!node))
	370	return -ENODEV;
	371
	372	if (of_address_to_resource(node, 0, &res)) {
	373	WARN(1, "unable to get intc registers\n");
	374	return -EINVAL;
	375	}
	376
52b1e129	377	if (of_device_is_compatible(node, "ti,am33xx-intc")) {
a74f0a17	378	omap_nr_irqs = 128;
52b1e129 FB	379	omap_nr_pending = 4;
52b1e129 FB	380	}
470f30de	381
55601c9f FB	382	ret = omap_init_irq(-1, of_node_get(node));
	383	if (ret < 0)
	384	return ret;
52fa2120	385
2aced892	386	set_handle_irq(omap_intc_handle_irq);
b15c76b7	387
52fa2120 BC	388	return 0;
	389	}
	390
a35db9a4 FB	391	IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
	392	IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
	393	IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);