[deliverable/linux.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <plat/mailbox.h>
#include <mach/irqs.h>

#define MAILBOX_REVISION		0x000
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))

#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

#define MBOX_REG_SIZE			0x120

#define OMAP4_MBOX_REG_SIZE		0x130

#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[OMAP4_MBOX_NR_REGS];
	unsigned long irqdisable;
};

static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
				  omap_mbox_type_t irq);

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;

	pm_runtime_enable(mbox->dev->parent);
	pm_runtime_get_sync(mbox->dev->parent);

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	omap2_mbox_enable_irq(mbox, IRQ_RX);

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	pm_runtime_put_sync(mbox->dev->parent);
	pm_runtime_disable(mbox->dev->parent);
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return mbox_read_reg(fifo->fifo_stat);
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	if (!cpu_is_omap44xx())
		bit = mbox_read_reg(p->irqdisable) & ~bit;

	mbox_write_reg(bit, p->irqdisable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);

	/* Flush posted write for irq status to avoid spurious interrupts */
	mbox_read_reg(p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (int)(enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= MAILBOX_IRQENABLE(0),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};
#endif

#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif

#if defined(CONFIG_SOC_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
	.irqdisable	= MAILBOX_IRQENABLE(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};

struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
#endif

#if defined(CONFIG_ARCH_OMAP4)
/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_1_info = {
	.name	= "mailbox-1",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_1_priv,
};

static struct omap_mbox2_priv omap2_mbox_2_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.msg_stat	= MAILBOX_MSGSTATUS(2),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_2_info = {
	.name	= "mailbox-2",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_2_priv,
};

struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
#endif

static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *mem;
	int ret;
	struct omap_mbox **list;

	if (false)
		;
#if defined(CONFIG_ARCH_OMAP3)
	else if (cpu_is_omap34xx()) {
		list = omap3_mboxes;

		list[0]->irq = platform_get_irq(pdev, 0);
	}
#endif
#if defined(CONFIG_ARCH_OMAP2)
	else if (cpu_is_omap2430()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq(pdev, 0);
	} else if (cpu_is_omap2420()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
		list[1]->irq = platform_get_irq_byname(pdev, "iva");
	}
#endif
#if defined(CONFIG_ARCH_OMAP4)
	else if (cpu_is_omap44xx()) {
		list = omap4_mboxes;

		list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
	}
#endif
	else {
		pr_err("%s: platform not supported\n", __func__);
		return -ENODEV;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mbox_base = ioremap(mem->start, resource_size(mem));
	if (!mbox_base)
		return -ENOMEM;

	ret = omap_mbox_register(&pdev->dev, list);
	if (ret) {
		iounmap(mbox_base);
		return ret;
	}

	return 0;
}

static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
	omap_mbox_unregister();
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = __devexit_p(omap2_mbox_remove),
	.driver = {
		.name = "omap-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_AUTHOR("Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
340a614a HD	13	#include <linux/clk.h>
	14	#include <linux/err.h>
	15	#include <linux/platform_device.h>
fced80c7	16	#include <linux/io.h>
82d2a5db	17	#include <linux/pm_runtime.h>
ce491cf8	18	#include <plat/mailbox.h>
a09e64fb	19	#include <mach/irqs.h>
340a614a	20
733ecc5c	21	#define MAILBOX_REVISION 0x000
733ecc5c HD	22	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	23	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	24	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	25	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	26	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	27
5f00ec64 S	28	#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
	29	#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
	30	#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
	31
	32	#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
	33	#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
340a614a	34
c75ee752	35	#define MBOX_REG_SIZE 0x120
5f00ec64 S	36
	37	#define OMAP4_MBOX_REG_SIZE 0x130
	38
c75ee752	39	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
5f00ec64	40	#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
c75ee752	41
6c20a683	42	static void __iomem *mbox_base;
340a614a HD	43
	44	struct omap_mbox2_fifo {
	45	unsigned long msg;
	46	unsigned long fifo_stat;
	47	unsigned long msg_stat;
	48	};
	49
	50	struct omap_mbox2_priv {
	51	struct omap_mbox2_fifo tx_fifo;
	52	struct omap_mbox2_fifo rx_fifo;
	53	unsigned long irqenable;
	54	unsigned long irqstatus;
	55	u32 newmsg_bit;
	56	u32 notfull_bit;
5f00ec64 S	57	u32 ctx[OMAP4_MBOX_NR_REGS];
5f00ec64 S	58	unsigned long irqdisable;
340a614a HD	59	};
340a614a HD	60
bfbdcf8a HD	61	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
	62	omap_mbox_type_t irq);
	63
6c20a683	64	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	65	{
6c20a683	66	return __raw_readl(mbox_base + ofs);
340a614a HD	67	}
340a614a HD	68
6c20a683	69	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	70	{
6c20a683	71	__raw_writel(val, mbox_base + ofs);
340a614a HD	72	}
	73
	74	/* Mailbox H/W preparations */
bfbdcf8a	75	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	76	{
1ffe627d	77	u32 l;
340a614a	78
82d2a5db ORL	79	pm_runtime_enable(mbox->dev->parent);
82d2a5db ORL	80	pm_runtime_get_sync(mbox->dev->parent);
1ffe627d	81
94fc58c6	82	l = mbox_read_reg(MAILBOX_REVISION);
909f9dc7	83	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
94fc58c6	84
bfbdcf8a HD	85	omap2_mbox_enable_irq(mbox, IRQ_RX);
bfbdcf8a HD	86
340a614a HD	87	return 0;
	88	}
	89
bfbdcf8a	90	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a	91	{
82d2a5db ORL	92	pm_runtime_put_sync(mbox->dev->parent);
82d2a5db ORL	93	pm_runtime_disable(mbox->dev->parent);
340a614a HD	94	}
	95
	96	/* Mailbox FIFO handle functions */
bfbdcf8a	97	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	98	{
	99	struct omap_mbox2_fifo *fifo =
	100	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	101	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	102	}
	103
bfbdcf8a	104	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	105	{
	106	struct omap_mbox2_fifo *fifo =
	107	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	108	mbox_write_reg(msg, fifo->msg);
	109	}
	110
bfbdcf8a	111	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	112	{
	113	struct omap_mbox2_fifo *fifo =
	114	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	115	return (mbox_read_reg(fifo->msg_stat) == 0);
	116	}
	117
bfbdcf8a	118	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	119	{
	120	struct omap_mbox2_fifo *fifo =
	121	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
5f00ec64	122	return mbox_read_reg(fifo->fifo_stat);
340a614a HD	123	}
	124
	125	/* Mailbox IRQ handle functions */
bfbdcf8a	126	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
340a614a HD	127	omap_mbox_type_t irq)
340a614a HD	128	{
b45b501c	129	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	130	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	131
	132	l = mbox_read_reg(p->irqenable);
	133	l \|= bit;
	134	mbox_write_reg(l, p->irqenable);
	135	}
	136
bfbdcf8a	137	static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
340a614a HD	138	omap_mbox_type_t irq)
340a614a HD	139	{
b45b501c	140	struct omap_mbox2_priv *p = mbox->priv;
525a1138 HK	141	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	142
	143	if (!cpu_is_omap44xx())
	144	bit = mbox_read_reg(p->irqdisable) & ~bit;
	145
	146	mbox_write_reg(bit, p->irqdisable);
340a614a HD	147	}
340a614a HD	148
bfbdcf8a	149	static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
340a614a HD	150	omap_mbox_type_t irq)
340a614a HD	151	{
b45b501c	152	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	153	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	154
	155	mbox_write_reg(bit, p->irqstatus);
8828880d HD	156
	157	/* Flush posted write for irq status to avoid spurious interrupts */
	158	mbox_read_reg(p->irqstatus);
340a614a HD	159	}
340a614a HD	160
bfbdcf8a	161	static int omap2_mbox_is_irq(struct omap_mbox *mbox,
340a614a HD	162	omap_mbox_type_t irq)
340a614a HD	163	{
b45b501c	164	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	165	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	166	u32 enable = mbox_read_reg(p->irqenable);
	167	u32 status = mbox_read_reg(p->irqstatus);
	168
5f00ec64	169	return (int)(enable & status & bit);
340a614a HD	170	}
340a614a HD	171
c75ee752 HD	172	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	173	{
	174	int i;
	175	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	176	int nr_regs;
	177	if (cpu_is_omap44xx())
	178	nr_regs = OMAP4_MBOX_NR_REGS;
	179	else
	180	nr_regs = MBOX_NR_REGS;
	181	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	182	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	183
	184	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	185	i, p->ctx[i]);
	186	}
	187	}
	188
	189	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	190	{
	191	int i;
	192	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	193	int nr_regs;
	194	if (cpu_is_omap44xx())
	195	nr_regs = OMAP4_MBOX_NR_REGS;
	196	else
	197	nr_regs = MBOX_NR_REGS;
	198	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	199	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	200
	201	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	202	i, p->ctx[i]);
	203	}
	204	}
	205
340a614a HD	206	static struct omap_mbox_ops omap2_mbox_ops = {
	207	.type = OMAP_MBOX_TYPE2,
	208	.startup = omap2_mbox_startup,
	209	.shutdown = omap2_mbox_shutdown,
	210	.fifo_read = omap2_mbox_fifo_read,
	211	.fifo_write = omap2_mbox_fifo_write,
	212	.fifo_empty = omap2_mbox_fifo_empty,
	213	.fifo_full = omap2_mbox_fifo_full,
	214	.enable_irq = omap2_mbox_enable_irq,
	215	.disable_irq = omap2_mbox_disable_irq,
	216	.ack_irq = omap2_mbox_ack_irq,
	217	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	218	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	219	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	220	};
	221
	222	/*
	223	* MAILBOX 0: ARM -> DSP,
	224	* MAILBOX 1: ARM <- DSP.
	225	* MAILBOX 2: ARM -> IVA,
	226	* MAILBOX 3: ARM <- IVA.
	227	*/
	228
	229	/* FIXME: the following structs should be filled automatically by the user id */
07d65d8b	230
ff0fba0b	231	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP2)
340a614a HD	232	/* DSP */
	233	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	234	.tx_fifo = {
733ecc5c HD	235	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	236	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	237	},
340a614a HD	238	.rx_fifo = {
733ecc5c HD	239	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	240	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	241	},
733ecc5c HD	242	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	243	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	244	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
340a614a HD	245	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
5f00ec64 S	246	.irqdisable = MAILBOX_IRQENABLE(0),
	247	};
	248
07d65d8b FC	249	struct omap_mbox mbox_dsp_info = {
	250	.name = "dsp",
	251	.ops = &omap2_mbox_ops,
	252	.priv = &omap2_mbox_dsp_priv,
	253	};
14476bd9	254	#endif
07d65d8b	255
ff0fba0b	256	#if defined(CONFIG_ARCH_OMAP3)
898ee756	257	struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
14476bd9	258	#endif
898ee756	259
59b479e0	260	#if defined(CONFIG_SOC_OMAP2420)
07d65d8b FC	261	/* IVA */
	262	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	263	.tx_fifo = {
	264	.msg = MAILBOX_MESSAGE(2),
	265	.fifo_stat = MAILBOX_FIFOSTATUS(2),
	266	},
	267	.rx_fifo = {
	268	.msg = MAILBOX_MESSAGE(3),
	269	.msg_stat = MAILBOX_MSGSTATUS(3),
	270	},
	271	.irqenable = MAILBOX_IRQENABLE(3),
	272	.irqstatus = MAILBOX_IRQSTATUS(3),
	273	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	274	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	275	.irqdisable = MAILBOX_IRQENABLE(3),
	276	};
	277
	278	static struct omap_mbox mbox_iva_info = {
	279	.name = "iva",
	280	.ops = &omap2_mbox_ops,
	281	.priv = &omap2_mbox_iva_priv,
	282	};
898ee756	283
eca83258	284	struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
07d65d8b FC	285	#endif
07d65d8b FC	286
14476bd9	287	#if defined(CONFIG_ARCH_OMAP4)
07d65d8b	288	/* OMAP4 */
5f00ec64 S	289	static struct omap_mbox2_priv omap2_mbox_1_priv = {
	290	.tx_fifo = {
	291	.msg = MAILBOX_MESSAGE(0),
	292	.fifo_stat = MAILBOX_FIFOSTATUS(0),
	293	},
	294	.rx_fifo = {
	295	.msg = MAILBOX_MESSAGE(1),
	296	.msg_stat = MAILBOX_MSGSTATUS(1),
	297	},
	298	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	299	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	300	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	301	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	302	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
340a614a HD	303	};
340a614a HD	304
5f00ec64 S	305	struct omap_mbox mbox_1_info = {
	306	.name = "mailbox-1",
	307	.ops = &omap2_mbox_ops,
	308	.priv = &omap2_mbox_1_priv,
	309	};
5f00ec64	310
5f00ec64 S	311	static struct omap_mbox2_priv omap2_mbox_2_priv = {
	312	.tx_fifo = {
	313	.msg = MAILBOX_MESSAGE(3),
	314	.fifo_stat = MAILBOX_FIFOSTATUS(3),
	315	},
	316	.rx_fifo = {
	317	.msg = MAILBOX_MESSAGE(2),
	318	.msg_stat = MAILBOX_MSGSTATUS(2),
	319	},
	320	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	321	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	322	.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
	323	.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
	324	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
	325	};
	326
	327	struct omap_mbox mbox_2_info = {
	328	.name = "mailbox-2",
	329	.ops = &omap2_mbox_ops,
	330	.priv = &omap2_mbox_2_priv,
	331	};
5f00ec64	332
898ee756	333	struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
14476bd9	334	#endif
898ee756	335
da8cfe03	336	static int __devinit omap2_mbox_probe(struct platform_device *pdev)
340a614a	337	{
898ee756	338	struct resource *mem;
6c20a683	339	int ret;
9c80c8cd	340	struct omap_mbox **list;
340a614a	341
14476bd9 FC	342	if (false)
14476bd9 FC	343	;
ff0fba0b ORL	344	#if defined(CONFIG_ARCH_OMAP3)
ff0fba0b ORL	345	else if (cpu_is_omap34xx()) {
898ee756 FC	346	list = omap3_mboxes;
898ee756 FC	347
69dbf857	348	list[0]->irq = platform_get_irq(pdev, 0);
340a614a	349	}
14476bd9	350	#endif
ff0fba0b ORL	351	#if defined(CONFIG_ARCH_OMAP2)
	352	else if (cpu_is_omap2430()) {
	353	list = omap2_mboxes;
	354
69dbf857	355	list[0]->irq = platform_get_irq(pdev, 0);
ff0fba0b	356	} else if (cpu_is_omap2420()) {
898ee756	357	list = omap2_mboxes;
340a614a	358
898ee756 FC	359	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	360	list[1]->irq = platform_get_irq_byname(pdev, "iva");
	361	}
	362	#endif
14476bd9	363	#if defined(CONFIG_ARCH_OMAP4)
898ee756 FC	364	else if (cpu_is_omap44xx()) {
898ee756 FC	365	list = omap4_mboxes;
5f00ec64	366
69dbf857	367	list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
340a614a	368	}
14476bd9	369	#endif
898ee756 FC	370	else {
	371	pr_err("%s: platform not supported\n", __func__);
	372	return -ENODEV;
5f00ec64	373	}
6c20a683	374
898ee756 FC	375	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	376	mbox_base = ioremap(mem->start, resource_size(mem));
	377	if (!mbox_base)
	378	return -ENOMEM;
	379
9c80c8cd FC	380	ret = omap_mbox_register(&pdev->dev, list);
	381	if (ret) {
	382	iounmap(mbox_base);
	383	return ret;
340a614a	384	}
340a614a	385
5d783731	386	return 0;
340a614a HD	387	}
340a614a HD	388
da8cfe03	389	static int __devexit omap2_mbox_remove(struct platform_device *pdev)
340a614a	390	{
9c80c8cd	391	omap_mbox_unregister();
6c20a683	392	iounmap(mbox_base);
340a614a HD	393	return 0;
	394	}
	395
	396	static struct platform_driver omap2_mbox_driver = {
	397	.probe = omap2_mbox_probe,
da8cfe03	398	.remove = __devexit_p(omap2_mbox_remove),
340a614a	399	.driver = {
d742709e	400	.name = "omap-mailbox",
340a614a HD	401	},
	402	};
	403
	404	static int __init omap2_mbox_init(void)
	405	{
	406	return platform_driver_register(&omap2_mbox_driver);
	407	}
	408
	409	static void __exit omap2_mbox_exit(void)
	410	{
	411	platform_driver_unregister(&omap2_mbox_driver);
	412	}
	413
	414	module_init(omap2_mbox_init);
	415	module_exit(omap2_mbox_exit);
	416
733ecc5c	417	MODULE_LICENSE("GPL v2");
5f00ec64	418	MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
f375325a OBC	419	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
f375325a OBC	420	MODULE_AUTHOR("Paul Mundt");
d742709e	421	MODULE_ALIAS("platform:omap2-mailbox");