[deliverable/linux.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <plat/mailbox.h>
#include <mach/irqs.h>

#define MAILBOX_REVISION		0x000
#define MAILBOX_SYSCONFIG		0x010
#define MAILBOX_SYSSTATUS		0x014
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))

#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

/* SYSCONFIG: register bit definition */
#define AUTOIDLE	(1 << 0)
#define SOFTRESET	(1 << 1)
#define SMARTIDLE	(2 << 3)
#define OMAP4_SOFTRESET	(1 << 0)
#define OMAP4_NOIDLE	(1 << 2)
#define OMAP4_SMARTIDLE	(2 << 2)

/* SYSSTATUS: register bit definition */
#define RESETDONE	(1 << 0)

#define MBOX_REG_SIZE			0x120

#define OMAP4_MBOX_REG_SIZE		0x130

#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[OMAP4_MBOX_NR_REGS];
	unsigned long irqdisable;
};

static struct clk *mbox_ick_handle;

static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
				  omap_mbox_type_t irq);

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;
	unsigned long timeout;

	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	if (IS_ERR(mbox_ick_handle)) {
		printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
			PTR_ERR(mbox_ick_handle));
		return PTR_ERR(mbox_ick_handle);
	}
	clk_enable(mbox_ick_handle);

	if (cpu_is_omap44xx()) {
		mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
		timeout = jiffies + msecs_to_jiffies(20);
		do {
			l = mbox_read_reg(MAILBOX_SYSCONFIG);
			if (!(l & OMAP4_SOFTRESET))
				break;
		} while (!time_after(jiffies, timeout));

		if (l & OMAP4_SOFTRESET) {
			pr_err("Can't take mailbox out of reset\n");
			return -ENODEV;
		}
	} else {
		mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
		timeout = jiffies + msecs_to_jiffies(20);
		do {
			l = mbox_read_reg(MAILBOX_SYSSTATUS);
			if (l & RESETDONE)
				break;
		} while (!time_after(jiffies, timeout));

		if (!(l & RESETDONE)) {
			pr_err("Can't take mailbox out of reset\n");
			return -ENODEV;
		}
	}

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	if (cpu_is_omap44xx())
		l = OMAP4_SMARTIDLE;
	else
		l = SMARTIDLE | AUTOIDLE;
	mbox_write_reg(l, MAILBOX_SYSCONFIG);

	omap2_mbox_enable_irq(mbox, IRQ_RX);

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	clk_disable(mbox_ick_handle);
	clk_put(mbox_ick_handle);
	mbox_ick_handle = NULL;
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return mbox_read_reg(fifo->fifo_stat);
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	if (!cpu_is_omap44xx())
		bit = mbox_read_reg(p->irqdisable) & ~bit;

	mbox_write_reg(bit, p->irqdisable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);

	/* Flush posted write for irq status to avoid spurious interrupts */
	mbox_read_reg(p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (int)(enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= MAILBOX_IRQENABLE(0),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};
#endif

#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif

#if defined(CONFIG_ARCH_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
	.irqdisable	= MAILBOX_IRQENABLE(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};

struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
#endif

#if defined(CONFIG_ARCH_OMAP4)
/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_1_info = {
	.name	= "mailbox-1",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_1_priv,
};

static struct omap_mbox2_priv omap2_mbox_2_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.msg_stat	= MAILBOX_MSGSTATUS(2),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_2_info = {
	.name	= "mailbox-2",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_2_priv,
};

struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
#endif

static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *mem;
	int ret;
	struct omap_mbox **list;

	if (false)
		;
#if defined(CONFIG_ARCH_OMAP3)
	else if (cpu_is_omap34xx()) {
		list = omap3_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	}
#endif
#if defined(CONFIG_ARCH_OMAP2)
	else if (cpu_is_omap2430()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	} else if (cpu_is_omap2420()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
		list[1]->irq = platform_get_irq_byname(pdev, "iva");
	}
#endif
#if defined(CONFIG_ARCH_OMAP4)
	else if (cpu_is_omap44xx()) {
		list = omap4_mboxes;

		list[0]->irq = list[1]->irq =
			platform_get_irq_byname(pdev, "mbox");
	}
#endif
	else {
		pr_err("%s: platform not supported\n", __func__);
		return -ENODEV;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mbox_base = ioremap(mem->start, resource_size(mem));
	if (!mbox_base)
		return -ENOMEM;

	ret = omap_mbox_register(&pdev->dev, list);
	if (ret) {
		iounmap(mbox_base);
		return ret;
	}

	return 0;
}

static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
	omap_mbox_unregister();
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = __devexit_p(omap2_mbox_remove),
	.driver = {
		.name = "omap-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_AUTHOR("Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
340a614a HD	13	#include <linux/clk.h>
	14	#include <linux/err.h>
	15	#include <linux/platform_device.h>
fced80c7	16	#include <linux/io.h>
ce491cf8	17	#include <plat/mailbox.h>
a09e64fb	18	#include <mach/irqs.h>
340a614a	19
733ecc5c HD	20	#define MAILBOX_REVISION 0x000
	21	#define MAILBOX_SYSCONFIG 0x010
	22	#define MAILBOX_SYSSTATUS 0x014
	23	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	24	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	25	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	26	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	27	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	28
5f00ec64 S	29	#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
	30	#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
	31	#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
	32
	33	#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
	34	#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
340a614a	35
1ffe627d HD	36	/* SYSCONFIG: register bit definition */
	37	#define AUTOIDLE (1 << 0)
	38	#define SOFTRESET (1 << 1)
	39	#define SMARTIDLE (2 << 3)
a6a60228	40	#define OMAP4_SOFTRESET (1 << 0)
4499ce42 SA	41	#define OMAP4_NOIDLE (1 << 2)
4499ce42 SA	42	#define OMAP4_SMARTIDLE (2 << 2)
1ffe627d HD	43
	44	/* SYSSTATUS: register bit definition */
	45	#define RESETDONE (1 << 0)
	46
c75ee752	47	#define MBOX_REG_SIZE 0x120
5f00ec64 S	48
	49	#define OMAP4_MBOX_REG_SIZE 0x130
	50
c75ee752	51	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
5f00ec64	52	#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
c75ee752	53
6c20a683	54	static void __iomem *mbox_base;
340a614a HD	55
	56	struct omap_mbox2_fifo {
	57	unsigned long msg;
	58	unsigned long fifo_stat;
	59	unsigned long msg_stat;
	60	};
	61
	62	struct omap_mbox2_priv {
	63	struct omap_mbox2_fifo tx_fifo;
	64	struct omap_mbox2_fifo rx_fifo;
	65	unsigned long irqenable;
	66	unsigned long irqstatus;
	67	u32 newmsg_bit;
	68	u32 notfull_bit;
5f00ec64 S	69	u32 ctx[OMAP4_MBOX_NR_REGS];
5f00ec64 S	70	unsigned long irqdisable;
340a614a HD	71	};
	72
	73	static struct clk *mbox_ick_handle;
	74
bfbdcf8a HD	75	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
	76	omap_mbox_type_t irq);
	77
6c20a683	78	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	79	{
6c20a683	80	return __raw_readl(mbox_base + ofs);
340a614a HD	81	}
340a614a HD	82
6c20a683	83	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	84	{
6c20a683	85	__raw_writel(val, mbox_base + ofs);
340a614a HD	86	}
	87
	88	/* Mailbox H/W preparations */
bfbdcf8a	89	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	90	{
1ffe627d HD	91	u32 l;
1ffe627d HD	92	unsigned long timeout;
340a614a HD	93
	94	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	95	if (IS_ERR(mbox_ick_handle)) {
0cd7e1cc	96	printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
5f00ec64 S	97	PTR_ERR(mbox_ick_handle));
5f00ec64 S	98	return PTR_ERR(mbox_ick_handle);
340a614a HD	99	}
	100	clk_enable(mbox_ick_handle);
	101
a6a60228 SA	102	if (cpu_is_omap44xx()) {
	103	mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
	104	timeout = jiffies + msecs_to_jiffies(20);
	105	do {
	106	l = mbox_read_reg(MAILBOX_SYSCONFIG);
	107	if (!(l & OMAP4_SOFTRESET))
	108	break;
	109	} while (!time_after(jiffies, timeout));
	110
	111	if (l & OMAP4_SOFTRESET) {
	112	pr_err("Can't take mailbox out of reset\n");
	113	return -ENODEV;
	114	}
	115	} else {
	116	mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
	117	timeout = jiffies + msecs_to_jiffies(20);
	118	do {
	119	l = mbox_read_reg(MAILBOX_SYSSTATUS);
	120	if (l & RESETDONE)
	121	break;
	122	} while (!time_after(jiffies, timeout));
	123
	124	if (!(l & RESETDONE)) {
	125	pr_err("Can't take mailbox out of reset\n");
	126	return -ENODEV;
	127	}
1ffe627d HD	128	}
1ffe627d HD	129
94fc58c6	130	l = mbox_read_reg(MAILBOX_REVISION);
909f9dc7	131	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
94fc58c6	132
4499ce42 SA	133	if (cpu_is_omap44xx())
	134	l = OMAP4_SMARTIDLE;
	135	else
	136	l = SMARTIDLE \| AUTOIDLE;
340a614a HD	137	mbox_write_reg(l, MAILBOX_SYSCONFIG);
340a614a HD	138
bfbdcf8a HD	139	omap2_mbox_enable_irq(mbox, IRQ_RX);
bfbdcf8a HD	140
340a614a HD	141	return 0;
	142	}
	143
bfbdcf8a	144	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a HD	145	{
	146	clk_disable(mbox_ick_handle);
	147	clk_put(mbox_ick_handle);
5f00ec64	148	mbox_ick_handle = NULL;
340a614a HD	149	}
	150
	151	/* Mailbox FIFO handle functions */
bfbdcf8a	152	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	153	{
	154	struct omap_mbox2_fifo *fifo =
	155	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	156	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	157	}
	158
bfbdcf8a	159	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	160	{
	161	struct omap_mbox2_fifo *fifo =
	162	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	163	mbox_write_reg(msg, fifo->msg);
	164	}
	165
bfbdcf8a	166	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	167	{
	168	struct omap_mbox2_fifo *fifo =
	169	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	170	return (mbox_read_reg(fifo->msg_stat) == 0);
	171	}
	172
bfbdcf8a	173	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	174	{
	175	struct omap_mbox2_fifo *fifo =
	176	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
5f00ec64	177	return mbox_read_reg(fifo->fifo_stat);
340a614a HD	178	}
	179
	180	/* Mailbox IRQ handle functions */
bfbdcf8a	181	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
340a614a HD	182	omap_mbox_type_t irq)
340a614a HD	183	{
b45b501c	184	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	185	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	186
	187	l = mbox_read_reg(p->irqenable);
	188	l \|= bit;
	189	mbox_write_reg(l, p->irqenable);
	190	}
	191
bfbdcf8a	192	static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
340a614a HD	193	omap_mbox_type_t irq)
340a614a HD	194	{
b45b501c	195	struct omap_mbox2_priv *p = mbox->priv;
525a1138 HK	196	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	197
	198	if (!cpu_is_omap44xx())
	199	bit = mbox_read_reg(p->irqdisable) & ~bit;
	200
	201	mbox_write_reg(bit, p->irqdisable);
340a614a HD	202	}
340a614a HD	203
bfbdcf8a	204	static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
340a614a HD	205	omap_mbox_type_t irq)
340a614a HD	206	{
b45b501c	207	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	208	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	209
	210	mbox_write_reg(bit, p->irqstatus);
8828880d HD	211
	212	/* Flush posted write for irq status to avoid spurious interrupts */
	213	mbox_read_reg(p->irqstatus);
340a614a HD	214	}
340a614a HD	215
bfbdcf8a	216	static int omap2_mbox_is_irq(struct omap_mbox *mbox,
340a614a HD	217	omap_mbox_type_t irq)
340a614a HD	218	{
b45b501c	219	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	220	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	221	u32 enable = mbox_read_reg(p->irqenable);
	222	u32 status = mbox_read_reg(p->irqstatus);
	223
5f00ec64	224	return (int)(enable & status & bit);
340a614a HD	225	}
340a614a HD	226
c75ee752 HD	227	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	228	{
	229	int i;
	230	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	231	int nr_regs;
	232	if (cpu_is_omap44xx())
	233	nr_regs = OMAP4_MBOX_NR_REGS;
	234	else
	235	nr_regs = MBOX_NR_REGS;
	236	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	237	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	238
	239	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	240	i, p->ctx[i]);
	241	}
	242	}
	243
	244	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	245	{
	246	int i;
	247	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	248	int nr_regs;
	249	if (cpu_is_omap44xx())
	250	nr_regs = OMAP4_MBOX_NR_REGS;
	251	else
	252	nr_regs = MBOX_NR_REGS;
	253	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	254	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	255
	256	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	257	i, p->ctx[i]);
	258	}
	259	}
	260
340a614a HD	261	static struct omap_mbox_ops omap2_mbox_ops = {
	262	.type = OMAP_MBOX_TYPE2,
	263	.startup = omap2_mbox_startup,
	264	.shutdown = omap2_mbox_shutdown,
	265	.fifo_read = omap2_mbox_fifo_read,
	266	.fifo_write = omap2_mbox_fifo_write,
	267	.fifo_empty = omap2_mbox_fifo_empty,
	268	.fifo_full = omap2_mbox_fifo_full,
	269	.enable_irq = omap2_mbox_enable_irq,
	270	.disable_irq = omap2_mbox_disable_irq,
	271	.ack_irq = omap2_mbox_ack_irq,
	272	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	273	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	274	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	275	};
	276
	277	/*
	278	* MAILBOX 0: ARM -> DSP,
	279	* MAILBOX 1: ARM <- DSP.
	280	* MAILBOX 2: ARM -> IVA,
	281	* MAILBOX 3: ARM <- IVA.
	282	*/
	283
	284	/* FIXME: the following structs should be filled automatically by the user id */
07d65d8b	285
ff0fba0b	286	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP2)
340a614a HD	287	/* DSP */
	288	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	289	.tx_fifo = {
733ecc5c HD	290	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	291	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	292	},
340a614a HD	293	.rx_fifo = {
733ecc5c HD	294	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	295	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	296	},
733ecc5c HD	297	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	298	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	299	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
340a614a HD	300	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
5f00ec64 S	301	.irqdisable = MAILBOX_IRQENABLE(0),
	302	};
	303
07d65d8b FC	304	struct omap_mbox mbox_dsp_info = {
	305	.name = "dsp",
	306	.ops = &omap2_mbox_ops,
	307	.priv = &omap2_mbox_dsp_priv,
	308	};
14476bd9	309	#endif
07d65d8b	310
ff0fba0b	311	#if defined(CONFIG_ARCH_OMAP3)
898ee756	312	struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
14476bd9	313	#endif
898ee756	314
07d65d8b	315	#if defined(CONFIG_ARCH_OMAP2420)
07d65d8b FC	316	/* IVA */
	317	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	318	.tx_fifo = {
	319	.msg = MAILBOX_MESSAGE(2),
	320	.fifo_stat = MAILBOX_FIFOSTATUS(2),
	321	},
	322	.rx_fifo = {
	323	.msg = MAILBOX_MESSAGE(3),
	324	.msg_stat = MAILBOX_MSGSTATUS(3),
	325	},
	326	.irqenable = MAILBOX_IRQENABLE(3),
	327	.irqstatus = MAILBOX_IRQSTATUS(3),
	328	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	329	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	330	.irqdisable = MAILBOX_IRQENABLE(3),
	331	};
	332
	333	static struct omap_mbox mbox_iva_info = {
	334	.name = "iva",
	335	.ops = &omap2_mbox_ops,
	336	.priv = &omap2_mbox_iva_priv,
	337	};
898ee756	338
eca83258	339	struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
07d65d8b FC	340	#endif
07d65d8b FC	341
14476bd9	342	#if defined(CONFIG_ARCH_OMAP4)
07d65d8b	343	/* OMAP4 */
5f00ec64 S	344	static struct omap_mbox2_priv omap2_mbox_1_priv = {
	345	.tx_fifo = {
	346	.msg = MAILBOX_MESSAGE(0),
	347	.fifo_stat = MAILBOX_FIFOSTATUS(0),
	348	},
	349	.rx_fifo = {
	350	.msg = MAILBOX_MESSAGE(1),
	351	.msg_stat = MAILBOX_MSGSTATUS(1),
	352	},
	353	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	354	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	355	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	356	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	357	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
340a614a HD	358	};
340a614a HD	359
5f00ec64 S	360	struct omap_mbox mbox_1_info = {
	361	.name = "mailbox-1",
	362	.ops = &omap2_mbox_ops,
	363	.priv = &omap2_mbox_1_priv,
	364	};
5f00ec64	365
5f00ec64 S	366	static struct omap_mbox2_priv omap2_mbox_2_priv = {
	367	.tx_fifo = {
	368	.msg = MAILBOX_MESSAGE(3),
	369	.fifo_stat = MAILBOX_FIFOSTATUS(3),
	370	},
	371	.rx_fifo = {
	372	.msg = MAILBOX_MESSAGE(2),
	373	.msg_stat = MAILBOX_MSGSTATUS(2),
	374	},
	375	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	376	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	377	.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
	378	.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
	379	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
	380	};
	381
	382	struct omap_mbox mbox_2_info = {
	383	.name = "mailbox-2",
	384	.ops = &omap2_mbox_ops,
	385	.priv = &omap2_mbox_2_priv,
	386	};
5f00ec64	387
898ee756	388	struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
14476bd9	389	#endif
898ee756	390
da8cfe03	391	static int __devinit omap2_mbox_probe(struct platform_device *pdev)
340a614a	392	{
898ee756	393	struct resource *mem;
6c20a683	394	int ret;
9c80c8cd	395	struct omap_mbox **list;
340a614a	396
14476bd9 FC	397	if (false)
14476bd9 FC	398	;
ff0fba0b ORL	399	#if defined(CONFIG_ARCH_OMAP3)
ff0fba0b ORL	400	else if (cpu_is_omap34xx()) {
898ee756 FC	401	list = omap3_mboxes;
	402
	403	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
340a614a	404	}
14476bd9	405	#endif
ff0fba0b ORL	406	#if defined(CONFIG_ARCH_OMAP2)
	407	else if (cpu_is_omap2430()) {
	408	list = omap2_mboxes;
	409
	410	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	411	} else if (cpu_is_omap2420()) {
898ee756	412	list = omap2_mboxes;
340a614a	413
898ee756 FC	414	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	415	list[1]->irq = platform_get_irq_byname(pdev, "iva");
	416	}
	417	#endif
14476bd9	418	#if defined(CONFIG_ARCH_OMAP4)
898ee756 FC	419	else if (cpu_is_omap44xx()) {
898ee756 FC	420	list = omap4_mboxes;
5f00ec64	421
898ee756 FC	422	list[0]->irq = list[1]->irq =
898ee756 FC	423	platform_get_irq_byname(pdev, "mbox");
340a614a	424	}
14476bd9	425	#endif
898ee756 FC	426	else {
	427	pr_err("%s: platform not supported\n", __func__);
	428	return -ENODEV;
5f00ec64	429	}
6c20a683	430
898ee756 FC	431	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	432	mbox_base = ioremap(mem->start, resource_size(mem));
	433	if (!mbox_base)
	434	return -ENOMEM;
	435
9c80c8cd FC	436	ret = omap_mbox_register(&pdev->dev, list);
	437	if (ret) {
	438	iounmap(mbox_base);
	439	return ret;
340a614a	440	}
340a614a	441
5d783731	442	return 0;
340a614a HD	443	}
340a614a HD	444
da8cfe03	445	static int __devexit omap2_mbox_remove(struct platform_device *pdev)
340a614a	446	{
9c80c8cd	447	omap_mbox_unregister();
6c20a683	448	iounmap(mbox_base);
340a614a HD	449	return 0;
	450	}
	451
	452	static struct platform_driver omap2_mbox_driver = {
	453	.probe = omap2_mbox_probe,
da8cfe03	454	.remove = __devexit_p(omap2_mbox_remove),
340a614a	455	.driver = {
d742709e	456	.name = "omap-mailbox",
340a614a HD	457	},
	458	};
	459
	460	static int __init omap2_mbox_init(void)
	461	{
	462	return platform_driver_register(&omap2_mbox_driver);
	463	}
	464
	465	static void __exit omap2_mbox_exit(void)
	466	{
	467	platform_driver_unregister(&omap2_mbox_driver);
	468	}
	469
	470	module_init(omap2_mbox_init);
	471	module_exit(omap2_mbox_exit);
	472
733ecc5c	473	MODULE_LICENSE("GPL v2");
5f00ec64	474	MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
f375325a OBC	475	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
f375325a OBC	476	MODULE_AUTHOR("Paul Mundt");
d742709e	477	MODULE_ALIAS("platform:omap2-mailbox");