[deliverable/linux.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <plat/mailbox.h>
#include <mach/irqs.h>

#define DRV_NAME "omap2-mailbox"

#define MAILBOX_REVISION		0x000
#define MAILBOX_SYSCONFIG		0x010
#define MAILBOX_SYSSTATUS		0x014
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))

#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

/* SYSCONFIG: register bit definition */
#define AUTOIDLE	(1 << 0)
#define SOFTRESET	(1 << 1)
#define SMARTIDLE	(2 << 3)
#define OMAP4_SOFTRESET	(1 << 0)
#define OMAP4_NOIDLE	(1 << 2)
#define OMAP4_SMARTIDLE	(2 << 2)

/* SYSSTATUS: register bit definition */
#define RESETDONE	(1 << 0)

#define MBOX_REG_SIZE			0x120

#define OMAP4_MBOX_REG_SIZE		0x130

#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[OMAP4_MBOX_NR_REGS];
	unsigned long irqdisable;
};

static struct clk *mbox_ick_handle;

static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
				  omap_mbox_type_t irq);

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;
	unsigned long timeout;

	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	if (IS_ERR(mbox_ick_handle)) {
		printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
			PTR_ERR(mbox_ick_handle));
		return PTR_ERR(mbox_ick_handle);
	}
	clk_enable(mbox_ick_handle);

	if (cpu_is_omap44xx()) {
		mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
		timeout = jiffies + msecs_to_jiffies(20);
		do {
			l = mbox_read_reg(MAILBOX_SYSCONFIG);
			if (!(l & OMAP4_SOFTRESET))
				break;
		} while (!time_after(jiffies, timeout));

		if (l & OMAP4_SOFTRESET) {
			pr_err("Can't take mailbox out of reset\n");
			return -ENODEV;
		}
	} else {
		mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
		timeout = jiffies + msecs_to_jiffies(20);
		do {
			l = mbox_read_reg(MAILBOX_SYSSTATUS);
			if (l & RESETDONE)
				break;
		} while (!time_after(jiffies, timeout));

		if (!(l & RESETDONE)) {
			pr_err("Can't take mailbox out of reset\n");
			return -ENODEV;
		}
	}

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	if (cpu_is_omap44xx())
		l = OMAP4_SMARTIDLE;
	else
		l = SMARTIDLE | AUTOIDLE;
	mbox_write_reg(l, MAILBOX_SYSCONFIG);

	omap2_mbox_enable_irq(mbox, IRQ_RX);

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	clk_disable(mbox_ick_handle);
	clk_put(mbox_ick_handle);
	mbox_ick_handle = NULL;
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return mbox_read_reg(fifo->fifo_stat);
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	l = mbox_read_reg(p->irqdisable);
	l &= ~bit;
	mbox_write_reg(l, p->irqdisable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);

	/* Flush posted write for irq status to avoid spurious interrupts */
	mbox_read_reg(p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (int)(enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= MAILBOX_IRQENABLE(0),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};

struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };

#if defined(CONFIG_ARCH_OMAP2420)

/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
	.irqdisable	= MAILBOX_IRQENABLE(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};

struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
#endif

/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_1_info = {
	.name	= "mailbox-1",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_1_priv,
};

static struct omap_mbox2_priv omap2_mbox_2_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.msg_stat	= MAILBOX_MSGSTATUS(2),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_2_info = {
	.name	= "mailbox-2",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_2_priv,
};

struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };

static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *mem;
	int ret;
	struct omap_mbox **list;

	if (cpu_is_omap3430()) {
		list = omap3_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	}
#if defined(CONFIG_ARCH_OMAP2420)
	else if (cpu_is_omap2420()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
		list[1]->irq = platform_get_irq_byname(pdev, "iva");
	}
#endif
	else if (cpu_is_omap44xx()) {
		list = omap4_mboxes;

		list[0]->irq = list[1]->irq =
			platform_get_irq_byname(pdev, "mbox");
	}
	else {
		pr_err("%s: platform not supported\n", __func__);
		return -ENODEV;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mbox_base = ioremap(mem->start, resource_size(mem));
	if (!mbox_base)
		return -ENOMEM;

	ret = omap_mbox_register(&pdev->dev, list);
	if (ret) {
		iounmap(mbox_base);
		return ret;
	}
	return 0;

	return ret;
}

static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
	omap_mbox_unregister();
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = __devexit_p(omap2_mbox_remove),
	.driver = {
		.name = DRV_NAME,
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_AUTHOR("Paul Mundt");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/clk.h>
	15	#include <linux/err.h>
	16	#include <linux/platform_device.h>
fced80c7	17	#include <linux/io.h>
ce491cf8	18	#include <plat/mailbox.h>
a09e64fb	19	#include <mach/irqs.h>
340a614a	20
5f00ec64 S	21	#define DRV_NAME "omap2-mailbox"
5f00ec64 S	22
733ecc5c HD	23	#define MAILBOX_REVISION 0x000
	24	#define MAILBOX_SYSCONFIG 0x010
	25	#define MAILBOX_SYSSTATUS 0x014
	26	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	27	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	28	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	29	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	30	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	31
5f00ec64 S	32	#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
	33	#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
	34	#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
	35
	36	#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
	37	#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
340a614a	38
1ffe627d HD	39	/* SYSCONFIG: register bit definition */
	40	#define AUTOIDLE (1 << 0)
	41	#define SOFTRESET (1 << 1)
	42	#define SMARTIDLE (2 << 3)
a6a60228	43	#define OMAP4_SOFTRESET (1 << 0)
4499ce42 SA	44	#define OMAP4_NOIDLE (1 << 2)
4499ce42 SA	45	#define OMAP4_SMARTIDLE (2 << 2)
1ffe627d HD	46
	47	/* SYSSTATUS: register bit definition */
	48	#define RESETDONE (1 << 0)
	49
c75ee752	50	#define MBOX_REG_SIZE 0x120
5f00ec64 S	51
	52	#define OMAP4_MBOX_REG_SIZE 0x130
	53
c75ee752	54	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
5f00ec64	55	#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
c75ee752	56
6c20a683	57	static void __iomem *mbox_base;
340a614a HD	58
	59	struct omap_mbox2_fifo {
	60	unsigned long msg;
	61	unsigned long fifo_stat;
	62	unsigned long msg_stat;
	63	};
	64
	65	struct omap_mbox2_priv {
	66	struct omap_mbox2_fifo tx_fifo;
	67	struct omap_mbox2_fifo rx_fifo;
	68	unsigned long irqenable;
	69	unsigned long irqstatus;
	70	u32 newmsg_bit;
	71	u32 notfull_bit;
5f00ec64 S	72	u32 ctx[OMAP4_MBOX_NR_REGS];
5f00ec64 S	73	unsigned long irqdisable;
340a614a HD	74	};
	75
	76	static struct clk *mbox_ick_handle;
	77
bfbdcf8a HD	78	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
	79	omap_mbox_type_t irq);
	80
6c20a683	81	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	82	{
6c20a683	83	return __raw_readl(mbox_base + ofs);
340a614a HD	84	}
340a614a HD	85
6c20a683	86	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	87	{
6c20a683	88	__raw_writel(val, mbox_base + ofs);
340a614a HD	89	}
	90
	91	/* Mailbox H/W preparations */
bfbdcf8a	92	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	93	{
1ffe627d HD	94	u32 l;
1ffe627d HD	95	unsigned long timeout;
340a614a HD	96
	97	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	98	if (IS_ERR(mbox_ick_handle)) {
0cd7e1cc	99	printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
5f00ec64 S	100	PTR_ERR(mbox_ick_handle));
5f00ec64 S	101	return PTR_ERR(mbox_ick_handle);
340a614a HD	102	}
	103	clk_enable(mbox_ick_handle);
	104
a6a60228 SA	105	if (cpu_is_omap44xx()) {
	106	mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
	107	timeout = jiffies + msecs_to_jiffies(20);
	108	do {
	109	l = mbox_read_reg(MAILBOX_SYSCONFIG);
	110	if (!(l & OMAP4_SOFTRESET))
	111	break;
	112	} while (!time_after(jiffies, timeout));
	113
	114	if (l & OMAP4_SOFTRESET) {
	115	pr_err("Can't take mailbox out of reset\n");
	116	return -ENODEV;
	117	}
	118	} else {
	119	mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
	120	timeout = jiffies + msecs_to_jiffies(20);
	121	do {
	122	l = mbox_read_reg(MAILBOX_SYSSTATUS);
	123	if (l & RESETDONE)
	124	break;
	125	} while (!time_after(jiffies, timeout));
	126
	127	if (!(l & RESETDONE)) {
	128	pr_err("Can't take mailbox out of reset\n");
	129	return -ENODEV;
	130	}
1ffe627d HD	131	}
1ffe627d HD	132
94fc58c6	133	l = mbox_read_reg(MAILBOX_REVISION);
909f9dc7	134	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
94fc58c6	135
4499ce42 SA	136	if (cpu_is_omap44xx())
	137	l = OMAP4_SMARTIDLE;
	138	else
	139	l = SMARTIDLE \| AUTOIDLE;
340a614a HD	140	mbox_write_reg(l, MAILBOX_SYSCONFIG);
340a614a HD	141
bfbdcf8a HD	142	omap2_mbox_enable_irq(mbox, IRQ_RX);
bfbdcf8a HD	143
340a614a HD	144	return 0;
	145	}
	146
bfbdcf8a	147	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a HD	148	{
	149	clk_disable(mbox_ick_handle);
	150	clk_put(mbox_ick_handle);
5f00ec64	151	mbox_ick_handle = NULL;
340a614a HD	152	}
	153
	154	/* Mailbox FIFO handle functions */
bfbdcf8a	155	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	156	{
	157	struct omap_mbox2_fifo *fifo =
	158	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	159	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	160	}
	161
bfbdcf8a	162	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	163	{
	164	struct omap_mbox2_fifo *fifo =
	165	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	166	mbox_write_reg(msg, fifo->msg);
	167	}
	168
bfbdcf8a	169	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	170	{
	171	struct omap_mbox2_fifo *fifo =
	172	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	173	return (mbox_read_reg(fifo->msg_stat) == 0);
	174	}
	175
bfbdcf8a	176	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	177	{
	178	struct omap_mbox2_fifo *fifo =
	179	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
5f00ec64	180	return mbox_read_reg(fifo->fifo_stat);
340a614a HD	181	}
	182
	183	/* Mailbox IRQ handle functions */
bfbdcf8a	184	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
340a614a HD	185	omap_mbox_type_t irq)
	186	{
	187	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	188	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	189
	190	l = mbox_read_reg(p->irqenable);
	191	l \|= bit;
	192	mbox_write_reg(l, p->irqenable);
	193	}
	194
bfbdcf8a	195	static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
340a614a HD	196	omap_mbox_type_t irq)
	197	{
	198	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	199	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
5f00ec64	200	l = mbox_read_reg(p->irqdisable);
340a614a	201	l &= ~bit;
5f00ec64	202	mbox_write_reg(l, p->irqdisable);
340a614a HD	203	}
340a614a HD	204
bfbdcf8a	205	static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
340a614a HD	206	omap_mbox_type_t irq)
	207	{
	208	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	209	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	210
	211	mbox_write_reg(bit, p->irqstatus);
8828880d HD	212
	213	/* Flush posted write for irq status to avoid spurious interrupts */
	214	mbox_read_reg(p->irqstatus);
340a614a HD	215	}
340a614a HD	216
bfbdcf8a	217	static int omap2_mbox_is_irq(struct omap_mbox *mbox,
340a614a HD	218	omap_mbox_type_t irq)
	219	{
	220	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	221	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	222	u32 enable = mbox_read_reg(p->irqenable);
	223	u32 status = mbox_read_reg(p->irqstatus);
	224
5f00ec64	225	return (int)(enable & status & bit);
340a614a HD	226	}
340a614a HD	227
c75ee752 HD	228	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	229	{
	230	int i;
	231	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	232	int nr_regs;
	233	if (cpu_is_omap44xx())
	234	nr_regs = OMAP4_MBOX_NR_REGS;
	235	else
	236	nr_regs = MBOX_NR_REGS;
	237	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	238	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	239
	240	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	241	i, p->ctx[i]);
	242	}
	243	}
	244
	245	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	246	{
	247	int i;
	248	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	249	int nr_regs;
	250	if (cpu_is_omap44xx())
	251	nr_regs = OMAP4_MBOX_NR_REGS;
	252	else
	253	nr_regs = MBOX_NR_REGS;
	254	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	255	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	256
	257	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	258	i, p->ctx[i]);
	259	}
	260	}
	261
340a614a HD	262	static struct omap_mbox_ops omap2_mbox_ops = {
	263	.type = OMAP_MBOX_TYPE2,
	264	.startup = omap2_mbox_startup,
	265	.shutdown = omap2_mbox_shutdown,
	266	.fifo_read = omap2_mbox_fifo_read,
	267	.fifo_write = omap2_mbox_fifo_write,
	268	.fifo_empty = omap2_mbox_fifo_empty,
	269	.fifo_full = omap2_mbox_fifo_full,
	270	.enable_irq = omap2_mbox_enable_irq,
	271	.disable_irq = omap2_mbox_disable_irq,
	272	.ack_irq = omap2_mbox_ack_irq,
	273	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	274	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	275	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	276	};
	277
	278	/*
	279	* MAILBOX 0: ARM -> DSP,
	280	* MAILBOX 1: ARM <- DSP.
	281	* MAILBOX 2: ARM -> IVA,
	282	* MAILBOX 3: ARM <- IVA.
	283	*/
	284
	285	/* FIXME: the following structs should be filled automatically by the user id */
07d65d8b	286
340a614a HD	287	/* DSP */
	288	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	289	.tx_fifo = {
733ecc5c HD	290	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	291	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	292	},
340a614a HD	293	.rx_fifo = {
733ecc5c HD	294	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	295	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	296	},
733ecc5c HD	297	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	298	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	299	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
340a614a HD	300	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
5f00ec64 S	301	.irqdisable = MAILBOX_IRQENABLE(0),
	302	};
	303
07d65d8b FC	304	struct omap_mbox mbox_dsp_info = {
	305	.name = "dsp",
	306	.ops = &omap2_mbox_ops,
	307	.priv = &omap2_mbox_dsp_priv,
	308	};
07d65d8b	309
898ee756 FC	310	struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
898ee756 FC	311
07d65d8b FC	312	#if defined(CONFIG_ARCH_OMAP2420)
	313
	314	/* IVA */
	315	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	316	.tx_fifo = {
	317	.msg = MAILBOX_MESSAGE(2),
	318	.fifo_stat = MAILBOX_FIFOSTATUS(2),
	319	},
	320	.rx_fifo = {
	321	.msg = MAILBOX_MESSAGE(3),
	322	.msg_stat = MAILBOX_MSGSTATUS(3),
	323	},
	324	.irqenable = MAILBOX_IRQENABLE(3),
	325	.irqstatus = MAILBOX_IRQSTATUS(3),
	326	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	327	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	328	.irqdisable = MAILBOX_IRQENABLE(3),
	329	};
	330
	331	static struct omap_mbox mbox_iva_info = {
	332	.name = "iva",
	333	.ops = &omap2_mbox_ops,
	334	.priv = &omap2_mbox_iva_priv,
	335	};
898ee756 FC	336
898ee756 FC	337	struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
07d65d8b FC	338	#endif
	339
	340	/* OMAP4 */
5f00ec64 S	341	static struct omap_mbox2_priv omap2_mbox_1_priv = {
	342	.tx_fifo = {
	343	.msg = MAILBOX_MESSAGE(0),
	344	.fifo_stat = MAILBOX_FIFOSTATUS(0),
	345	},
	346	.rx_fifo = {
	347	.msg = MAILBOX_MESSAGE(1),
	348	.msg_stat = MAILBOX_MSGSTATUS(1),
	349	},
	350	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	351	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	352	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	353	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	354	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
340a614a HD	355	};
340a614a HD	356
5f00ec64 S	357	struct omap_mbox mbox_1_info = {
	358	.name = "mailbox-1",
	359	.ops = &omap2_mbox_ops,
	360	.priv = &omap2_mbox_1_priv,
	361	};
5f00ec64	362
5f00ec64 S	363	static struct omap_mbox2_priv omap2_mbox_2_priv = {
	364	.tx_fifo = {
	365	.msg = MAILBOX_MESSAGE(3),
	366	.fifo_stat = MAILBOX_FIFOSTATUS(3),
	367	},
	368	.rx_fifo = {
	369	.msg = MAILBOX_MESSAGE(2),
	370	.msg_stat = MAILBOX_MSGSTATUS(2),
	371	},
	372	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	373	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	374	.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
	375	.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
	376	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
	377	};
	378
	379	struct omap_mbox mbox_2_info = {
	380	.name = "mailbox-2",
	381	.ops = &omap2_mbox_ops,
	382	.priv = &omap2_mbox_2_priv,
	383	};
5f00ec64	384
898ee756 FC	385	struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
898ee756 FC	386
da8cfe03	387	static int __devinit omap2_mbox_probe(struct platform_device *pdev)
340a614a	388	{
898ee756	389	struct resource *mem;
6c20a683	390	int ret;
9c80c8cd	391	struct omap_mbox **list;
340a614a	392
898ee756 FC	393	if (cpu_is_omap3430()) {
	394	list = omap3_mboxes;
	395
	396	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
340a614a	397	}
898ee756 FC	398	#if defined(CONFIG_ARCH_OMAP2420)
	399	else if (cpu_is_omap2420()) {
	400	list = omap2_mboxes;
340a614a	401
898ee756 FC	402	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	403	list[1]->irq = platform_get_irq_byname(pdev, "iva");
	404	}
	405	#endif
	406	else if (cpu_is_omap44xx()) {
	407	list = omap4_mboxes;
5f00ec64	408
898ee756 FC	409	list[0]->irq = list[1]->irq =
898ee756 FC	410	platform_get_irq_byname(pdev, "mbox");
340a614a	411	}
898ee756 FC	412	else {
	413	pr_err("%s: platform not supported\n", __func__);
	414	return -ENODEV;
5f00ec64	415	}
6c20a683	416
898ee756 FC	417	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	418	mbox_base = ioremap(mem->start, resource_size(mem));
	419	if (!mbox_base)
	420	return -ENOMEM;
	421
9c80c8cd FC	422	ret = omap_mbox_register(&pdev->dev, list);
	423	if (ret) {
	424	iounmap(mbox_base);
	425	return ret;
340a614a	426	}
6c20a683	427	return 0;
340a614a HD	428
	429	return ret;
	430	}
	431
da8cfe03	432	static int __devexit omap2_mbox_remove(struct platform_device *pdev)
340a614a	433	{
9c80c8cd	434	omap_mbox_unregister();
6c20a683	435	iounmap(mbox_base);
340a614a HD	436	return 0;
	437	}
	438
	439	static struct platform_driver omap2_mbox_driver = {
	440	.probe = omap2_mbox_probe,
da8cfe03	441	.remove = __devexit_p(omap2_mbox_remove),
340a614a	442	.driver = {
5f00ec64	443	.name = DRV_NAME,
340a614a HD	444	},
	445	};
	446
	447	static int __init omap2_mbox_init(void)
	448	{
	449	return platform_driver_register(&omap2_mbox_driver);
	450	}
	451
	452	static void __exit omap2_mbox_exit(void)
	453	{
	454	platform_driver_unregister(&omap2_mbox_driver);
	455	}
	456
	457	module_init(omap2_mbox_init);
	458	module_exit(omap2_mbox_exit);
	459
733ecc5c	460	MODULE_LICENSE("GPL v2");
5f00ec64	461	MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
f375325a OBC	462	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
f375325a OBC	463	MODULE_AUTHOR("Paul Mundt");
5f00ec64	464	MODULE_ALIAS("platform:"DRV_NAME);