[deliverable/linux.git] / arch / arm / mach-omap2 / mcbsp.c

/*
 * linux/arch/arm/mach-omap2/mcbsp.c
 *
 * Copyright (C) 2008 Instituto Nokia de Tecnologia
 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Multichannel mode not supported.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <plat/dma.h>
#include <plat/cpu.h>
#include <plat/mcbsp.h>
#include <plat/omap_device.h>
#include <linux/pm_runtime.h>

#include "control.h"

/*
 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
 */
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/* McBSP1 internal signal muxing function for OMAP2/3 */
static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP2_MCBSP1_CLKR_MASK;
		else if (!strcmp(src, "clkx"))
			v |= OMAP2_MCBSP1_CLKR_MASK;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP2_MCBSP1_FSR_MASK;
		else if (!strcmp(src, "fsx"))
			v |= OMAP2_MCBSP1_FSR_MASK;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);

	return 0;
}

/* McBSP4 internal signal muxing function for OMAP4 */
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	/*
	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	 * mux) is used */
	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else if (!strcmp(src, "clkx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else if (!strcmp(src, "fsx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	return 0;
}

/* McBSP CLKS source switching function */
static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
				   const char *src)
{
	struct clk *fck_src;
	char *fck_src_name;
	int r;

	if (!strcmp(src, "clks_ext"))
		fck_src_name = "pad_fck";
	else if (!strcmp(src, "clks_fclk"))
		fck_src_name = "prcm_fck";
	else
		return -EINVAL;

	fck_src = clk_get(dev, fck_src_name);
	if (IS_ERR_OR_NULL(fck_src)) {
		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
		       fck_src_name);
		return -EINVAL;
	}

	pm_runtime_put_sync(dev);

	r = clk_set_parent(clk, fck_src);
	if (IS_ERR_VALUE(r)) {
		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
		       "clks", fck_src_name);
		clk_put(fck_src);
		return -EINVAL;
	}

	pm_runtime_get_sync(dev);

	clk_put(fck_src);

	return 0;
}

static int omap3_enable_st_clock(unsigned int id, bool enable)
{
	unsigned int w;

	/*
	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
	 * are enabled or sidetones start sounding ugly.
	 */
	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	if (enable)
		w &= ~(1 << (id - 2));
	else
		w |= 1 << (id - 2);
	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);

	return 0;
}

static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
{
	int id, count = 1;
	char *name = "omap-mcbsp";
	struct omap_hwmod *oh_device[2];
	struct omap_mcbsp_platform_data *pdata = NULL;
	struct platform_device *pdev;

	sscanf(oh->name, "mcbsp%d", &id);

	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for mcbsp\n", __func__);
		return -ENOMEM;
	}

	pdata->reg_step = 4;
	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
		pdata->reg_size = 2;
	} else {
		pdata->reg_size = 4;
		pdata->has_ccr = true;
	}
	pdata->set_clk_src = omap2_mcbsp_set_clk_src;

	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;

	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;

	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
		if (id == 2)
			/* The FIFO has 1024 + 256 locations */
			pdata->buffer_size = 0x500;
		else
			/* The FIFO has 128 locations */
			pdata->buffer_size = 0x80;
	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
		/* The FIFO has 128 locations for all instances */
		pdata->buffer_size = 0x80;
	}

	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
		pdata->has_wakeup = true;

	oh_device[0] = oh;

	if (oh->dev_attr) {
		oh_device[1] = omap_hwmod_lookup((
		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
		pdata->enable_st_clock = omap3_enable_st_clock;
		count++;
	}
	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
				sizeof(*pdata), NULL, 0, false);
	kfree(pdata);
	if (IS_ERR(pdev))  {
		pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
					name, oh->name);
		return PTR_ERR(pdev);
	}
	return 0;
}

static int __init omap2_mcbsp_init(void)
{
	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);

	return 0;
}
arch_initcall(omap2_mcbsp_init);
Commit	Line	Data
78673bc8 EV	1	/*
	2	* linux/arch/arm/mach-omap2/mcbsp.c
	3	*
	4	* Copyright (C) 2008 Instituto Nokia de Tecnologia
	5	* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Multichannel mode not supported.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
78673bc8	20
ce491cf8	21	#include <plat/dma.h>
ce491cf8 TL	22	#include <plat/cpu.h>
ce491cf8 TL	23	#include <plat/mcbsp.h>
64bcbd33	24	#include <plat/omap_device.h>
e95496d4	25	#include <linux/pm_runtime.h>
4814ced5 PW	26
	27	#include "control.h"
	28
1743d14f JN	29	/*
	30	* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
	31	* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
	32	*/
	33	#include "cm2xxx_3xxx.h"
	34	#include "cm-regbits-34xx.h"
	35
40c0764b	36	/* McBSP1 internal signal muxing function for OMAP2/3 */
7bc0c4ba JN	37	static int omap2_mcbsp1_mux_rx_clk(struct device dev, const char signal,
7bc0c4ba JN	38	const char *src)
cf4c87ab PW	39	{
	40	u32 v;
	41
	42	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
cf4c87ab	43
7bc0c4ba JN	44	if (!strcmp(signal, "clkr")) {
	45	if (!strcmp(src, "clkr"))
	46	v &= ~OMAP2_MCBSP1_CLKR_MASK;
	47	else if (!strcmp(src, "clkx"))
	48	v \|= OMAP2_MCBSP1_CLKR_MASK;
	49	else
	50	return -EINVAL;
	51	} else if (!strcmp(signal, "fsr")) {
	52	if (!strcmp(src, "fsr"))
	53	v &= ~OMAP2_MCBSP1_FSR_MASK;
	54	else if (!strcmp(src, "fsx"))
	55	v \|= OMAP2_MCBSP1_FSR_MASK;
	56	else
	57	return -EINVAL;
	58	} else {
	59	return -EINVAL;
	60	}
cf4c87ab	61
cf4c87ab	62	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
7bc0c4ba JN	63
7bc0c4ba JN	64	return 0;
cf4c87ab	65	}
cf4c87ab	66
40c0764b PU	67	/* McBSP4 internal signal muxing function for OMAP4 */
	68	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
	69	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
	70	static int omap4_mcbsp4_mux_rx_clk(struct device dev, const char signal,
	71	const char *src)
	72	{
	73	u32 v;
	74
	75	/*
	76	* In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	77	* mux) is used */
	78	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	79
	80	if (!strcmp(signal, "clkr")) {
	81	if (!strcmp(src, "clkr"))
	82	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	83	else if (!strcmp(src, "clkx"))
	84	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	85	else
	86	return -EINVAL;
	87	} else if (!strcmp(signal, "fsr")) {
	88	if (!strcmp(src, "fsr"))
	89	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	90	else if (!strcmp(src, "fsx"))
	91	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	92	else
	93	return -EINVAL;
	94	} else {
	95	return -EINVAL;
	96	}
	97
	98	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	99
	100	return 0;
	101	}
	102
d1358657	103	/* McBSP CLKS source switching function */
09d28d2c JN	104	static int omap2_mcbsp_set_clk_src(struct device dev, struct clk clk,
09d28d2c JN	105	const char *src)
d1358657	106	{
d1358657 PW	107	struct clk *fck_src;
	108	char *fck_src_name;
	109	int r;
	110
09d28d2c	111	if (!strcmp(src, "clks_ext"))
d1358657	112	fck_src_name = "pad_fck";
09d28d2c	113	else if (!strcmp(src, "clks_fclk"))
d1358657 PW	114	fck_src_name = "prcm_fck";
	115	else
	116	return -EINVAL;
	117
09d28d2c	118	fck_src = clk_get(dev, fck_src_name);
d1358657 PW	119	if (IS_ERR_OR_NULL(fck_src)) {
	120	pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
	121	fck_src_name);
	122	return -EINVAL;
	123	}
	124
09d28d2c	125	pm_runtime_put_sync(dev);
d1358657	126
09d28d2c	127	r = clk_set_parent(clk, fck_src);
d1358657 PW	128	if (IS_ERR_VALUE(r)) {
	129	pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
	130	"clks", fck_src_name);
	131	clk_put(fck_src);
	132	return -EINVAL;
	133	}
	134
09d28d2c	135	pm_runtime_get_sync(dev);
d1358657 PW	136
	137	clk_put(fck_src);
	138
	139	return 0;
	140	}
d1358657	141
1743d14f JN	142	static int omap3_enable_st_clock(unsigned int id, bool enable)
	143	{
	144	unsigned int w;
	145
	146	/*
	147	* Sidetone uses McBSP ICLK - which must not idle when sidetones
	148	* are enabled or sidetones start sounding ugly.
	149	*/
	150	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	151	if (enable)
	152	w &= ~(1 << (id - 2));
	153	else
	154	w \|= 1 << (id - 2);
	155	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
	156
	157	return 0;
	158	}
	159
9cf793f9	160	static int __init omap_init_mcbsp(struct omap_hwmod oh, void unused)
64bcbd33 KVA	161	{
	162	int id, count = 1;
	163	char *name = "omap-mcbsp";
	164	struct omap_hwmod *oh_device[2];
	165	struct omap_mcbsp_platform_data *pdata = NULL;
3528c58e	166	struct platform_device *pdev;
3cf32bba	167
64bcbd33	168	sscanf(oh->name, "mcbsp%d", &id);
78673bc8	169
64bcbd33 KVA	170	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	171	if (!pdata) {
	172	pr_err("%s: No memory for mcbsp\n", __func__);
	173	return -ENOMEM;
	174	}
3cf32bba	175
cdc71514	176	pdata->reg_step = 4;
88408230	177	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
cdc71514	178	pdata->reg_size = 2;
88408230	179	} else {
cdc71514	180	pdata->reg_size = 4;
88408230 JN	181	pdata->has_ccr = true;
88408230 JN	182	}
0c8551e5	183	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
40c0764b PU	184
	185	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	186	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
0c8551e5	187	pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
9504ba64	188
40c0764b PU	189	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	190	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
	191	pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
	192
64bcbd33 KVA	193	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
	194	if (id == 2)
	195	/* The FIFO has 1024 + 256 locations */
	196	pdata->buffer_size = 0x500;
	197	else
	198	/* The FIFO has 128 locations */
	199	pdata->buffer_size = 0x80;
da76250e PU	200	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
	201	/* The FIFO has 128 locations for all instances */
	202	pdata->buffer_size = 0x80;
64bcbd33	203	}
3cf32bba	204
1a645884 JN	205	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
	206	pdata->has_wakeup = true;
	207
64bcbd33	208	oh_device[0] = oh;
78673bc8	209
64bcbd33 KVA	210	if (oh->dev_attr) {
	211	oh_device[1] = omap_hwmod_lookup((
	212	(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
1743d14f	213	pdata->enable_st_clock = omap3_enable_st_clock;
64bcbd33 KVA	214	count++;
64bcbd33 KVA	215	}
3528c58e	216	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
f718e2c0	217	sizeof(*pdata), NULL, 0, false);
64bcbd33	218	kfree(pdata);
3528c58e	219	if (IS_ERR(pdev)) {
25985edc	220	pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
64bcbd33	221	name, oh->name);
3528c58e	222	return PTR_ERR(pdev);
64bcbd33	223	}
64bcbd33 KVA	224	return 0;
64bcbd33 KVA	225	}
a5b92cc3	226
b4b58f58	227	static int __init omap2_mcbsp_init(void)
78673bc8	228	{
64bcbd33	229	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
b4b58f58	230
0210dc4e	231	return 0;
78673bc8 EV	232	}
78673bc8 EV	233	arch_initcall(omap2_mcbsp_init);