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90c62bf0 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/mmc-twl4030.c | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Author: Texas Instruments | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/i2c/twl4030.h> | |
01971f65 | 20 | #include <linux/regulator/machine.h> |
90c62bf0 TL |
21 | |
22 | #include <mach/hardware.h> | |
23 | #include <mach/control.h> | |
24 | #include <mach/mmc.h> | |
25 | #include <mach/board.h> | |
26 | ||
27 | #include "mmc-twl4030.h" | |
28 | ||
29 | #if defined(CONFIG_TWL4030_CORE) && \ | |
30 | (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) | |
31 | ||
32 | #define LDO_CLR 0x00 | |
33 | #define VSEL_S2_CLR 0x40 | |
34 | ||
35 | #define VMMC1_DEV_GRP 0x27 | |
36 | #define VMMC1_CLR 0x00 | |
37 | #define VMMC1_315V 0x03 | |
38 | #define VMMC1_300V 0x02 | |
39 | #define VMMC1_285V 0x01 | |
40 | #define VMMC1_185V 0x00 | |
41 | #define VMMC1_DEDICATED 0x2A | |
42 | ||
43 | #define VMMC2_DEV_GRP 0x2B | |
44 | #define VMMC2_CLR 0x40 | |
45 | #define VMMC2_315V 0x0c | |
46 | #define VMMC2_300V 0x0b | |
47 | #define VMMC2_285V 0x0a | |
0329c377 | 48 | #define VMMC2_280V 0x09 |
90c62bf0 TL |
49 | #define VMMC2_260V 0x08 |
50 | #define VMMC2_185V 0x06 | |
51 | #define VMMC2_DEDICATED 0x2E | |
52 | ||
53 | #define VMMC_DEV_GRP_P1 0x20 | |
54 | ||
55 | static u16 control_pbias_offset; | |
56 | static u16 control_devconf1_offset; | |
57 | ||
58 | #define HSMMC_NAME_LEN 9 | |
59 | ||
60 | static struct twl_mmc_controller { | |
61 | struct omap_mmc_platform_data *mmc; | |
62 | u8 twl_vmmc_dev_grp; | |
63 | u8 twl_mmc_dedicated; | |
8466032d | 64 | char name[HSMMC_NAME_LEN + 1]; |
07d83cc9 | 65 | } hsmmc[OMAP34XX_NR_MMC] = { |
90c62bf0 TL |
66 | { |
67 | .twl_vmmc_dev_grp = VMMC1_DEV_GRP, | |
68 | .twl_mmc_dedicated = VMMC1_DEDICATED, | |
69 | }, | |
70 | { | |
71 | .twl_vmmc_dev_grp = VMMC2_DEV_GRP, | |
72 | .twl_mmc_dedicated = VMMC2_DEDICATED, | |
73 | }, | |
74 | }; | |
75 | ||
76 | static int twl_mmc_card_detect(int irq) | |
77 | { | |
78 | unsigned i; | |
79 | ||
80 | for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { | |
81 | struct omap_mmc_platform_data *mmc; | |
82 | ||
83 | mmc = hsmmc[i].mmc; | |
84 | if (!mmc) | |
85 | continue; | |
86 | if (irq != mmc->slots[0].card_detect_irq) | |
87 | continue; | |
88 | ||
89 | /* NOTE: assumes card detect signal is active-low */ | |
90 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
91 | } | |
92 | return -ENOSYS; | |
93 | } | |
94 | ||
95 | static int twl_mmc_get_ro(struct device *dev, int slot) | |
96 | { | |
97 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
98 | ||
99 | /* NOTE: assumes write protect signal is active-high */ | |
100 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
101 | } | |
102 | ||
8d75e98b AH |
103 | static int twl_mmc_get_cover_state(struct device *dev, int slot) |
104 | { | |
105 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
106 | ||
107 | /* NOTE: assumes card detect signal is active-low */ | |
108 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
109 | } | |
110 | ||
90c62bf0 TL |
111 | /* |
112 | * MMC Slot Initialization. | |
113 | */ | |
114 | static int twl_mmc_late_init(struct device *dev) | |
115 | { | |
116 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
117 | int ret = 0; | |
118 | int i; | |
119 | ||
120 | ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); | |
121 | if (ret) | |
122 | goto done; | |
123 | ret = gpio_direction_input(mmc->slots[0].switch_pin); | |
124 | if (ret) | |
125 | goto err; | |
126 | ||
127 | for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { | |
128 | if (hsmmc[i].name == mmc->slots[0].name) { | |
129 | hsmmc[i].mmc = mmc; | |
130 | break; | |
131 | } | |
132 | } | |
133 | ||
134 | return 0; | |
135 | ||
136 | err: | |
137 | gpio_free(mmc->slots[0].switch_pin); | |
138 | done: | |
139 | mmc->slots[0].card_detect_irq = 0; | |
140 | mmc->slots[0].card_detect = NULL; | |
141 | ||
142 | dev_err(dev, "err %d configuring card detect\n", ret); | |
143 | return ret; | |
144 | } | |
145 | ||
146 | static void twl_mmc_cleanup(struct device *dev) | |
147 | { | |
148 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
149 | ||
150 | gpio_free(mmc->slots[0].switch_pin); | |
151 | } | |
152 | ||
153 | #ifdef CONFIG_PM | |
154 | ||
155 | static int twl_mmc_suspend(struct device *dev, int slot) | |
156 | { | |
157 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
158 | ||
159 | disable_irq(mmc->slots[0].card_detect_irq); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | static int twl_mmc_resume(struct device *dev, int slot) | |
164 | { | |
165 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
166 | ||
167 | enable_irq(mmc->slots[0].card_detect_irq); | |
168 | return 0; | |
169 | } | |
170 | ||
171 | #else | |
172 | #define twl_mmc_suspend NULL | |
173 | #define twl_mmc_resume NULL | |
174 | #endif | |
175 | ||
176 | /* | |
177 | * Sets the MMC voltage in twl4030 | |
178 | */ | |
0329c377 DB |
179 | |
180 | #define MMC1_OCR (MMC_VDD_165_195 \ | |
181 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | |
182 | #define MMC2_OCR (MMC_VDD_165_195 \ | |
183 | |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \ | |
184 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | |
185 | ||
90c62bf0 TL |
186 | static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) |
187 | { | |
188 | int ret; | |
034ae7b4 DB |
189 | u8 vmmc = 0, dev_grp_val; |
190 | ||
191 | if (!vdd) | |
192 | goto doit; | |
90c62bf0 | 193 | |
0329c377 DB |
194 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) { |
195 | /* VMMC1: max 220 mA. And for 8-bit mode, | |
196 | * VSIM: max 50 mA | |
197 | */ | |
198 | switch (1 << vdd) { | |
199 | case MMC_VDD_165_195: | |
90c62bf0 | 200 | vmmc = VMMC1_185V; |
0329c377 DB |
201 | /* and VSIM_180V */ |
202 | break; | |
203 | case MMC_VDD_28_29: | |
204 | vmmc = VMMC1_285V; | |
205 | /* and VSIM_280V */ | |
206 | break; | |
207 | case MMC_VDD_29_30: | |
208 | case MMC_VDD_30_31: | |
209 | vmmc = VMMC1_300V; | |
210 | /* and VSIM_300V */ | |
211 | break; | |
212 | case MMC_VDD_31_32: | |
213 | vmmc = VMMC1_315V; | |
214 | /* error if VSIM needed */ | |
215 | break; | |
216 | default: | |
034ae7b4 | 217 | return -EINVAL; |
0329c377 DB |
218 | } |
219 | } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) { | |
220 | /* VMMC2: max 100 mA */ | |
221 | switch (1 << vdd) { | |
222 | case MMC_VDD_165_195: | |
90c62bf0 | 223 | vmmc = VMMC2_185V; |
0329c377 DB |
224 | break; |
225 | case MMC_VDD_25_26: | |
226 | case MMC_VDD_26_27: | |
227 | vmmc = VMMC2_260V; | |
228 | break; | |
229 | case MMC_VDD_27_28: | |
230 | vmmc = VMMC2_280V; | |
231 | break; | |
232 | case MMC_VDD_28_29: | |
233 | vmmc = VMMC2_285V; | |
234 | break; | |
235 | case MMC_VDD_29_30: | |
236 | case MMC_VDD_30_31: | |
237 | vmmc = VMMC2_300V; | |
238 | break; | |
239 | case MMC_VDD_31_32: | |
240 | vmmc = VMMC2_315V; | |
241 | break; | |
242 | default: | |
034ae7b4 | 243 | return -EINVAL; |
0329c377 DB |
244 | } |
245 | } else { | |
034ae7b4 | 246 | return -EINVAL; |
90c62bf0 TL |
247 | } |
248 | ||
034ae7b4 DB |
249 | doit: |
250 | if (vdd) | |
90c62bf0 TL |
251 | dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ |
252 | else | |
253 | dev_grp_val = LDO_CLR; /* Power down */ | |
254 | ||
255 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | |
256 | dev_grp_val, c->twl_vmmc_dev_grp); | |
034ae7b4 | 257 | if (ret || !vdd) |
90c62bf0 TL |
258 | return ret; |
259 | ||
260 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | |
261 | vmmc, c->twl_mmc_dedicated); | |
262 | ||
263 | return ret; | |
264 | } | |
265 | ||
266 | static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, | |
267 | int vdd) | |
268 | { | |
269 | u32 reg; | |
270 | int ret = 0; | |
271 | struct twl_mmc_controller *c = &hsmmc[0]; | |
272 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
273 | ||
0329c377 DB |
274 | /* |
275 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | |
276 | * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both | |
277 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | |
278 | * | |
279 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | |
280 | * is most naturally TWL VSIM; those pins also use PBIAS. | |
281 | */ | |
90c62bf0 TL |
282 | if (power_on) { |
283 | if (cpu_is_omap2430()) { | |
284 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | |
285 | if ((1 << vdd) >= MMC_VDD_30_31) | |
286 | reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
287 | else | |
288 | reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; | |
289 | omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); | |
290 | } | |
291 | ||
292 | if (mmc->slots[0].internal_clock) { | |
293 | reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
294 | reg |= OMAP2_MMCSDIO1ADPCLKISEL; | |
295 | omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); | |
296 | } | |
297 | ||
298 | reg = omap_ctrl_readl(control_pbias_offset); | |
299 | reg |= OMAP2_PBIASSPEEDCTRL0; | |
300 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | |
301 | omap_ctrl_writel(reg, control_pbias_offset); | |
302 | ||
303 | ret = twl_mmc_set_voltage(c, vdd); | |
304 | ||
305 | /* 100ms delay required for PBIAS configuration */ | |
306 | msleep(100); | |
307 | reg = omap_ctrl_readl(control_pbias_offset); | |
308 | reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); | |
309 | if ((1 << vdd) <= MMC_VDD_165_195) | |
310 | reg &= ~OMAP2_PBIASLITEVMODE0; | |
311 | else | |
312 | reg |= OMAP2_PBIASLITEVMODE0; | |
313 | omap_ctrl_writel(reg, control_pbias_offset); | |
314 | } else { | |
315 | reg = omap_ctrl_readl(control_pbias_offset); | |
316 | reg &= ~OMAP2_PBIASLITEPWRDNZ0; | |
317 | omap_ctrl_writel(reg, control_pbias_offset); | |
318 | ||
319 | ret = twl_mmc_set_voltage(c, 0); | |
320 | ||
321 | /* 100ms delay required for PBIAS configuration */ | |
322 | msleep(100); | |
323 | reg = omap_ctrl_readl(control_pbias_offset); | |
324 | reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | | |
325 | OMAP2_PBIASLITEVMODE0); | |
326 | omap_ctrl_writel(reg, control_pbias_offset); | |
327 | } | |
328 | ||
329 | return ret; | |
330 | } | |
331 | ||
332 | static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd) | |
333 | { | |
334 | int ret; | |
335 | struct twl_mmc_controller *c = &hsmmc[1]; | |
336 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
337 | ||
0329c377 DB |
338 | /* |
339 | * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP | |
340 | * VDDS is used to power the pins, optionally with a transceiver to | |
341 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
342 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
343 | */ | |
90c62bf0 TL |
344 | if (power_on) { |
345 | if (mmc->slots[0].internal_clock) { | |
346 | u32 reg; | |
347 | ||
348 | reg = omap_ctrl_readl(control_devconf1_offset); | |
349 | reg |= OMAP2_MMCSDIO2ADPCLKISEL; | |
350 | omap_ctrl_writel(reg, control_devconf1_offset); | |
351 | } | |
352 | ret = twl_mmc_set_voltage(c, vdd); | |
353 | } else { | |
354 | ret = twl_mmc_set_voltage(c, 0); | |
355 | } | |
356 | ||
357 | return ret; | |
358 | } | |
359 | ||
07d83cc9 GI |
360 | static int twl_mmc3_set_power(struct device *dev, int slot, int power_on, |
361 | int vdd) | |
362 | { | |
363 | /* | |
364 | * Assume MMC3 has self-powered device connected, for example on-board | |
365 | * chip with external power source. | |
366 | */ | |
367 | return 0; | |
368 | } | |
369 | ||
90c62bf0 TL |
370 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; |
371 | ||
372 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |
373 | { | |
374 | struct twl4030_hsmmc_info *c; | |
375 | int nr_hsmmc = ARRAY_SIZE(hsmmc_data); | |
376 | ||
377 | if (cpu_is_omap2430()) { | |
378 | control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; | |
379 | control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; | |
380 | nr_hsmmc = 2; | |
381 | } else { | |
382 | control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; | |
383 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | |
384 | } | |
385 | ||
386 | for (c = controllers; c->mmc; c++) { | |
387 | struct twl_mmc_controller *twl = hsmmc + c->mmc - 1; | |
388 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | |
389 | ||
390 | if (!c->mmc || c->mmc > nr_hsmmc) { | |
391 | pr_debug("MMC%d: no such controller\n", c->mmc); | |
392 | continue; | |
393 | } | |
394 | if (mmc) { | |
395 | pr_debug("MMC%d: already configured\n", c->mmc); | |
396 | continue; | |
397 | } | |
398 | ||
399 | mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); | |
400 | if (!mmc) { | |
401 | pr_err("Cannot allocate memory for mmc device!\n"); | |
402 | return; | |
403 | } | |
404 | ||
e51151a5 AH |
405 | if (c->name) |
406 | strncpy(twl->name, c->name, HSMMC_NAME_LEN); | |
407 | else | |
408 | snprintf(twl->name, ARRAY_SIZE(twl->name), | |
409 | "mmc%islot%i", c->mmc, 1); | |
90c62bf0 TL |
410 | mmc->slots[0].name = twl->name; |
411 | mmc->nr_slots = 1; | |
90c62bf0 TL |
412 | mmc->slots[0].wires = c->wires; |
413 | mmc->slots[0].internal_clock = !c->ext_clock; | |
414 | mmc->dma_mask = 0xffffffff; | |
415 | ||
416 | /* note: twl4030 card detect GPIOs normally switch VMMCx ... */ | |
417 | if (gpio_is_valid(c->gpio_cd)) { | |
418 | mmc->init = twl_mmc_late_init; | |
419 | mmc->cleanup = twl_mmc_cleanup; | |
420 | mmc->suspend = twl_mmc_suspend; | |
421 | mmc->resume = twl_mmc_resume; | |
422 | ||
423 | mmc->slots[0].switch_pin = c->gpio_cd; | |
424 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); | |
8d75e98b AH |
425 | if (c->cover_only) |
426 | mmc->slots[0].get_cover_state = twl_mmc_get_cover_state; | |
427 | else | |
428 | mmc->slots[0].card_detect = twl_mmc_card_detect; | |
90c62bf0 TL |
429 | } else |
430 | mmc->slots[0].switch_pin = -EINVAL; | |
431 | ||
432 | /* write protect normally uses an OMAP gpio */ | |
433 | if (gpio_is_valid(c->gpio_wp)) { | |
434 | gpio_request(c->gpio_wp, "mmc_wp"); | |
435 | gpio_direction_input(c->gpio_wp); | |
436 | ||
437 | mmc->slots[0].gpio_wp = c->gpio_wp; | |
438 | mmc->slots[0].get_ro = twl_mmc_get_ro; | |
439 | } else | |
440 | mmc->slots[0].gpio_wp = -EINVAL; | |
441 | ||
442 | /* NOTE: we assume OMAP's MMC1 and MMC2 use | |
443 | * the TWL4030's VMMC1 and VMMC2, respectively; | |
07d83cc9 | 444 | * and that MMC3 device has it's own power source. |
90c62bf0 TL |
445 | */ |
446 | ||
447 | switch (c->mmc) { | |
448 | case 1: | |
449 | mmc->slots[0].set_power = twl_mmc1_set_power; | |
0329c377 | 450 | mmc->slots[0].ocr_mask = MMC1_OCR; |
90c62bf0 TL |
451 | break; |
452 | case 2: | |
453 | mmc->slots[0].set_power = twl_mmc2_set_power; | |
0329c377 DB |
454 | if (c->transceiver) |
455 | mmc->slots[0].ocr_mask = MMC2_OCR; | |
456 | else | |
457 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | |
90c62bf0 | 458 | break; |
07d83cc9 GI |
459 | case 3: |
460 | mmc->slots[0].set_power = twl_mmc3_set_power; | |
461 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | |
462 | break; | |
90c62bf0 TL |
463 | default: |
464 | pr_err("MMC%d configuration not supported!\n", c->mmc); | |
07d83cc9 | 465 | kfree(mmc); |
90c62bf0 TL |
466 | continue; |
467 | } | |
468 | hsmmc_data[c->mmc - 1] = mmc; | |
469 | } | |
470 | ||
471 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | |
01971f65 DB |
472 | |
473 | /* pass the device nodes back to board setup code */ | |
474 | for (c = controllers; c->mmc; c++) { | |
475 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | |
476 | ||
477 | if (!c->mmc || c->mmc > nr_hsmmc) | |
478 | continue; | |
479 | c->dev = mmc->dev; | |
480 | } | |
90c62bf0 TL |
481 | } |
482 | ||
483 | #endif |