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omap: Fix 3630 mux errors
[deliverable/linux.git] / arch / arm / mach-omap2 / mux.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
2351872c 4 * OMAP2 and OMAP3 pin multiplexing configurations
1dbae815 5 *
9330899e
TL		 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
1dbae815 8 *
9330899e 9 * Written by Tony Lindgren
1dbae815
TL		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
1dbae815
TL		 26#include <linux/module.h>
27#include <linux/init.h>
fced80c7 28#include <linux/io.h>
1dbae815 29#include <linux/spinlock.h>
15ac7afe 30#include <linux/list.h>
4b715efc
TL		 31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/seq_file.h>
34#include <linux/uaccess.h>
1dbae815 35
fced80c7
RK		 36#include <asm/system.h>
37
ce491cf8
TL		 38#include <plat/control.h>
39#include <plat/mux.h>
1dbae815 40
15ac7afe 41#include "mux.h"
1dbae815 42
92c9f501
MR		 43#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
44#define OMAP_MUX_BASE_SZ 0x5ca
45
15ac7afe
TL		 46struct omap_mux_entry {
47 struct omap_mux mux;
48 struct list_head node;
49};
50
4b715efc 51static unsigned long mux_phys;
92c9f501
MR		 52static void __iomem *mux_base;
53
d4bb72e5 54u16 omap_mux_read(u16 reg)
92c9f501
MR		 55{
56 if (cpu_is_omap24xx())
57 return __raw_readb(mux_base + reg);
58 else
59 return __raw_readw(mux_base + reg);
60}
61
d4bb72e5 62void omap_mux_write(u16 val, u16 reg)
92c9f501
MR		 63{
64 if (cpu_is_omap24xx())
65 __raw_writeb(val, mux_base + reg);
66 else
67 __raw_writew(val, mux_base + reg);
68}
7d7f665d 69
d4bb72e5
TL		 70void omap_mux_write_array(struct omap_board_mux *board_mux)
71{
72 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
73 omap_mux_write(board_mux->value, board_mux->reg_offset);
74 board_mux++;
75 }
76}
77
15f45e6f 78#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
15ac7afe
TL		 79
80static struct omap_mux_cfg arch_mux_cfg;
81
1dbae815
TL		 82/* NOTE: See mux.h for the enumeration */
83
9330899e 84static struct pin_config __initdata_or_module omap24xx_pins[] = {
1dbae815
TL		 85/*
86 * description mux mux pull pull debug
87 * offset mode ena type
88 */
89
90/* 24xx I2C */
91MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
92MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
7bbb3cc5 93MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1)
1dbae815
TL		 94MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
95
96/* Menelaus interrupt */
97MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
98
8d7f9f50
TL		 99/* 24xx clocks */
100MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
101
7bbb3cc5 102/* 24xx GPMC chipselects, wait pin monitoring */
7d34f3b3
TL		 103MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1)
104MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1)
3cbc9605
TL		 105MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
106MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
107MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
108MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
109
8d7f9f50
TL		 110/* 24xx McBSP */
111MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
112MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
113MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
114MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
115
1dbae815 116/* 24xx GPIO */
7d34f3b3
TL		 117MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
118MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1)
119MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
120MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
121MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
122MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
123MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
124MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
1dbae815 125MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
7d34f3b3 126MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
f7337a19 127MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
1dbae815 128MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
f7337a19
TL		 129MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
130MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
131MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
132MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
7d34f3b3 133MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
8d7f9f50 134MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
7bbb3cc5 135MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
8d7f9f50 136
5ac42153
TL		 137/* 242x DBG GPIO */
138MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
139MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
140MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
141MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
142MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
143MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
144MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
145MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
146MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
147MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
148
149/* 24xx external DMA requests */
7d34f3b3
TL		 150MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
151MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
152MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
153MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
154MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
155MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
5ac42153 156
7d34f3b3 157/* UART3 */
8d7f9f50
TL		 158MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
159MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
160
abc45e1d
KP		 161/* MMC/SDIO */
162MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
163MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
164MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
165MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
166MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
167MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
168MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
169MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
170MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
171MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
172MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
173MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
174
7bbb3cc5
KP		 175/* Full speed USB */
176MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1)
177MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1)
178MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1)
179MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1)
180MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1)
181MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1)
182MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1)
183
184MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1)
185MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1)
186MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1)
187MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1)
188MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1)
189MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1)
190MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1)
191MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1)
192
193MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1)
194MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1)
195MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1)
196MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1)
197MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1)
198
8d7f9f50
TL		 199/* Keypad GPIO*/
200MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
201MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
202MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1)
203MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1)
204MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1)
205MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1)
206MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1)
207MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1)
208MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1)
209MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1)
210MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1)
211MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1)
212MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1)
213
214/* 24xx Menelaus Keypad GPIO */
215MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
216MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
217MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
1dbae815 218
f7337a19
TL		 219/* 2430 USB */
220MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
221MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
222MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
223MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
224MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
225MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
226MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
227MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
228MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
229MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
230MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
231
232/* 2430 HS-USB */
233MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
234MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
235MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
236MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
237MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
238MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
239MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
240MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
241MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
242MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
243MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
244MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
245
246/* 2430 McBSP */
2619bc32
AK		 247MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
248
249MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
250MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
251MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
252MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
253MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
254MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
255
f7337a19
TL		 256MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
257MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
258MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
259MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
260MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
261MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
262MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
263MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
2619bc32
AK		 264
265MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
266MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
267MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
268MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
269
270MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
271MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
272MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
273MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
274
275MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
276MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
277MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
278MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
279
280/* 2430 MCSPI1 */
281MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
282MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
283MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
284MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
285
286/* Touchscreen GPIO */
287MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
288
1dbae815
TL		 289};
290
9330899e
TL		 291#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
292
9330899e 293#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
15f45e6f 294
2351872c 295static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
9330899e
TL		 296{
297 u16 orig;
298 u8 warn = 0, debug = 0;
299
92c9f501 300 orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
9330899e
TL		 301
302#ifdef CONFIG_OMAP_MUX_DEBUG
303 debug = cfg->debug;
304#endif
305 warn = (orig != reg);
306 if (debug || warn)
307 printk(KERN_WARNING
a58caad1 308 "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
44595982
PW		 309 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
310 orig, reg);
9330899e
TL		 311}
312#else
313#define omap2_cfg_debug(x, y) do {} while (0)
314#endif
315
2619bc32 316static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
1dbae815 317{
9330899e
TL		 318 static DEFINE_SPINLOCK(mux_spin_lock);
319 unsigned long flags;
225dfda1 320 u8 reg = 0;
225dfda1 321
9330899e 322 spin_lock_irqsave(&mux_spin_lock, flags);
225dfda1
TL		 323 reg |= cfg->mask & 0x7;
324 if (cfg->pull_val)
2351872c 325 reg |= OMAP2_PULL_ENA;
9330899e 326 if (cfg->pu_pd_val)
2351872c 327 reg |= OMAP2_PULL_UP;
9330899e 328 omap2_cfg_debug(cfg, reg);
92c9f501 329 omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
9330899e 330 spin_unlock_irqrestore(&mux_spin_lock, flags);
225dfda1 331
1dbae815
TL		 332 return 0;
333}
7d7f665d
TL		 334
335int __init omap2_mux_init(void)
336{
92c9f501
MR		 337 u32 mux_pbase;
338
339 if (cpu_is_omap2420())
340 mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
341 else if (cpu_is_omap2430())
342 mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
15ac7afe
TL		 343 else
344 return -ENODEV;
92c9f501
MR		 345
346 mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
347 if (!mux_base) {
348 printk(KERN_ERR "mux: Could not ioremap\n");
349 return -ENODEV;
350 }
351
7d7f665d
TL		 352 if (cpu_is_omap24xx()) {
353 arch_mux_cfg.pins = omap24xx_pins;
9330899e 354 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
7d7f665d 355 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
15f45e6f
TL		 356
357 return omap_mux_register(&arch_mux_cfg);
7d7f665d 358 }
7d7f665d 359
15f45e6f 360 return 0;
7d7f665d 361}
1dbae815 362
15f45e6f
TL		 363#else
364int __init omap2_mux_init(void)
365{
366 return 0;
367}
15ac7afe
TL		 368#endif /* CONFIG_OMAP_MUX */
369
370/*----------------------------------------------------------------------------*/
371
372#ifdef CONFIG_ARCH_OMAP34XX
15ac7afe
TL		 373static LIST_HEAD(muxmodes);
374static DEFINE_MUTEX(muxmode_mutex);
375
376#ifdef CONFIG_OMAP_MUX
377
378static char *omap_mux_options;
379
380int __init omap_mux_init_gpio(int gpio, int val)
381{
382 struct omap_mux_entry *e;
383 int found = 0;
384
385 if (!gpio)
386 return -EINVAL;
387
388 list_for_each_entry(e, &muxmodes, node) {
389 struct omap_mux *m = &e->mux;
390 if (gpio == m->gpio) {
391 u16 old_mode;
392 u16 mux_mode;
393
394 old_mode = omap_mux_read(m->reg_offset);
395 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
396 mux_mode |= OMAP_MUX_MODE4;
397 printk(KERN_DEBUG "mux: Setting signal "
398 "%s.gpio%i 0x%04x -> 0x%04x\n",
399 m->muxnames[0], gpio, old_mode, mux_mode);
400 omap_mux_write(mux_mode, m->reg_offset);
401 found++;
402 }
403 }
404
405 if (found == 1)
406 return 0;
407
408 if (found > 1) {
409 printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
410 return -EINVAL;
411 }
412
413 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
414
415 return -ENODEV;
416}
417
418int __init omap_mux_init_signal(char *muxname, int val)
419{
420 struct omap_mux_entry *e;
421 char *m0_name = NULL, *mode_name = NULL;
422 int found = 0;
423
424 mode_name = strchr(muxname, '.');
425 if (mode_name) {
426 *mode_name = '\0';
427 mode_name++;
428 m0_name = muxname;
429 } else {
430 mode_name = muxname;
431 }
432
433 list_for_each_entry(e, &muxmodes, node) {
434 struct omap_mux *m = &e->mux;
435 char *m0_entry = m->muxnames[0];
436 int i;
437
438 if (m0_name && strcmp(m0_name, m0_entry))
439 continue;
440
441 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
442 char *mode_cur = m->muxnames[i];
443
444 if (!mode_cur)
445 continue;
446
447 if (!strcmp(mode_name, mode_cur)) {
448 u16 old_mode;
449 u16 mux_mode;
450
451 old_mode = omap_mux_read(m->reg_offset);
452 mux_mode = val | i;
453 printk(KERN_DEBUG "mux: Setting signal "
454 "%s.%s 0x%04x -> 0x%04x\n",
455 m0_entry, muxname, old_mode, mux_mode);
456 omap_mux_write(mux_mode, m->reg_offset);
457 found++;
458 }
459 }
460 }
461
462 if (found == 1)
463 return 0;
464
465 if (found > 1) {
466 printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
467 found, muxname);
468 return -EINVAL;
469 }
470
471 printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
472
473 return -ENODEV;
474}
475
4b715efc
TL		 476#ifdef CONFIG_DEBUG_FS
477
478#define OMAP_MUX_MAX_NR_FLAGS 10
479#define OMAP_MUX_TEST_FLAG(val, mask) \
480 if (((val) & (mask)) == (mask)) { \
481 i++; \
482 flags[i] = #mask; \
483 }
484
485/* REVISIT: Add checking for non-optimal mux settings */
486static inline void omap_mux_decode(struct seq_file *s, u16 val)
487{
488 char *flags[OMAP_MUX_MAX_NR_FLAGS];
489 char mode[14];
490 int i = -1;
491
492 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
493 i++;
494 flags[i] = mode;
495
496 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
497 if (val & OMAP_OFF_EN) {
498 if (!(val & OMAP_OFFOUT_EN)) {
499 if (!(val & OMAP_OFF_PULL_UP)) {
500 OMAP_MUX_TEST_FLAG(val,
501 OMAP_PIN_OFF_INPUT_PULLDOWN);
502 } else {
503 OMAP_MUX_TEST_FLAG(val,
504 OMAP_PIN_OFF_INPUT_PULLUP);
505 }
506 } else {
507 if (!(val & OMAP_OFFOUT_VAL)) {
508 OMAP_MUX_TEST_FLAG(val,
509 OMAP_PIN_OFF_OUTPUT_LOW);
510 } else {
511 OMAP_MUX_TEST_FLAG(val,
512 OMAP_PIN_OFF_OUTPUT_HIGH);
513 }
514 }
515 }
516
517 if (val & OMAP_INPUT_EN) {
518 if (val & OMAP_PULL_ENA) {
519 if (!(val & OMAP_PULL_UP)) {
520 OMAP_MUX_TEST_FLAG(val,
521 OMAP_PIN_INPUT_PULLDOWN);
522 } else {
523 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
524 }
525 } else {
526 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
527 }
528 } else {
529 i++;
530 flags[i] = "OMAP_PIN_OUTPUT";
531 }
532
533 do {
534 seq_printf(s, "%s", flags[i]);
535 if (i > 0)
536 seq_printf(s, " | ");
537 } while (i-- > 0);
538}
539
540#define OMAP_MUX_DEFNAME_LEN 16
541
542static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
543{
544 struct omap_mux_entry *e;
545
546 list_for_each_entry(e, &muxmodes, node) {
547 struct omap_mux *m = &e->mux;
548 char m0_def[OMAP_MUX_DEFNAME_LEN];
549 char *m0_name = m->muxnames[0];
550 u16 val;
551 int i, mode;
552
553 if (!m0_name)
554 continue;
555
556 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
557 if (m0_name[i] == '\0') {
558 m0_def[i] = m0_name[i];
559 break;
560 }
561 m0_def[i] = toupper(m0_name[i]);
562 }
563 val = omap_mux_read(m->reg_offset);
564 mode = val & OMAP_MUX_MODE7;
565
566 seq_printf(s, "OMAP%i_MUX(%s, ",
567 cpu_is_omap34xx() ? 3 : 0, m0_def);
568 omap_mux_decode(s, val);
569 seq_printf(s, "),\n");
570 }
571
572 return 0;
573}
574
575static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
576{
577 return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
578}
579
580static const struct file_operations omap_mux_dbg_board_fops = {
581 .open = omap_mux_dbg_board_open,
582 .read = seq_read,
583 .llseek = seq_lseek,
584 .release = single_release,
585};
586
587static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
588{
589 struct omap_mux *m = s->private;
590 const char *none = "NA";
591 u16 val;
592 int mode;
593
594 val = omap_mux_read(m->reg_offset);
595 mode = val & OMAP_MUX_MODE7;
596
597 seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
598 m->muxnames[0], m->muxnames[mode],
599 mux_phys + m->reg_offset, m->reg_offset, val,
600 m->balls[0] ? m->balls[0] : none,
601 m->balls[1] ? m->balls[1] : none);
602 seq_printf(s, "mode: ");
603 omap_mux_decode(s, val);
604 seq_printf(s, "\n");
605 seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
606 m->muxnames[0] ? m->muxnames[0] : none,
607 m->muxnames[1] ? m->muxnames[1] : none,
608 m->muxnames[2] ? m->muxnames[2] : none,
609 m->muxnames[3] ? m->muxnames[3] : none,
610 m->muxnames[4] ? m->muxnames[4] : none,
611 m->muxnames[5] ? m->muxnames[5] : none,
612 m->muxnames[6] ? m->muxnames[6] : none,
613 m->muxnames[7] ? m->muxnames[7] : none);
614
615 return 0;
616}
617
618#define OMAP_MUX_MAX_ARG_CHAR 7
619
620static ssize_t omap_mux_dbg_signal_write(struct file *file,
621 const char __user *user_buf,
622 size_t count, loff_t *ppos)
623{
624 char buf[OMAP_MUX_MAX_ARG_CHAR];
625 struct seq_file *seqf;
626 struct omap_mux *m;
627 unsigned long val;
628 int buf_size, ret;
629
630 if (count > OMAP_MUX_MAX_ARG_CHAR)
631 return -EINVAL;
632
633 memset(buf, 0, sizeof(buf));
634 buf_size = min(count, sizeof(buf) - 1);
635
636 if (copy_from_user(buf, user_buf, buf_size))
637 return -EFAULT;
638
639 ret = strict_strtoul(buf, 0x10, &val);
640 if (ret < 0)
641 return ret;
642
643 if (val > 0xffff)
644 return -EINVAL;
645
646 seqf = file->private_data;
647 m = seqf->private;
648
649 omap_mux_write((u16)val, m->reg_offset);
650 *ppos += count;
651
652 return count;
653}
654
655static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
656{
657 return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
658}
659
660static const struct file_operations omap_mux_dbg_signal_fops = {
661 .open = omap_mux_dbg_signal_open,
662 .read = seq_read,
663 .write = omap_mux_dbg_signal_write,
664 .llseek = seq_lseek,
665 .release = single_release,
666};
667
668static struct dentry *mux_dbg_dir;
669
670static void __init omap_mux_dbg_init(void)
671{
672 struct omap_mux_entry *e;
673
674 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
675 if (!mux_dbg_dir)
676 return;
677
678 (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
679 NULL, &omap_mux_dbg_board_fops);
680
681 list_for_each_entry(e, &muxmodes, node) {
682 struct omap_mux *m = &e->mux;
683
684 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
685 m, &omap_mux_dbg_signal_fops);
686 }
687}
688
689#else
690static inline void omap_mux_dbg_init(void)
691{
692}
693#endif /* CONFIG_DEBUG_FS */
694
15ac7afe
TL		 695static void __init omap_mux_free_names(struct omap_mux *m)
696{
697 int i;
698
699 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
700 kfree(m->muxnames[i]);
701
702#ifdef CONFIG_DEBUG_FS
703 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
704 kfree(m->balls[i]);
705#endif
706
707}
708
709/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
710static int __init omap_mux_late_init(void)
711{
712 struct omap_mux_entry *e, *tmp;
713
714 list_for_each_entry_safe(e, tmp, &muxmodes, node) {
715 struct omap_mux *m = &e->mux;
716 u16 mode = omap_mux_read(m->reg_offset);
717
718 if (OMAP_MODE_GPIO(mode))
719 continue;
720
721#ifndef CONFIG_DEBUG_FS
722 mutex_lock(&muxmode_mutex);
723 list_del(&e->node);
724 mutex_unlock(&muxmode_mutex);
725 omap_mux_free_names(m);
726 kfree(m);
1dbae815 727#endif
15ac7afe
TL		 728
729 }
730
4b715efc
TL		 731 omap_mux_dbg_init();
732
15ac7afe
TL		 733 return 0;
734}
735late_initcall(omap_mux_late_init);
736
737static void __init omap_mux_package_fixup(struct omap_mux *p,
738 struct omap_mux *superset)
739{
740 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
741 struct omap_mux *s = superset;
742 int found = 0;
743
744 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
745 if (s->reg_offset == p->reg_offset) {
746 *s = *p;
747 found++;
748 break;
749 }
750 s++;
751 }
752 if (!found)
753 printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
754 p->reg_offset);
755 p++;
756 }
757}
758
759#ifdef CONFIG_DEBUG_FS
760
761static void __init omap_mux_package_init_balls(struct omap_ball *b,
762 struct omap_mux *superset)
763{
764 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
765 struct omap_mux *s = superset;
766 int found = 0;
767
768 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
769 if (s->reg_offset == b->reg_offset) {
770 s->balls[0] = b->balls[0];
771 s->balls[1] = b->balls[1];
772 found++;
773 break;
774 }
775 s++;
776 }
777 if (!found)
778 printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
779 b->reg_offset);
780 b++;
781 }
782}
783
784#else /* CONFIG_DEBUG_FS */
785
786static inline void omap_mux_package_init_balls(struct omap_ball *b,
787 struct omap_mux *superset)
788{
789}
790
791#endif /* CONFIG_DEBUG_FS */
792
793static int __init omap_mux_setup(char *options)
794{
795 if (!options)
796 return 0;
797
798 omap_mux_options = options;
799
800 return 1;
801}
802__setup("omap_mux=", omap_mux_setup);
803
804/*
805 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
806 * cmdline options only override the bootloader values.
807 * During development, please enable CONFIG_DEBUG_FS, and use the
808 * signal specific entries under debugfs.
809 */
810static void __init omap_mux_set_cmdline_signals(void)
811{
812 char *options, *next_opt, *token;
813
814 if (!omap_mux_options)
815 return;
816
817 options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
818 if (!options)
819 return;
820
821 strcpy(options, omap_mux_options);
822 next_opt = options;
823
824 while ((token = strsep(&next_opt, ",")) != NULL) {
825 char *keyval, *name;
826 unsigned long val;
827
828 keyval = token;
829 name = strsep(&keyval, "=");
830 if (name) {
831 int res;
832
833 res = strict_strtoul(keyval, 0x10, &val);
834 if (res < 0)
835 continue;
836
837 omap_mux_init_signal(name, (u16)val);
838 }
839 }
840
841 kfree(options);
842}
843
15ac7afe
TL		 844static int __init omap_mux_copy_names(struct omap_mux *src,
845 struct omap_mux *dst)
846{
847 int i;
848
849 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
850 if (src->muxnames[i]) {
851 dst->muxnames[i] =
852 kmalloc(strlen(src->muxnames[i]) + 1,
853 GFP_KERNEL);
854 if (!dst->muxnames[i])
855 goto free;
856 strcpy(dst->muxnames[i], src->muxnames[i]);
857 }
858 }
859
860#ifdef CONFIG_DEBUG_FS
861 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
862 if (src->balls[i]) {
863 dst->balls[i] =
864 kmalloc(strlen(src->balls[i]) + 1,
865 GFP_KERNEL);
866 if (!dst->balls[i])
867 goto free;
868 strcpy(dst->balls[i], src->balls[i]);
869 }
870 }
871#endif
872
873 return 0;
874
875free:
876 omap_mux_free_names(dst);
877 return -ENOMEM;
878
879}
880
881#endif /* CONFIG_OMAP_MUX */
882
883static u16 omap_mux_get_by_gpio(int gpio)
884{
885 struct omap_mux_entry *e;
886 u16 offset = OMAP_MUX_TERMINATOR;
887
888 list_for_each_entry(e, &muxmodes, node) {
889 struct omap_mux *m = &e->mux;
890 if (m->gpio == gpio) {
891 offset = m->reg_offset;
892 break;
893 }
894 }
895
896 return offset;
897}
898
899/* Needed for dynamic muxing of GPIO pins for off-idle */
900u16 omap_mux_get_gpio(int gpio)
901{
902 u16 offset;
903
904 offset = omap_mux_get_by_gpio(gpio);
905 if (offset == OMAP_MUX_TERMINATOR) {
906 printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
907 return offset;
908 }
909
910 return omap_mux_read(offset);
911}
912
913/* Needed for dynamic muxing of GPIO pins for off-idle */
914void omap_mux_set_gpio(u16 val, int gpio)
915{
916 u16 offset;
917
918 offset = omap_mux_get_by_gpio(gpio);
919 if (offset == OMAP_MUX_TERMINATOR) {
920 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
921 return;
922 }
923
924 omap_mux_write(val, offset);
925}
926
927static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
928{
929 struct omap_mux_entry *entry;
930 struct omap_mux *m;
931
932 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
933 if (!entry)
934 return NULL;
935
936 m = &entry->mux;
937 memcpy(m, src, sizeof(struct omap_mux_entry));
938
939#ifdef CONFIG_OMAP_MUX
940 if (omap_mux_copy_names(src, m)) {
941 kfree(entry);
942 return NULL;
943 }
944#endif
945
946 mutex_lock(&muxmode_mutex);
947 list_add_tail(&entry->node, &muxmodes);
948 mutex_unlock(&muxmode_mutex);
949
950 return m;
951}
952
953/*
954 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
955 * the GPIO to mux offset mapping that is needed for dynamic muxing
956 * of GPIO pins for off-idle.
957 */
958static void __init omap_mux_init_list(struct omap_mux *superset)
959{
960 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
961 struct omap_mux *entry;
962
963#ifndef CONFIG_OMAP_MUX
964 /* Skip pins that are not muxed as GPIO by bootloader */
965 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
966 superset++;
967 continue;
968 }
969#endif
970
9ecef433
TL		 971#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)
972 if (!superset->muxnames || !superset->muxnames[0]) {
973 superset++;
974 continue;
975 }
976#endif
977
15ac7afe
TL		 978 entry = omap_mux_list_add(superset);
979 if (!entry) {
980 printk(KERN_ERR "mux: Could not add entry\n");
981 return;
982 }
983 superset++;
984 }
985}
986
987int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
988 struct omap_mux *superset,
989 struct omap_mux *package_subset,
990 struct omap_board_mux *board_mux,
991 struct omap_ball *package_balls)
992{
993 if (mux_base)
994 return -EBUSY;
995
4b715efc 996 mux_phys = mux_pbase;
15ac7afe
TL		 997 mux_base = ioremap(mux_pbase, mux_size);
998 if (!mux_base) {
999 printk(KERN_ERR "mux: Could not ioremap\n");
1000 return -ENODEV;
1001 }
1002
1003#ifdef CONFIG_OMAP_MUX
d04eb600
TL		 1004 if (package_subset)
1005 omap_mux_package_fixup(package_subset, superset);
1006 if (package_balls)
1007 omap_mux_package_init_balls(package_balls, superset);
15ac7afe
TL		 1008#endif
1009
1010 omap_mux_init_list(superset);
1011
2cb0c54f
TL		 1012#ifdef CONFIG_OMAP_MUX
1013 omap_mux_set_cmdline_signals();
d4bb72e5 1014 omap_mux_write_array(board_mux);
2cb0c54f
TL		 1015#endif
1016
15ac7afe
TL		 1017 return 0;
1018}
1019
1020#endif /* CONFIG_ARCH_OMAP34XX */
15f45e6f 1021
Linux kernel - Deliverables
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