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omap: mux: Add new style init functions to omap3 board-*.c files
[deliverable/linux.git] / arch / arm / mach-omap2 / mux.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
2351872c 4 * OMAP2 and OMAP3 pin multiplexing configurations
1dbae815 5 *
9330899e
TL		 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
1dbae815 8 *
9330899e 9 * Written by Tony Lindgren
1dbae815
TL		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
1dbae815
TL		 26#include <linux/module.h>
27#include <linux/init.h>
fced80c7 28#include <linux/io.h>
1dbae815 29#include <linux/spinlock.h>
15ac7afe 30#include <linux/list.h>
1dbae815 31
fced80c7
RK		 32#include <asm/system.h>
33
ce491cf8
TL		 34#include <plat/control.h>
35#include <plat/mux.h>
1dbae815 36
15ac7afe 37#include "mux.h"
1dbae815 38
92c9f501
MR		 39#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
40#define OMAP_MUX_BASE_SZ 0x5ca
41
15ac7afe
TL		 42struct omap_mux_entry {
43 struct omap_mux mux;
44 struct list_head node;
45};
46
92c9f501
MR		 47static void __iomem *mux_base;
48
49static inline u16 omap_mux_read(u16 reg)
50{
51 if (cpu_is_omap24xx())
52 return __raw_readb(mux_base + reg);
53 else
54 return __raw_readw(mux_base + reg);
55}
56
57static inline void omap_mux_write(u16 val, u16 reg)
58{
59 if (cpu_is_omap24xx())
60 __raw_writeb(val, mux_base + reg);
61 else
62 __raw_writew(val, mux_base + reg);
63}
7d7f665d 64
15ac7afe
TL		 65#ifdef CONFIG_OMAP_MUX
66
67static struct omap_mux_cfg arch_mux_cfg;
68
1dbae815
TL		 69/* NOTE: See mux.h for the enumeration */
70
9330899e
TL		 71#ifdef CONFIG_ARCH_OMAP24XX
72static struct pin_config __initdata_or_module omap24xx_pins[] = {
1dbae815
TL		 73/*
74 * description mux mux pull pull debug
75 * offset mode ena type
76 */
77
78/* 24xx I2C */
79MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
80MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
7bbb3cc5 81MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1)
1dbae815
TL		 82MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
83
84/* Menelaus interrupt */
85MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
86
8d7f9f50
TL		 87/* 24xx clocks */
88MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
89
7bbb3cc5 90/* 24xx GPMC chipselects, wait pin monitoring */
7d34f3b3
TL		 91MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1)
92MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1)
3cbc9605
TL		 93MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
94MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
95MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
96MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
97
8d7f9f50
TL		 98/* 24xx McBSP */
99MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
100MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
101MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
102MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
103
1dbae815 104/* 24xx GPIO */
7d34f3b3
TL		 105MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
106MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1)
107MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
108MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
109MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
110MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
111MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
112MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
1dbae815 113MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
7d34f3b3 114MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
f7337a19 115MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
1dbae815 116MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
f7337a19
TL		 117MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
118MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
119MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
120MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
7d34f3b3 121MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
8d7f9f50 122MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
7bbb3cc5 123MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
8d7f9f50 124
5ac42153
TL		 125/* 242x DBG GPIO */
126MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
127MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
128MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
129MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
130MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
131MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
132MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
133MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
134MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
135MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
136
137/* 24xx external DMA requests */
7d34f3b3
TL		 138MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
139MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
140MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
141MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
142MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
143MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
5ac42153 144
7d34f3b3 145/* UART3 */
8d7f9f50
TL		 146MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
147MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
148
abc45e1d
KP		 149/* MMC/SDIO */
150MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
151MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
152MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
153MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
154MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
155MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
156MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
157MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
158MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
159MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
160MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
161MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
162
7bbb3cc5
KP		 163/* Full speed USB */
164MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1)
165MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1)
166MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1)
167MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1)
168MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1)
169MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1)
170MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1)
171
172MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1)
173MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1)
174MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1)
175MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1)
176MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1)
177MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1)
178MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1)
179MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1)
180
181MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1)
182MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1)
183MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1)
184MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1)
185MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1)
186
8d7f9f50
TL		 187/* Keypad GPIO*/
188MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
189MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
190MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1)
191MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1)
192MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1)
193MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1)
194MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1)
195MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1)
196MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1)
197MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1)
198MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1)
199MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1)
200MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1)
201
202/* 24xx Menelaus Keypad GPIO */
203MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
204MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
205MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
1dbae815 206
f7337a19
TL		 207/* 2430 USB */
208MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
209MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
210MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
211MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
212MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
213MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
214MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
215MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
216MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
217MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
218MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
219
220/* 2430 HS-USB */
221MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
222MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
223MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
224MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
225MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
226MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
227MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
228MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
229MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
230MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
231MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
232MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
233
234/* 2430 McBSP */
2619bc32
AK		 235MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
236
237MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
238MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
239MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
240MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
241MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
242MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
243
f7337a19
TL		 244MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
245MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
246MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
247MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
248MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
249MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
250MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
251MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
2619bc32
AK		 252
253MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
254MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
255MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
256MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
257
258MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
259MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
260MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
261MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
262
263MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
264MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
265MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
266MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
267
268/* 2430 MCSPI1 */
269MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
270MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
271MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
272MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
273
274/* Touchscreen GPIO */
275MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
276
1dbae815
TL		 277};
278
9330899e
TL		 279#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
280
281#else
282#define omap24xx_pins NULL
283#define OMAP24XX_PINS_SZ 0
284#endif /* CONFIG_ARCH_OMAP24XX */
225dfda1 285
2351872c
VP		 286#ifdef CONFIG_ARCH_OMAP34XX
287static struct pin_config __initdata_or_module omap34xx_pins[] = {
288/*
289 * Name, reg-offset,
290 * mux-mode | [active-mode | off-mode]
291 */
292
293/* 34xx I2C */
294MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
295 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
296MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
297 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
298MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
299 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
300MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
301 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
302MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
303 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
304MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
305 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
306MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
307 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
308MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
309 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
310
311/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
312MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
313 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
314MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
315 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
316MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
317 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
318MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
319 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
320MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
321 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
322MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
323 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
324MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
325 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
326MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
327 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
328MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
329 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
330MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
331 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
332MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
333 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
334MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
335 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
336
337/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
338MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
339 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
340MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
341 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
342MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
343 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
344MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
345 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
346MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
347 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
348MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
349 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
350MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
351 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
352MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
353 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
354MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
355 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
356MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
357 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
358MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
359 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
360MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
361 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
362
363/* TLL - HSUSB: 12-pin TLL Port 1*/
364MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
2351872c 365 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
cc26b3b0
SMK		 366MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
367 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
2351872c 368MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
cc26b3b0 369 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c 370MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
cc26b3b0 371 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c
VP		 372MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
373 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
374MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
375 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
376MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
377 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
378MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
379 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
380MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
381 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
382MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
383 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
384MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
385 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
386MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
387 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
388
389/* TLL - HSUSB: 12-pin TLL Port 2*/
390MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
2351872c 391 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
cc26b3b0
SMK		 392MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
393 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
2351872c 394MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
cc26b3b0 395 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c 396MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
cc26b3b0 397 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c
VP		 398MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
399 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
400MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
401 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
402MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
403 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
404MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
405 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
406MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
407 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
408MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
409 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
410MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
411 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
412MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
413 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
414
415/* TLL - HSUSB: 12-pin TLL Port 3*/
416MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
2351872c 417 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
cc26b3b0
SMK		 418MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
419 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
2351872c 420MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
cc26b3b0 421 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c 422MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
cc26b3b0 423 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
2351872c
VP		 424MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
425 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
426MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
427 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
428MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
429 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
430MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
431 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
432MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
433 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
434MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
435 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
436MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
437 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
438MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
439 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
cc26b3b0
SMK		 440
441/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
442MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
443 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
444MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
445 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
446MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
447 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
448MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
449 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
450MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
451 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
452MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
453 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
454
455/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
456MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
457 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
458MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
459 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
460MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
461 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
462MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
463 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
464MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
465 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
466MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
467 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
468
469/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
470MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
471 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
472MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
473 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
474MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
475 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
476MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
477 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
478MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
479 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
480MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
481 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
482
2619bc32
AK		 483
484/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
b9d766c7 485 * (Always specify PIN_INPUT, except for names suffixed by "_OUT".)
2619bc32
AK		 486 * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
487 */
b9d766c7
TL		 488MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
489 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
490MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
491 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
44e74840
JN		 492MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee,
493 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
2619bc32
AK		 494MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
495 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
b9d766c7
TL		 496MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4,
497 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
498MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4,
499 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN)
500MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce,
501 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
502MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc,
503 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
504MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160,
505 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
41a03c53
AKG		 506MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162,
507 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
b9d766c7
TL		 508MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164,
509 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
510MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
511 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
512MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
513 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
514MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
515 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
516MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
517 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
518MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
519 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
2619bc32
AK		 520MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
521 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
9fb97412
JP		 522
523/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
524MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
525 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
526MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
527 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
57b9daa0
VP		 528
529/* MMC1 */
530MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
531 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
532MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
533 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
534MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
535 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
536MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
537 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
538MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
539 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
540MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
541 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
542MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
543 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
544MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
545 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
546MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
547 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
548MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
549 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
550
551/* MMC2 */
552MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
553 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
554MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
555 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
556MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
557 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
558MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
559 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
560MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
561 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
562MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
563 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
4679232d
M		 564MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164,
565 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
566MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166,
567 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
568MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168,
569 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
570MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A,
571 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
57b9daa0
VP		 572
573/* MMC3 */
574MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
575 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
576MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
577 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
578MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
579 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
580MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
581 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
582MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
583 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
584MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
585 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
5110b298
RT		 586
587/* SYS_NIRQ T2 INT1 */
588MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
589 OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
590 OMAP34XX_MUX_MODE0)
e8e51d29
AKG		 591/* EHCI GPIO's on OMAP3EVM (Rev >= E) */
592MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea,
593 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
594MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec,
595 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
596MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8,
597 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
2351872c
VP		 598};
599
600#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
601
602#else
603#define omap34xx_pins NULL
604#define OMAP34XX_PINS_SZ 0
605#endif /* CONFIG_ARCH_OMAP34XX */
225dfda1 606
9330899e 607#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
2351872c 608static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
9330899e
TL		 609{
610 u16 orig;
611 u8 warn = 0, debug = 0;
612
92c9f501 613 orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
9330899e
TL		 614
615#ifdef CONFIG_OMAP_MUX_DEBUG
616 debug = cfg->debug;
617#endif
618 warn = (orig != reg);
619 if (debug || warn)
620 printk(KERN_WARNING
a58caad1 621 "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
44595982
PW		 622 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
623 orig, reg);
9330899e
TL		 624}
625#else
626#define omap2_cfg_debug(x, y) do {} while (0)
627#endif
628
629#ifdef CONFIG_ARCH_OMAP24XX
2619bc32 630static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
1dbae815 631{
9330899e
TL		 632 static DEFINE_SPINLOCK(mux_spin_lock);
633 unsigned long flags;
225dfda1 634 u8 reg = 0;
225dfda1 635
9330899e 636 spin_lock_irqsave(&mux_spin_lock, flags);
225dfda1
TL		 637 reg |= cfg->mask & 0x7;
638 if (cfg->pull_val)
2351872c 639 reg |= OMAP2_PULL_ENA;
9330899e 640 if (cfg->pu_pd_val)
2351872c 641 reg |= OMAP2_PULL_UP;
9330899e 642 omap2_cfg_debug(cfg, reg);
92c9f501 643 omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
9330899e 644 spin_unlock_irqrestore(&mux_spin_lock, flags);
225dfda1 645
1dbae815
TL		 646 return 0;
647}
9330899e 648#else
2351872c
VP		 649#define omap24xx_cfg_reg NULL
650#endif
651
652#ifdef CONFIG_ARCH_OMAP34XX
653static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
654{
655 static DEFINE_SPINLOCK(mux_spin_lock);
656 unsigned long flags;
657 u16 reg = 0;
658
659 spin_lock_irqsave(&mux_spin_lock, flags);
660 reg |= cfg->mux_val;
661 omap2_cfg_debug(cfg, reg);
92c9f501 662 omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
2351872c
VP		 663 spin_unlock_irqrestore(&mux_spin_lock, flags);
664
665 return 0;
666}
667#else
668#define omap34xx_cfg_reg NULL
7d7f665d
TL		 669#endif
670
671int __init omap2_mux_init(void)
672{
92c9f501
MR		 673 u32 mux_pbase;
674
675 if (cpu_is_omap2420())
676 mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
677 else if (cpu_is_omap2430())
678 mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
15ac7afe
TL		 679 else
680 return -ENODEV;
92c9f501
MR		 681
682 mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
683 if (!mux_base) {
684 printk(KERN_ERR "mux: Could not ioremap\n");
685 return -ENODEV;
686 }
687
7d7f665d
TL		 688 if (cpu_is_omap24xx()) {
689 arch_mux_cfg.pins = omap24xx_pins;
9330899e 690 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
7d7f665d 691 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
2351872c
VP		 692 } else if (cpu_is_omap34xx()) {
693 arch_mux_cfg.pins = omap34xx_pins;
694 arch_mux_cfg.size = OMAP34XX_PINS_SZ;
695 arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
7d7f665d 696 }
7d7f665d
TL		 697
698 return omap_mux_register(&arch_mux_cfg);
699}
1dbae815 700
15ac7afe
TL		 701#endif /* CONFIG_OMAP_MUX */
702
703/*----------------------------------------------------------------------------*/
704
705#ifdef CONFIG_ARCH_OMAP34XX
706
707static LIST_HEAD(muxmodes);
708static DEFINE_MUTEX(muxmode_mutex);
709
710#ifdef CONFIG_OMAP_MUX
711
712static char *omap_mux_options;
713
714int __init omap_mux_init_gpio(int gpio, int val)
715{
716 struct omap_mux_entry *e;
717 int found = 0;
718
719 if (!gpio)
720 return -EINVAL;
721
722 list_for_each_entry(e, &muxmodes, node) {
723 struct omap_mux *m = &e->mux;
724 if (gpio == m->gpio) {
725 u16 old_mode;
726 u16 mux_mode;
727
728 old_mode = omap_mux_read(m->reg_offset);
729 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
730 mux_mode |= OMAP_MUX_MODE4;
731 printk(KERN_DEBUG "mux: Setting signal "
732 "%s.gpio%i 0x%04x -> 0x%04x\n",
733 m->muxnames[0], gpio, old_mode, mux_mode);
734 omap_mux_write(mux_mode, m->reg_offset);
735 found++;
736 }
737 }
738
739 if (found == 1)
740 return 0;
741
742 if (found > 1) {
743 printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
744 return -EINVAL;
745 }
746
747 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
748
749 return -ENODEV;
750}
751
752int __init omap_mux_init_signal(char *muxname, int val)
753{
754 struct omap_mux_entry *e;
755 char *m0_name = NULL, *mode_name = NULL;
756 int found = 0;
757
758 mode_name = strchr(muxname, '.');
759 if (mode_name) {
760 *mode_name = '\0';
761 mode_name++;
762 m0_name = muxname;
763 } else {
764 mode_name = muxname;
765 }
766
767 list_for_each_entry(e, &muxmodes, node) {
768 struct omap_mux *m = &e->mux;
769 char *m0_entry = m->muxnames[0];
770 int i;
771
772 if (m0_name && strcmp(m0_name, m0_entry))
773 continue;
774
775 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
776 char *mode_cur = m->muxnames[i];
777
778 if (!mode_cur)
779 continue;
780
781 if (!strcmp(mode_name, mode_cur)) {
782 u16 old_mode;
783 u16 mux_mode;
784
785 old_mode = omap_mux_read(m->reg_offset);
786 mux_mode = val | i;
787 printk(KERN_DEBUG "mux: Setting signal "
788 "%s.%s 0x%04x -> 0x%04x\n",
789 m0_entry, muxname, old_mode, mux_mode);
790 omap_mux_write(mux_mode, m->reg_offset);
791 found++;
792 }
793 }
794 }
795
796 if (found == 1)
797 return 0;
798
799 if (found > 1) {
800 printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
801 found, muxname);
802 return -EINVAL;
803 }
804
805 printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
806
807 return -ENODEV;
808}
809
810static void __init omap_mux_free_names(struct omap_mux *m)
811{
812 int i;
813
814 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
815 kfree(m->muxnames[i]);
816
817#ifdef CONFIG_DEBUG_FS
818 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
819 kfree(m->balls[i]);
820#endif
821
822}
823
824/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
825static int __init omap_mux_late_init(void)
826{
827 struct omap_mux_entry *e, *tmp;
828
829 list_for_each_entry_safe(e, tmp, &muxmodes, node) {
830 struct omap_mux *m = &e->mux;
831 u16 mode = omap_mux_read(m->reg_offset);
832
833 if (OMAP_MODE_GPIO(mode))
834 continue;
835
836#ifndef CONFIG_DEBUG_FS
837 mutex_lock(&muxmode_mutex);
838 list_del(&e->node);
839 mutex_unlock(&muxmode_mutex);
840 omap_mux_free_names(m);
841 kfree(m);
1dbae815 842#endif
15ac7afe
TL		 843
844 }
845
846 return 0;
847}
848late_initcall(omap_mux_late_init);
849
850static void __init omap_mux_package_fixup(struct omap_mux *p,
851 struct omap_mux *superset)
852{
853 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
854 struct omap_mux *s = superset;
855 int found = 0;
856
857 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
858 if (s->reg_offset == p->reg_offset) {
859 *s = *p;
860 found++;
861 break;
862 }
863 s++;
864 }
865 if (!found)
866 printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
867 p->reg_offset);
868 p++;
869 }
870}
871
872#ifdef CONFIG_DEBUG_FS
873
874static void __init omap_mux_package_init_balls(struct omap_ball *b,
875 struct omap_mux *superset)
876{
877 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
878 struct omap_mux *s = superset;
879 int found = 0;
880
881 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
882 if (s->reg_offset == b->reg_offset) {
883 s->balls[0] = b->balls[0];
884 s->balls[1] = b->balls[1];
885 found++;
886 break;
887 }
888 s++;
889 }
890 if (!found)
891 printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
892 b->reg_offset);
893 b++;
894 }
895}
896
897#else /* CONFIG_DEBUG_FS */
898
899static inline void omap_mux_package_init_balls(struct omap_ball *b,
900 struct omap_mux *superset)
901{
902}
903
904#endif /* CONFIG_DEBUG_FS */
905
906static int __init omap_mux_setup(char *options)
907{
908 if (!options)
909 return 0;
910
911 omap_mux_options = options;
912
913 return 1;
914}
915__setup("omap_mux=", omap_mux_setup);
916
917/*
918 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
919 * cmdline options only override the bootloader values.
920 * During development, please enable CONFIG_DEBUG_FS, and use the
921 * signal specific entries under debugfs.
922 */
923static void __init omap_mux_set_cmdline_signals(void)
924{
925 char *options, *next_opt, *token;
926
927 if (!omap_mux_options)
928 return;
929
930 options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
931 if (!options)
932 return;
933
934 strcpy(options, omap_mux_options);
935 next_opt = options;
936
937 while ((token = strsep(&next_opt, ",")) != NULL) {
938 char *keyval, *name;
939 unsigned long val;
940
941 keyval = token;
942 name = strsep(&keyval, "=");
943 if (name) {
944 int res;
945
946 res = strict_strtoul(keyval, 0x10, &val);
947 if (res < 0)
948 continue;
949
950 omap_mux_init_signal(name, (u16)val);
951 }
952 }
953
954 kfree(options);
955}
956
957static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
958{
959 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
960 omap_mux_write(board_mux->value, board_mux->reg_offset);
961 board_mux++;
962 }
963}
964
965static int __init omap_mux_copy_names(struct omap_mux *src,
966 struct omap_mux *dst)
967{
968 int i;
969
970 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
971 if (src->muxnames[i]) {
972 dst->muxnames[i] =
973 kmalloc(strlen(src->muxnames[i]) + 1,
974 GFP_KERNEL);
975 if (!dst->muxnames[i])
976 goto free;
977 strcpy(dst->muxnames[i], src->muxnames[i]);
978 }
979 }
980
981#ifdef CONFIG_DEBUG_FS
982 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
983 if (src->balls[i]) {
984 dst->balls[i] =
985 kmalloc(strlen(src->balls[i]) + 1,
986 GFP_KERNEL);
987 if (!dst->balls[i])
988 goto free;
989 strcpy(dst->balls[i], src->balls[i]);
990 }
991 }
992#endif
993
994 return 0;
995
996free:
997 omap_mux_free_names(dst);
998 return -ENOMEM;
999
1000}
1001
1002#endif /* CONFIG_OMAP_MUX */
1003
1004static u16 omap_mux_get_by_gpio(int gpio)
1005{
1006 struct omap_mux_entry *e;
1007 u16 offset = OMAP_MUX_TERMINATOR;
1008
1009 list_for_each_entry(e, &muxmodes, node) {
1010 struct omap_mux *m = &e->mux;
1011 if (m->gpio == gpio) {
1012 offset = m->reg_offset;
1013 break;
1014 }
1015 }
1016
1017 return offset;
1018}
1019
1020/* Needed for dynamic muxing of GPIO pins for off-idle */
1021u16 omap_mux_get_gpio(int gpio)
1022{
1023 u16 offset;
1024
1025 offset = omap_mux_get_by_gpio(gpio);
1026 if (offset == OMAP_MUX_TERMINATOR) {
1027 printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
1028 return offset;
1029 }
1030
1031 return omap_mux_read(offset);
1032}
1033
1034/* Needed for dynamic muxing of GPIO pins for off-idle */
1035void omap_mux_set_gpio(u16 val, int gpio)
1036{
1037 u16 offset;
1038
1039 offset = omap_mux_get_by_gpio(gpio);
1040 if (offset == OMAP_MUX_TERMINATOR) {
1041 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
1042 return;
1043 }
1044
1045 omap_mux_write(val, offset);
1046}
1047
1048static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
1049{
1050 struct omap_mux_entry *entry;
1051 struct omap_mux *m;
1052
1053 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
1054 if (!entry)
1055 return NULL;
1056
1057 m = &entry->mux;
1058 memcpy(m, src, sizeof(struct omap_mux_entry));
1059
1060#ifdef CONFIG_OMAP_MUX
1061 if (omap_mux_copy_names(src, m)) {
1062 kfree(entry);
1063 return NULL;
1064 }
1065#endif
1066
1067 mutex_lock(&muxmode_mutex);
1068 list_add_tail(&entry->node, &muxmodes);
1069 mutex_unlock(&muxmode_mutex);
1070
1071 return m;
1072}
1073
1074/*
1075 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
1076 * the GPIO to mux offset mapping that is needed for dynamic muxing
1077 * of GPIO pins for off-idle.
1078 */
1079static void __init omap_mux_init_list(struct omap_mux *superset)
1080{
1081 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
1082 struct omap_mux *entry;
1083
1084#ifndef CONFIG_OMAP_MUX
1085 /* Skip pins that are not muxed as GPIO by bootloader */
1086 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
1087 superset++;
1088 continue;
1089 }
1090#endif
1091
1092 entry = omap_mux_list_add(superset);
1093 if (!entry) {
1094 printk(KERN_ERR "mux: Could not add entry\n");
1095 return;
1096 }
1097 superset++;
1098 }
1099}
1100
1101int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
1102 struct omap_mux *superset,
1103 struct omap_mux *package_subset,
1104 struct omap_board_mux *board_mux,
1105 struct omap_ball *package_balls)
1106{
1107 if (mux_base)
1108 return -EBUSY;
1109
1110 mux_base = ioremap(mux_pbase, mux_size);
1111 if (!mux_base) {
1112 printk(KERN_ERR "mux: Could not ioremap\n");
1113 return -ENODEV;
1114 }
1115
1116#ifdef CONFIG_OMAP_MUX
1117 omap_mux_package_fixup(package_subset, superset);
1118 omap_mux_package_init_balls(package_balls, superset);
1119 omap_mux_set_cmdline_signals();
1120 omap_mux_set_board_signals(board_mux);
1121#endif
1122
1123 omap_mux_init_list(superset);
1124
1125 return 0;
1126}
1127
1128#endif /* CONFIG_ARCH_OMAP34XX */
Linux kernel - Deliverables
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