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ddaa912a TL |
1 | /* |
2 | * Copyright (C) 2009 Nokia | |
3 | * Copyright (C) 2009 Texas Instruments | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU | |
11 | ||
12 | #define OMAP3_MUX(mode0, mux_value) \ | |
13 | { \ | |
14 | .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \ | |
15 | .value = (mux_value), \ | |
16 | } | |
17 | ||
18 | /* | |
19 | * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing | |
20 | * | |
21 | * Extracted from the TRM. Add 0x48002030 to these values to get the | |
22 | * absolute addresses. The name in the macro is the mode-0 name of | |
23 | * the pin. NOTE: These registers are 16-bits wide. | |
24 | * | |
25 | * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead | |
26 | * of CHASSIS for some registers. For the defines, we follow the | |
27 | * 36XX naming, and use SDMMC and CHASSIS. | |
28 | */ | |
29 | #define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000 | |
30 | #define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002 | |
31 | #define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004 | |
32 | #define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006 | |
33 | #define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008 | |
34 | #define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a | |
35 | #define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c | |
36 | #define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e | |
37 | #define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010 | |
38 | #define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012 | |
39 | #define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014 | |
40 | #define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016 | |
41 | #define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018 | |
42 | #define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a | |
43 | #define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c | |
44 | #define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e | |
45 | #define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020 | |
46 | #define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022 | |
47 | #define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024 | |
48 | #define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026 | |
49 | #define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028 | |
50 | #define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a | |
51 | #define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c | |
52 | #define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e | |
53 | #define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030 | |
54 | #define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032 | |
55 | #define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034 | |
56 | #define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036 | |
57 | #define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 | |
58 | #define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a | |
59 | #define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c | |
60 | #define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e | |
61 | #define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040 | |
62 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042 | |
63 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044 | |
64 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046 | |
65 | #define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048 | |
66 | #define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a | |
67 | #define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c | |
68 | #define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e | |
69 | #define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050 | |
70 | #define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052 | |
71 | #define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054 | |
72 | #define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056 | |
73 | #define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058 | |
74 | #define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a | |
75 | #define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c | |
76 | #define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e | |
77 | #define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060 | |
78 | #define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062 | |
79 | #define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064 | |
80 | #define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066 | |
81 | #define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068 | |
82 | #define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a | |
83 | #define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c | |
84 | #define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e | |
85 | #define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070 | |
86 | #define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072 | |
87 | #define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074 | |
88 | #define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076 | |
89 | #define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078 | |
90 | #define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a | |
91 | #define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c | |
92 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e | |
93 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080 | |
94 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082 | |
95 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084 | |
96 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086 | |
97 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088 | |
98 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a | |
99 | #define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c | |
100 | #define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e | |
101 | #define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090 | |
102 | #define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092 | |
103 | #define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094 | |
104 | #define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096 | |
105 | #define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098 | |
106 | #define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a | |
107 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c | |
108 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e | |
109 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0 | |
110 | #define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2 | |
111 | #define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4 | |
112 | #define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6 | |
113 | #define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8 | |
114 | #define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa | |
115 | #define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac | |
116 | #define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae | |
117 | #define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0 | |
118 | #define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2 | |
119 | #define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4 | |
120 | #define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6 | |
121 | #define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8 | |
122 | #define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba | |
123 | #define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc | |
124 | #define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be | |
125 | #define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0 | |
126 | #define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2 | |
127 | #define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4 | |
128 | #define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6 | |
129 | #define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8 | |
130 | #define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca | |
131 | #define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc | |
132 | #define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce | |
133 | #define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0 | |
134 | #define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2 | |
135 | #define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4 | |
136 | #define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6 | |
137 | #define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8 | |
138 | #define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da | |
139 | #define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc | |
140 | #define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de | |
141 | #define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0 | |
142 | #define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2 | |
143 | #define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4 | |
144 | #define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6 | |
145 | #define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8 | |
146 | #define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea | |
147 | #define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec | |
148 | #define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee | |
149 | #define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0 | |
150 | #define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2 | |
151 | #define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4 | |
152 | #define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6 | |
153 | #define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8 | |
154 | #define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa | |
155 | #define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc | |
156 | #define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe | |
157 | #define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100 | |
158 | #define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102 | |
159 | #define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104 | |
160 | #define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106 | |
161 | #define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108 | |
162 | #define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a | |
163 | #define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c | |
164 | #define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e | |
165 | #define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110 | |
166 | #define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112 | |
167 | #define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114 | |
168 | #define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116 | |
169 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118 | |
170 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a | |
171 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c | |
172 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e | |
662c8b55 TL |
173 | |
174 | /* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */ | |
ddaa912a TL |
175 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120 |
176 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122 | |
177 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124 | |
178 | #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126 | |
662c8b55 | 179 | |
ddaa912a TL |
180 | #define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128 |
181 | #define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a | |
182 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c | |
183 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e | |
184 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130 | |
185 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132 | |
186 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134 | |
187 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136 | |
188 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138 | |
189 | #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a | |
190 | #define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c | |
191 | #define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e | |
192 | #define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140 | |
193 | #define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142 | |
194 | #define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144 | |
195 | #define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146 | |
196 | #define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148 | |
197 | #define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a | |
198 | #define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c | |
199 | #define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e | |
200 | #define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150 | |
201 | #define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152 | |
202 | #define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154 | |
203 | #define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156 | |
204 | #define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158 | |
205 | #define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a | |
206 | #define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c | |
207 | #define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e | |
208 | #define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160 | |
209 | #define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162 | |
210 | #define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164 | |
211 | #define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166 | |
212 | #define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168 | |
213 | #define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a | |
214 | #define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c | |
215 | #define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e | |
216 | #define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170 | |
217 | #define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172 | |
218 | #define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174 | |
219 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176 | |
220 | #define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178 | |
221 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a | |
222 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c | |
223 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e | |
224 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180 | |
225 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182 | |
226 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184 | |
227 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186 | |
228 | #define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188 | |
229 | #define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a | |
230 | #define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c | |
231 | #define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e | |
232 | #define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190 | |
233 | #define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192 | |
234 | #define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194 | |
235 | #define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196 | |
236 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198 | |
237 | #define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a | |
238 | #define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c | |
239 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e | |
240 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0 | |
241 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2 | |
242 | #define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4 | |
243 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6 | |
244 | #define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8 | |
245 | #define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa | |
246 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac | |
247 | #define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae | |
248 | #define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0 | |
249 | #define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2 | |
250 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4 | |
251 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6 | |
252 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8 | |
253 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba | |
254 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc | |
255 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be | |
256 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0 | |
257 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2 | |
258 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4 | |
259 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6 | |
260 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8 | |
261 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca | |
262 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc | |
263 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce | |
264 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0 | |
265 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2 | |
266 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4 | |
267 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6 | |
268 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8 | |
269 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da | |
270 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc | |
271 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de | |
272 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0 | |
273 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2 | |
274 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4 | |
275 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6 | |
276 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8 | |
277 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea | |
278 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec | |
279 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee | |
280 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0 | |
281 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2 | |
282 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4 | |
283 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6 | |
284 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8 | |
285 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa | |
286 | #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc | |
662c8b55 | 287 | |
ddaa912a TL |
288 | /* Note that 34xx TRM has SAD2D instead of CHASSIS for these */ |
289 | #define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe | |
290 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200 | |
291 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202 | |
292 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204 | |
293 | #define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206 | |
294 | #define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208 | |
295 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a | |
296 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c | |
297 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e | |
298 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210 | |
299 | #define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212 | |
300 | #define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214 | |
301 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216 | |
302 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218 | |
303 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a | |
304 | #define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c | |
305 | #define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e | |
306 | #define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220 | |
307 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222 | |
308 | #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224 | |
662c8b55 | 309 | |
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310 | #define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226 |
311 | #define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228 | |
312 | #define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a | |
313 | #define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c | |
314 | #define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e | |
315 | #define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230 | |
316 | #define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232 | |
317 | #define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234 | |
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318 | |
319 | /* 36xx only */ | |
320 | #define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236 | |
321 | #define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570 | |
322 | #define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572 | |
323 | #define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574 | |
324 | #define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576 | |
325 | #define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578 | |
326 | #define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a | |
327 | #define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c | |
328 | #define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e | |
329 | #define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580 | |
330 | #define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582 | |
331 | #define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584 | |
332 | #define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586 | |
333 | #define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588 | |
334 | #define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a | |
335 | #define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c | |
336 | #define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e | |
337 | #define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590 | |
338 | #define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592 | |
339 | #define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594 | |
340 | #define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596 | |
341 | #define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598 | |
342 | #define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a | |
343 | #define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c | |
344 | #define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e | |
345 | #define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0 | |
346 | #define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2 | |
347 | #define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4 | |
348 | ||
349 | /* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */ | |
350 | #define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120 | |
351 | #define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122 | |
352 | #define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124 | |
353 | #define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126 | |
354 | ||
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355 | #define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8 |
356 | #define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa | |
357 | #define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac | |
358 | #define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae | |
359 | #define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0 | |
360 | #define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2 | |
361 | #define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4 | |
362 | #define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6 | |
363 | #define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8 | |
364 | #define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba | |
365 | #define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc | |
366 | #define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be | |
367 | #define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0 | |
368 | #define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2 | |
369 | #define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4 | |
370 | #define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6 | |
371 | #define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8 | |
372 | #define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca | |
373 | #define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0 | |
374 | #define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2 | |
375 | #define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4 | |
376 | #define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6 | |
377 | #define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8 | |
378 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da | |
379 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc | |
380 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de | |
381 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0 | |
382 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2 | |
383 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4 | |
384 | #define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6 | |
385 | #define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8 | |
386 | #define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea | |
387 | #define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec | |
388 | #define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee | |
389 | #define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0 | |
390 | #define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2 | |
391 | #define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4 | |
392 | #define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6 | |
393 | #define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c | |
394 | #define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e | |
395 | #define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20 | |
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396 | #define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24 |
397 | #define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26 | |
398 | #define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28 | |
399 | #define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a | |
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400 | |
401 | #define OMAP3_CONTROL_PADCONF_MUX_SIZE \ | |
27b105bb | 402 | (OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2) |