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367cd31e SS |
1 | /* |
2 | * Secondary CPU startup routine source file. | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * Interface functions needed for the SMP. This file is based on arm | |
10 | * realview smp platform. | |
11 | * Copyright (c) 2003 ARM Limited. | |
12 | * | |
13 | * This program is free software,you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/linkage.h> | |
19 | #include <linux/init.h> | |
20 | ||
21 | /* Physical address needed since MMU not enabled yet on secondary core */ | |
22 | #define OMAP4_AUX_CORE_BOOT1_PA 0x48281804 | |
23 | ||
24 | __INIT | |
25 | ||
26 | /* | |
27 | * OMAP4 specific entry point for secondary CPU to jump from ROM | |
28 | * code. This routine also provides a holding flag into which | |
29 | * secondary core is held until we're ready for it to initialise. | |
30 | * The primary core will update the this flag using a hardware | |
31 | * register AuxCoreBoot1. | |
32 | */ | |
33 | ENTRY(omap_secondary_startup) | |
34 | mrc p15, 0, r0, c0, c0, 5 | |
35 | and r0, r0, #0x0f | |
36 | hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1 | |
37 | ldr r2, [r1] | |
38 | cmp r2, r0 | |
39 | bne hold | |
40 | ||
41 | /* | |
42 | * we've been released from the cpu_release,secondary_stack | |
43 | * should now contain the SVC stack for this core | |
44 | */ | |
45 | b secondary_startup | |
46 |