projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 367cd31e SS |
1 | /* |
| 2 | * Secondary CPU startup routine source file. | |
| 3 | * | |
| da0159fd | 4 | * Copyright (C) 2009-2014 Texas Instruments, Inc. |
| 367cd31e SS |
5 | * |
| 6 | * Author: | |
| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| 8 | * | |
| 9 | * Interface functions needed for the SMP. This file is based on arm | |
| 10 | * realview smp platform. | |
| 11 | * Copyright (c) 2003 ARM Limited. | |
| 12 | * | |
| 13 | * This program is free software,you can redistribute it and/or modify | |
| 14 | * it under the terms of the GNU General Public License version 2 as | |
| 15 | * published by the Free Software Foundation. | |
| 16 | */ | |
| 17 | ||
| 18 | #include <linux/linkage.h> | |
| 19 | #include <linux/init.h> | |
| 20 | ||
| ff999b8a SS |
21 | #include "omap44xx.h" |
| 22 | ||
| 283f708c SS |
23 | /* Physical address needed since MMU not enabled yet on secondary core */ |
| 24 | #define AUX_CORE_BOOT0_PA 0x48281800 | |
| 999f934d | 25 | #define API_HYP_ENTRY 0x102 |
| 283f708c | 26 | |
| 44e7475d TL |
27 | ENTRY(omap_secondary_startup) |
| 28 | #ifdef CONFIG_SMP | |
| 29 | b secondary_startup | |
| 30 | #else | |
| 31 | /* Should never get here */ | |
| 32 | again: wfi | |
| 33 | b again | |
| 34 | #endif | |
| 35 | #ENDPROC(omap_secondary_startup) | |
| 36 | ||
| 283f708c SS |
37 | /* |
| 38 | * OMAP5 specific entry point for secondary CPU to jump from ROM | |
| 39 | * code. This routine also provides a holding flag into which | |
| 40 | * secondary core is held until we're ready for it to initialise. | |
| 41 | * The primary core will update this flag using a hardware | |
| da0159fd | 42 | * register AuxCoreBoot0. |
| 283f708c SS |
43 | */ |
| 44 | ENTRY(omap5_secondary_startup) | |
| 45 | wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 | |
| 46 | ldr r0, [r2] | |
| 47 | mov r0, r0, lsr #5 | |
| 48 | mrc p15, 0, r4, c0, c0, 5 | |
| 49 | and r4, r4, #0x0f | |
| 50 | cmp r0, r4 | |
| 51 | bne wait | |
| 44e7475d | 52 | b omap_secondary_startup |
| 55fde31c | 53 | ENDPROC(omap5_secondary_startup) |
| 999f934d LS |
54 | /* |
| 55 | * Same as omap5_secondary_startup except we call into the ROM to | |
| 56 | * enable HYP mode first. This is called instead of | |
| 57 | * omap5_secondary_startup if the primary CPU was put into HYP mode by | |
| 58 | * the boot loader. | |
| 59 | */ | |
| 60 | ENTRY(omap5_secondary_hyp_startup) | |
| 61 | wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 | |
| 62 | ldr r0, [r2] | |
| 63 | mov r0, r0, lsr #5 | |
| 64 | mrc p15, 0, r4, c0, c0, 5 | |
| 65 | and r4, r4, #0x0f | |
| 66 | cmp r0, r4 | |
| 67 | bne wait_2 | |
| 68 | ldr r12, =API_HYP_ENTRY | |
| 69 | adr r0, hyp_boot | |
| 70 | smc #0 | |
| 71 | hyp_boot: | |
| 44e7475d | 72 | b omap_secondary_startup |
| 999f934d | 73 | ENDPROC(omap5_secondary_hyp_startup) |
| 367cd31e SS |
74 | /* |
| 75 | * OMAP4 specific entry point for secondary CPU to jump from ROM | |
| 76 | * code. This routine also provides a holding flag into which | |
| 77 | * secondary core is held until we're ready for it to initialise. | |
| 942e2c9e SS |
78 | * The primary core will update this flag using a hardware |
| 79 | * register AuxCoreBoot0. | |
| 367cd31e | 80 | */ |
| baf4b7d3 | 81 | ENTRY(omap4_secondary_startup) |
| 942e2c9e SS |
82 | hold: ldr r12,=0x103 |
| 83 | dsb | |
| df571c4a | 84 | smc #0 @ read from AuxCoreBoot0 |
| 942e2c9e SS |
85 | mov r0, r0, lsr #9 |
| 86 | mrc p15, 0, r4, c0, c0, 5 | |
| 87 | and r4, r4, #0x0f | |
| 88 | cmp r0, r4 | |
| 367cd31e SS |
89 | bne hold |
| 90 | ||
| 91 | /* | |
| 942e2c9e | 92 | * we've been released from the wait loop,secondary_stack |
| 367cd31e SS |
93 | * should now contain the SVC stack for this core |
| 94 | */ | |
| 44e7475d | 95 | b omap_secondary_startup |
| baf4b7d3 | 96 | ENDPROC(omap4_secondary_startup) |
| 367cd31e | 97 | |
| baf4b7d3 | 98 | ENTRY(omap4460_secondary_startup) |
| ff999b8a SS |
99 | hold_2: ldr r12,=0x103 |
| 100 | dsb | |
| 101 | smc #0 @ read from AuxCoreBoot0 | |
| 102 | mov r0, r0, lsr #9 | |
| 103 | mrc p15, 0, r4, c0, c0, 5 | |
| 104 | and r4, r4, #0x0f | |
| 105 | cmp r0, r4 | |
| 106 | bne hold_2 | |
| 107 | ||
| 108 | /* | |
| 109 | * GIC distributor control register has changed between | |
| 110 | * CortexA9 r1pX and r2pX. The Control Register secure | |
| 111 | * banked version is now composed of 2 bits: | |
| 112 | * bit 0 == Secure Enable | |
| 113 | * bit 1 == Non-Secure Enable | |
| 114 | * The Non-Secure banked register has not changed | |
| 115 | * Because the ROM Code is based on the r1pX GIC, the CPU1 | |
| 116 | * GIC restoration will cause a problem to CPU0 Non-Secure SW. | |
| 117 | * The workaround must be: | |
| 118 | * 1) Before doing the CPU1 wakeup, CPU0 must disable | |
| 119 | * the GIC distributor | |
| 120 | * 2) CPU1 must re-enable the GIC distributor on | |
| 121 | * it's wakeup path. | |
| 122 | */ | |
| 123 | ldr r1, =OMAP44XX_GIC_DIST_BASE | |
| 124 | ldr r0, [r1] | |
| 125 | orr r0, #1 | |
| 126 | str r0, [r1] | |
| 127 | ||
| 128 | /* | |
| 129 | * we've been released from the wait loop,secondary_stack | |
| 130 | * should now contain the SVC stack for this core | |
| 131 | */ | |
| 44e7475d | 132 | b omap_secondary_startup |
| baf4b7d3 | 133 | ENDPROC(omap4460_secondary_startup) |