Commit | Line | Data |
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b2b9762f SS |
1 | /* |
2 | * OMAP MPUSS low power code | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
6 | * | |
7 | * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU | |
8 | * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, | |
9 | * CPU0 and CPU1 LPRM modules. | |
10 | * CPU0, CPU1 and MPUSS each have there own power domain and | |
11 | * hence multiple low power combinations of MPUSS are possible. | |
12 | * | |
13 | * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) | |
14 | * because the mode is not supported by hw constraints of dormant | |
15 | * mode. While waking up from the dormant mode, a reset signal | |
16 | * to the Cortex-A9 processor must be asserted by the external | |
17 | * power controller. | |
18 | * | |
19 | * With architectural inputs and hardware recommendations, only | |
20 | * below modes are supported from power gain vs latency point of view. | |
21 | * | |
22 | * CPU0 CPU1 MPUSS | |
23 | * ---------------------------------------------- | |
24 | * ON ON ON | |
25 | * ON(Inactive) OFF ON(Inactive) | |
26 | * OFF OFF CSWR | |
3ba2a739 SS |
27 | * OFF OFF OSWR |
28 | * OFF OFF OFF(Device OFF *TBD) | |
b2b9762f SS |
29 | * ---------------------------------------------- |
30 | * | |
31 | * Note: CPU0 is the master core and it is the last CPU to go down | |
32 | * and first to wake-up when MPUSS low power states are excercised | |
33 | * | |
34 | * | |
35 | * This program is free software; you can redistribute it and/or modify | |
36 | * it under the terms of the GNU General Public License version 2 as | |
37 | * published by the Free Software Foundation. | |
38 | */ | |
39 | ||
40 | #include <linux/kernel.h> | |
41 | #include <linux/io.h> | |
42 | #include <linux/errno.h> | |
43 | #include <linux/linkage.h> | |
44 | #include <linux/smp.h> | |
45 | ||
46 | #include <asm/cacheflush.h> | |
47 | #include <asm/tlbflush.h> | |
48 | #include <asm/smp_scu.h> | |
b2b9762f SS |
49 | #include <asm/pgalloc.h> |
50 | #include <asm/suspend.h> | |
5e94c6e3 | 51 | #include <asm/hardware/cache-l2x0.h> |
b2b9762f | 52 | |
e4c060db | 53 | #include "soc.h" |
b2b9762f | 54 | #include "common.h" |
c49f34bc | 55 | #include "omap44xx.h" |
b2b9762f SS |
56 | #include "omap4-sar-layout.h" |
57 | #include "pm.h" | |
3ba2a739 SS |
58 | #include "prcm_mpu44xx.h" |
59 | #include "prminst44xx.h" | |
60 | #include "prcm44xx.h" | |
61 | #include "prm44xx.h" | |
62 | #include "prm-regbits-44xx.h" | |
b2b9762f SS |
63 | |
64 | #ifdef CONFIG_SMP | |
65 | ||
66 | struct omap4_cpu_pm_info { | |
67 | struct powerdomain *pwrdm; | |
68 | void __iomem *scu_sar_addr; | |
69 | void __iomem *wkup_sar_addr; | |
5e94c6e3 | 70 | void __iomem *l2x0_sar_addr; |
ff999b8a | 71 | void (*secondary_startup)(void); |
b2b9762f SS |
72 | }; |
73 | ||
9f192cf7 SS |
74 | /** |
75 | * struct cpu_pm_ops - CPU pm operations | |
76 | * @finish_suspend: CPU suspend finisher function pointer | |
77 | * @resume: CPU resume function pointer | |
78 | * @scu_prepare: CPU Snoop Control program function pointer | |
79 | * | |
80 | * Structure holds functions pointer for CPU low power operations like | |
81 | * suspend, resume and scu programming. | |
82 | */ | |
83 | struct cpu_pm_ops { | |
84 | int (*finish_suspend)(unsigned long cpu_state); | |
85 | void (*resume)(void); | |
86 | void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); | |
87 | }; | |
88 | ||
b2b9762f | 89 | static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); |
e44f9a77 | 90 | static struct powerdomain *mpuss_pd; |
5e94c6e3 | 91 | static void __iomem *sar_base; |
b2b9762f | 92 | |
9f192cf7 SS |
93 | static int default_finish_suspend(unsigned long cpu_state) |
94 | { | |
95 | omap_do_wfi(); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static void dummy_cpu_resume(void) | |
100 | {} | |
101 | ||
102 | static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) | |
103 | {} | |
104 | ||
105 | struct cpu_pm_ops omap_pm_ops = { | |
106 | .finish_suspend = default_finish_suspend, | |
107 | .resume = dummy_cpu_resume, | |
108 | .scu_prepare = dummy_scu_prepare, | |
109 | }; | |
110 | ||
b2b9762f SS |
111 | /* |
112 | * Program the wakeup routine address for the CPU0 and CPU1 | |
113 | * used for OFF or DORMANT wakeup. | |
114 | */ | |
115 | static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) | |
116 | { | |
117 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | |
118 | ||
edfaf05c | 119 | writel_relaxed(addr, pm_info->wkup_sar_addr); |
b2b9762f SS |
120 | } |
121 | ||
b2b9762f SS |
122 | /* |
123 | * Store the SCU power status value to scratchpad memory | |
124 | */ | |
125 | static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) | |
126 | { | |
127 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | |
128 | u32 scu_pwr_st; | |
129 | ||
130 | switch (cpu_state) { | |
131 | case PWRDM_POWER_RET: | |
132 | scu_pwr_st = SCU_PM_DORMANT; | |
133 | break; | |
134 | case PWRDM_POWER_OFF: | |
135 | scu_pwr_st = SCU_PM_POWEROFF; | |
136 | break; | |
137 | case PWRDM_POWER_ON: | |
138 | case PWRDM_POWER_INACTIVE: | |
139 | default: | |
140 | scu_pwr_st = SCU_PM_NORMAL; | |
141 | break; | |
142 | } | |
143 | ||
edfaf05c | 144 | writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); |
b2b9762f SS |
145 | } |
146 | ||
3ba2a739 SS |
147 | /* Helper functions for MPUSS OSWR */ |
148 | static inline void mpuss_clear_prev_logic_pwrst(void) | |
149 | { | |
150 | u32 reg; | |
151 | ||
152 | reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, | |
153 | OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); | |
154 | omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, | |
155 | OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); | |
156 | } | |
157 | ||
158 | static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) | |
159 | { | |
160 | u32 reg; | |
161 | ||
162 | if (cpu_id) { | |
163 | reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, | |
164 | OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); | |
165 | omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, | |
166 | OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); | |
167 | } else { | |
168 | reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, | |
169 | OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); | |
170 | omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, | |
171 | OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); | |
172 | } | |
173 | } | |
174 | ||
5e94c6e3 SS |
175 | /* |
176 | * Store the CPU cluster state for L2X0 low power operations. | |
177 | */ | |
178 | static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) | |
179 | { | |
180 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); | |
181 | ||
edfaf05c | 182 | writel_relaxed(save_state, pm_info->l2x0_sar_addr); |
5e94c6e3 SS |
183 | } |
184 | ||
185 | /* | |
186 | * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to | |
187 | * in every restore MPUSS OFF path. | |
188 | */ | |
189 | #ifdef CONFIG_CACHE_L2X0 | |
7a09b28e | 190 | static void __init save_l2x0_context(void) |
5e94c6e3 | 191 | { |
eb3d3ec5 | 192 | writel_relaxed(l2x0_saved_regs.aux_ctrl, |
7a09b28e | 193 | sar_base + L2X0_AUXCTRL_OFFSET); |
eb3d3ec5 | 194 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, |
7a09b28e | 195 | sar_base + L2X0_PREFETCH_CTRL_OFFSET); |
5e94c6e3 SS |
196 | } |
197 | #else | |
7a09b28e | 198 | static void __init save_l2x0_context(void) |
5e94c6e3 SS |
199 | {} |
200 | #endif | |
201 | ||
b2b9762f SS |
202 | /** |
203 | * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function | |
204 | * The purpose of this function is to manage low power programming | |
205 | * of OMAP4 MPUSS subsystem | |
206 | * @cpu : CPU ID | |
207 | * @power_state: Low power state. | |
e44f9a77 SS |
208 | * |
209 | * MPUSS states for the context save: | |
210 | * save_state = | |
211 | * 0 - Nothing lost and no need to save: MPUSS INACTIVE | |
212 | * 1 - CPUx L1 and logic lost: MPUSS CSWR | |
213 | * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR | |
214 | * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF | |
b2b9762f SS |
215 | */ |
216 | int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) | |
217 | { | |
32d174ed | 218 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); |
b2b9762f SS |
219 | unsigned int save_state = 0; |
220 | unsigned int wakeup_cpu; | |
221 | ||
222 | if (omap_rev() == OMAP4430_REV_ES1_0) | |
223 | return -ENXIO; | |
224 | ||
225 | switch (power_state) { | |
226 | case PWRDM_POWER_ON: | |
227 | case PWRDM_POWER_INACTIVE: | |
228 | save_state = 0; | |
229 | break; | |
230 | case PWRDM_POWER_OFF: | |
231 | save_state = 1; | |
232 | break; | |
233 | case PWRDM_POWER_RET: | |
234 | default: | |
235 | /* | |
236 | * CPUx CSWR is invalid hardware state. Also CPUx OSWR | |
237 | * doesn't make much scense, since logic is lost and $L1 | |
238 | * needs to be cleaned because of coherency. This makes | |
239 | * CPUx OSWR equivalent to CPUX OFF and hence not supported | |
240 | */ | |
241 | WARN_ON(1); | |
242 | return -ENXIO; | |
243 | } | |
244 | ||
e0555489 | 245 | pwrdm_pre_transition(NULL); |
49404dd0 | 246 | |
3ba2a739 SS |
247 | /* |
248 | * Check MPUSS next state and save interrupt controller if needed. | |
249 | * In MPUSS OSWR or device OFF, interrupt controller contest is lost. | |
250 | */ | |
251 | mpuss_clear_prev_logic_pwrst(); | |
3ba2a739 SS |
252 | if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && |
253 | (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) | |
254 | save_state = 2; | |
255 | ||
3ba2a739 | 256 | cpu_clear_prev_logic_pwrst(cpu); |
32d174ed | 257 | pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); |
9f192cf7 SS |
258 | set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume)); |
259 | omap_pm_ops.scu_prepare(cpu, power_state); | |
5e94c6e3 | 260 | l2x0_pwrst_prepare(cpu, save_state); |
b2b9762f SS |
261 | |
262 | /* | |
263 | * Call low level function with targeted low power state. | |
264 | */ | |
72433eba | 265 | if (save_state) |
9f192cf7 | 266 | cpu_suspend(save_state, omap_pm_ops.finish_suspend); |
72433eba | 267 | else |
9f192cf7 | 268 | omap_pm_ops.finish_suspend(save_state); |
b2b9762f | 269 | |
74ed7bdc SG |
270 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu) |
271 | gic_dist_enable(); | |
272 | ||
b2b9762f SS |
273 | /* |
274 | * Restore the CPUx power state to ON otherwise CPUx | |
275 | * power domain can transitions to programmed low power | |
276 | * state while doing WFI outside the low powe code. On | |
277 | * secure devices, CPUx does WFI which can result in | |
278 | * domain transition | |
279 | */ | |
280 | wakeup_cpu = smp_processor_id(); | |
32d174ed | 281 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); |
b2b9762f | 282 | |
e0555489 | 283 | pwrdm_post_transition(NULL); |
49404dd0 | 284 | |
b2b9762f SS |
285 | return 0; |
286 | } | |
287 | ||
b5b4f288 SS |
288 | /** |
289 | * omap4_hotplug_cpu: OMAP4 CPU hotplug entry | |
290 | * @cpu : CPU ID | |
291 | * @power_state: CPU low power state. | |
292 | */ | |
8bd26e3a | 293 | int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
b5b4f288 | 294 | { |
ff999b8a | 295 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); |
32d174ed | 296 | unsigned int cpu_state = 0; |
b5b4f288 SS |
297 | |
298 | if (omap_rev() == OMAP4430_REV_ES1_0) | |
299 | return -ENXIO; | |
300 | ||
301 | if (power_state == PWRDM_POWER_OFF) | |
302 | cpu_state = 1; | |
303 | ||
32d174ed PW |
304 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); |
305 | pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); | |
ff999b8a | 306 | set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); |
9f192cf7 | 307 | omap_pm_ops.scu_prepare(cpu, power_state); |
b5b4f288 SS |
308 | |
309 | /* | |
260db902 | 310 | * CPU never retuns back if targeted power state is OFF mode. |
b5b4f288 | 311 | * CPU ONLINE follows normal CPU ONLINE ptah via |
baf4b7d3 | 312 | * omap4_secondary_startup(). |
b5b4f288 | 313 | */ |
9f192cf7 | 314 | omap_pm_ops.finish_suspend(cpu_state); |
b5b4f288 | 315 | |
32d174ed | 316 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); |
b5b4f288 SS |
317 | return 0; |
318 | } | |
319 | ||
320 | ||
b2b9762f SS |
321 | /* |
322 | * Initialise OMAP4 MPUSS | |
323 | */ | |
324 | int __init omap4_mpuss_init(void) | |
325 | { | |
326 | struct omap4_cpu_pm_info *pm_info; | |
b2b9762f SS |
327 | |
328 | if (omap_rev() == OMAP4430_REV_ES1_0) { | |
329 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | |
330 | return -ENODEV; | |
331 | } | |
332 | ||
5e94c6e3 SS |
333 | sar_base = omap4_get_sar_ram_base(); |
334 | ||
b2b9762f SS |
335 | /* Initilaise per CPU PM information */ |
336 | pm_info = &per_cpu(omap4_pm_info, 0x0); | |
337 | pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; | |
338 | pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; | |
5e94c6e3 | 339 | pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; |
b2b9762f SS |
340 | pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); |
341 | if (!pm_info->pwrdm) { | |
342 | pr_err("Lookup failed for CPU0 pwrdm\n"); | |
343 | return -ENODEV; | |
344 | } | |
345 | ||
346 | /* Clear CPU previous power domain state */ | |
347 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); | |
3ba2a739 | 348 | cpu_clear_prev_logic_pwrst(0); |
b2b9762f SS |
349 | |
350 | /* Initialise CPU0 power domain state to ON */ | |
351 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); | |
352 | ||
353 | pm_info = &per_cpu(omap4_pm_info, 0x1); | |
354 | pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; | |
355 | pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; | |
5e94c6e3 | 356 | pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; |
ff999b8a | 357 | if (cpu_is_omap446x()) |
baf4b7d3 | 358 | pm_info->secondary_startup = omap4460_secondary_startup; |
ff999b8a | 359 | else |
baf4b7d3 | 360 | pm_info->secondary_startup = omap4_secondary_startup; |
ff999b8a | 361 | |
b2b9762f SS |
362 | pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); |
363 | if (!pm_info->pwrdm) { | |
364 | pr_err("Lookup failed for CPU1 pwrdm\n"); | |
365 | return -ENODEV; | |
366 | } | |
367 | ||
368 | /* Clear CPU previous power domain state */ | |
369 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); | |
3ba2a739 | 370 | cpu_clear_prev_logic_pwrst(1); |
b2b9762f SS |
371 | |
372 | /* Initialise CPU1 power domain state to ON */ | |
373 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); | |
374 | ||
e44f9a77 SS |
375 | mpuss_pd = pwrdm_lookup("mpu_pwrdm"); |
376 | if (!mpuss_pd) { | |
377 | pr_err("Failed to lookup MPUSS power domain\n"); | |
378 | return -ENODEV; | |
379 | } | |
380 | pwrdm_clear_all_prev_pwrst(mpuss_pd); | |
3ba2a739 | 381 | mpuss_clear_prev_logic_pwrst(); |
e44f9a77 | 382 | |
b2b9762f SS |
383 | /* Save device type on scratchpad for low level code to use */ |
384 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) | |
edfaf05c | 385 | writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET); |
b2b9762f | 386 | else |
edfaf05c | 387 | writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET); |
b2b9762f | 388 | |
5e94c6e3 SS |
389 | save_l2x0_context(); |
390 | ||
9f192cf7 SS |
391 | if (cpu_is_omap44xx()) { |
392 | omap_pm_ops.finish_suspend = omap4_finish_suspend; | |
393 | omap_pm_ops.resume = omap4_cpu_resume; | |
394 | omap_pm_ops.scu_prepare = scu_pwrst_prepare; | |
395 | } | |
396 | ||
b2b9762f SS |
397 | return 0; |
398 | } | |
399 | ||
400 | #endif |