[deliverable/linux.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR
 *	OFF		OFF		OFF(Device OFF *TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include <plat/omap44xx.h>

#include "common.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"

#ifdef CONFIG_SMP

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
	void __iomem *l2x0_sar_addr;
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static void __iomem *sar_base;

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	__raw_writel(addr, pm_info->wkup_sar_addr);
}

/*
 * Set the CPUx powerdomain's previous power state
 */
static inline void set_cpu_next_pwrst(unsigned int cpu_id,
				unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
}

/*
 * Read CPU's previous power state
 */
static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
}

/*
 * Clear the CPUx powerdomain's previous power state
 */
static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
}

/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}

static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
{
	u32 reg;

	if (cpu_id) {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
					OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	} else {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
					OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	}
}

/**
 * omap4_mpuss_read_prev_context_state:
 * Function returns the MPUSS previous context state
 */
u32 omap4_mpuss_read_prev_context_state(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
	return reg;
}

/*
 * Store the CPU cluster state for L2X0 low power operations.
 */
static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	__raw_writel(save_state, pm_info->l2x0_sar_addr);
}

/*
 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 * in every restore MPUSS OFF path.
 */
#ifdef CONFIG_CACHE_L2X0
static void save_l2x0_context(void)
{
	u32 val;
	void __iomem *l2x0_base = omap4_get_l2cache_base();

	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
	val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
	__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
}
#else
static void save_l2x0_context(void)
{}
#endif

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	unsigned int save_state = 0;
	unsigned int wakeup_cpu;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_pre_transition(NULL);

	/*
	 * Check MPUSS next state and save interrupt controller if needed.
	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
	 */
	mpuss_clear_prev_logic_pwrst();
	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
		save_state = 2;

	cpu_clear_prev_logic_pwrst(cpu);
	set_cpu_next_pwrst(cpu, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
	scu_pwrst_prepare(cpu, power_state);
	l2x0_pwrst_prepare(cpu, save_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	cpu_suspend(save_state, omap4_finish_suspend);

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	wakeup_cpu = smp_processor_id();
	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);

	pwrdm_post_transition(NULL);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	clear_cpu_prev_pwrst(cpu);
	set_cpu_next_pwrst(cpu, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
	scu_pwrst_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap_secondary_startup().
	 */
	omap4_finish_suspend(cpu_state);

	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
	return 0;
}


/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	sar_base = omap4_get_sar_ram_base();

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(0);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(1);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	mpuss_clear_prev_logic_pwrst();

	/* Save device type on scratchpad for low level code to use */
	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
		__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	else
		__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);

	save_l2x0_context();

	return 0;
}

#endif
Commit	Line	Data
b2b9762f SS	1	/*
	2	* OMAP MPUSS low power code
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	*
	7	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	8	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	9	* CPU0 and CPU1 LPRM modules.
	10	* CPU0, CPU1 and MPUSS each have there own power domain and
	11	* hence multiple low power combinations of MPUSS are possible.
	12	*
	13	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	14	* because the mode is not supported by hw constraints of dormant
	15	* mode. While waking up from the dormant mode, a reset signal
	16	* to the Cortex-A9 processor must be asserted by the external
	17	* power controller.
	18	*
	19	* With architectural inputs and hardware recommendations, only
	20	* below modes are supported from power gain vs latency point of view.
	21	*
	22	* CPU0 CPU1 MPUSS
	23	* ----------------------------------------------
	24	* ON ON ON
	25	* ON(Inactive) OFF ON(Inactive)
	26	* OFF OFF CSWR
3ba2a739 SS	27	* OFF OFF OSWR
3ba2a739 SS	28	* OFF OFF OFF(Device OFF *TBD)
b2b9762f SS	29	* ----------------------------------------------
	30	*
	31	* Note: CPU0 is the master core and it is the last CPU to go down
	32	* and first to wake-up when MPUSS low power states are excercised
	33	*
	34	*
	35	* This program is free software; you can redistribute it and/or modify
	36	* it under the terms of the GNU General Public License version 2 as
	37	* published by the Free Software Foundation.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/io.h>
	42	#include <linux/errno.h>
	43	#include <linux/linkage.h>
	44	#include <linux/smp.h>
	45
	46	#include <asm/cacheflush.h>
	47	#include <asm/tlbflush.h>
	48	#include <asm/smp_scu.h>
b2b9762f SS	49	#include <asm/pgalloc.h>
b2b9762f SS	50	#include <asm/suspend.h>
5e94c6e3	51	#include <asm/hardware/cache-l2x0.h>
b2b9762f SS	52
	53	#include <plat/omap44xx.h>
	54
	55	#include "common.h"
	56	#include "omap4-sar-layout.h"
	57	#include "pm.h"
3ba2a739 SS	58	#include "prcm_mpu44xx.h"
	59	#include "prminst44xx.h"
	60	#include "prcm44xx.h"
	61	#include "prm44xx.h"
	62	#include "prm-regbits-44xx.h"
b2b9762f SS	63
	64	#ifdef CONFIG_SMP
	65
	66	struct omap4_cpu_pm_info {
	67	struct powerdomain *pwrdm;
	68	void __iomem *scu_sar_addr;
	69	void __iomem *wkup_sar_addr;
5e94c6e3	70	void __iomem *l2x0_sar_addr;
b2b9762f SS	71	};
	72
	73	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	74	static struct powerdomain *mpuss_pd;
5e94c6e3	75	static void __iomem *sar_base;
b2b9762f SS	76
	77	/*
	78	* Program the wakeup routine address for the CPU0 and CPU1
	79	* used for OFF or DORMANT wakeup.
	80	*/
	81	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	82	{
	83	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	84
	85	__raw_writel(addr, pm_info->wkup_sar_addr);
	86	}
	87
	88	/*
	89	* Set the CPUx powerdomain's previous power state
	90	*/
	91	static inline void set_cpu_next_pwrst(unsigned int cpu_id,
	92	unsigned int power_state)
	93	{
	94	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	95
	96	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	97	}
	98
	99	/*
	100	* Read CPU's previous power state
	101	*/
	102	static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
	103	{
	104	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	105
	106	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
	107	}
	108
	109	/*
	110	* Clear the CPUx powerdomain's previous power state
	111	*/
	112	static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
	113	{
	114	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	115
	116	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	117	}
	118
	119	/*
	120	* Store the SCU power status value to scratchpad memory
	121	*/
	122	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	123	{
	124	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	125	u32 scu_pwr_st;
	126
	127	switch (cpu_state) {
	128	case PWRDM_POWER_RET:
	129	scu_pwr_st = SCU_PM_DORMANT;
	130	break;
	131	case PWRDM_POWER_OFF:
	132	scu_pwr_st = SCU_PM_POWEROFF;
	133	break;
	134	case PWRDM_POWER_ON:
	135	case PWRDM_POWER_INACTIVE:
	136	default:
	137	scu_pwr_st = SCU_PM_NORMAL;
	138	break;
	139	}
140
141	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
142	}
143
3ba2a739 SS	144	/* Helper functions for MPUSS OSWR */
	145	static inline void mpuss_clear_prev_logic_pwrst(void)
	146	{
	147	u32 reg;
	148
	149	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	150	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	151	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
	152	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	153	}
	154
	155	static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
	156	{
	157	u32 reg;
	158
	159	if (cpu_id) {
	160	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
	161	OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	162	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
	163	OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
	164	} else {
	165	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
	166	OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	167	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
	168	OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
	169	}
	170	}
	171
	172	/**
	173	* omap4_mpuss_read_prev_context_state:
	174	* Function returns the MPUSS previous context state
	175	*/
	176	u32 omap4_mpuss_read_prev_context_state(void)
	177	{
	178	u32 reg;
	179
	180	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	181	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	182	reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
	183	return reg;
	184	}
	185
5e94c6e3 SS	186	/*
	187	* Store the CPU cluster state for L2X0 low power operations.
	188	*/
	189	static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
	190	{
	191	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	192
	193	__raw_writel(save_state, pm_info->l2x0_sar_addr);
	194	}
	195
	196	/*
	197	* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
	198	* in every restore MPUSS OFF path.
	199	*/
	200	#ifdef CONFIG_CACHE_L2X0
	201	static void save_l2x0_context(void)
	202	{
	203	u32 val;
	204	void __iomem *l2x0_base = omap4_get_l2cache_base();
	205
	206	val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
	207	__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
	208	val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
	209	__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	210	}
	211	#else
	212	static void save_l2x0_context(void)
	213	{}
	214	#endif
	215
b2b9762f SS	216	/**
	217	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
	218	* The purpose of this function is to manage low power programming
	219	* of OMAP4 MPUSS subsystem
	220	* @cpu : CPU ID
	221	* @power_state: Low power state.
e44f9a77 SS	222	*
	223	* MPUSS states for the context save:
	224	* save_state =
	225	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	226	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	227	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	228	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	229	*/
	230	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	231	{
	232	unsigned int save_state = 0;
	233	unsigned int wakeup_cpu;
	234
	235	if (omap_rev() == OMAP4430_REV_ES1_0)
	236	return -ENXIO;
	237
	238	switch (power_state) {
	239	case PWRDM_POWER_ON:
	240	case PWRDM_POWER_INACTIVE:
	241	save_state = 0;
	242	break;
	243	case PWRDM_POWER_OFF:
	244	save_state = 1;
	245	break;
	246	case PWRDM_POWER_RET:
	247	default:
	248	/*
	249	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	250	* doesn't make much scense, since logic is lost and $L1
	251	* needs to be cleaned because of coherency. This makes
	252	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	253	*/
	254	WARN_ON(1);
	255	return -ENXIO;
	256	}
	257
e0555489	258	pwrdm_pre_transition(NULL);
49404dd0	259
3ba2a739 SS	260	/*
	261	* Check MPUSS next state and save interrupt controller if needed.
	262	* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
	263	*/
	264	mpuss_clear_prev_logic_pwrst();
3ba2a739 SS	265	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
	266	(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
	267	save_state = 2;
	268
3ba2a739	269	cpu_clear_prev_logic_pwrst(cpu);
b2b9762f SS	270	set_cpu_next_pwrst(cpu, power_state);
	271	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
	272	scu_pwrst_prepare(cpu, power_state);
5e94c6e3	273	l2x0_pwrst_prepare(cpu, save_state);
b2b9762f SS	274
	275	/*
	276	* Call low level function with targeted low power state.
	277	*/
	278	cpu_suspend(save_state, omap4_finish_suspend);
	279
	280	/*
	281	* Restore the CPUx power state to ON otherwise CPUx
	282	* power domain can transitions to programmed low power
	283	* state while doing WFI outside the low powe code. On
	284	* secure devices, CPUx does WFI which can result in
	285	* domain transition
	286	*/
	287	wakeup_cpu = smp_processor_id();
	288	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
	289
e0555489	290	pwrdm_post_transition(NULL);
49404dd0	291
b2b9762f SS	292	return 0;
	293	}
	294
b5b4f288 SS	295	/**
	296	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	297	* @cpu : CPU ID
	298	* @power_state: CPU low power state.
	299	*/
ccdeed62	300	int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
b5b4f288 SS	301	{
	302	unsigned int cpu_state = 0;
	303
	304	if (omap_rev() == OMAP4430_REV_ES1_0)
	305	return -ENXIO;
	306
	307	if (power_state == PWRDM_POWER_OFF)
	308	cpu_state = 1;
	309
	310	clear_cpu_prev_pwrst(cpu);
	311	set_cpu_next_pwrst(cpu, power_state);
	312	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
	313	scu_pwrst_prepare(cpu, power_state);
	314
	315	/*
260db902	316	* CPU never retuns back if targeted power state is OFF mode.
b5b4f288 SS	317	* CPU ONLINE follows normal CPU ONLINE ptah via
	318	* omap_secondary_startup().
	319	*/
	320	omap4_finish_suspend(cpu_state);
	321
	322	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
	323	return 0;
	324	}
	325
	326
b2b9762f SS	327	/*
	328	* Initialise OMAP4 MPUSS
	329	*/
	330	int __init omap4_mpuss_init(void)
	331	{
	332	struct omap4_cpu_pm_info *pm_info;
b2b9762f SS	333
	334	if (omap_rev() == OMAP4430_REV_ES1_0) {
	335	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	336	return -ENODEV;
	337	}
	338
5e94c6e3 SS	339	sar_base = omap4_get_sar_ram_base();
5e94c6e3 SS	340
b2b9762f SS	341	/* Initilaise per CPU PM information */
	342	pm_info = &per_cpu(omap4_pm_info, 0x0);
	343	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	344	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
5e94c6e3	345	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
b2b9762f SS	346	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	347	if (!pm_info->pwrdm) {
	348	pr_err("Lookup failed for CPU0 pwrdm\n");
	349	return -ENODEV;
	350	}
	351
	352	/* Clear CPU previous power domain state */
	353	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	354	cpu_clear_prev_logic_pwrst(0);
b2b9762f SS	355
	356	/* Initialise CPU0 power domain state to ON */
	357	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	358
	359	pm_info = &per_cpu(omap4_pm_info, 0x1);
	360	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	361	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
5e94c6e3	362	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
b2b9762f SS	363	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	364	if (!pm_info->pwrdm) {
	365	pr_err("Lookup failed for CPU1 pwrdm\n");
	366	return -ENODEV;
	367	}
	368
	369	/* Clear CPU previous power domain state */
	370	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	371	cpu_clear_prev_logic_pwrst(1);
b2b9762f SS	372
	373	/* Initialise CPU1 power domain state to ON */
	374	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	375
e44f9a77 SS	376	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	377	if (!mpuss_pd) {
	378	pr_err("Failed to lookup MPUSS power domain\n");
	379	return -ENODEV;
	380	}
	381	pwrdm_clear_all_prev_pwrst(mpuss_pd);
3ba2a739	382	mpuss_clear_prev_logic_pwrst();
e44f9a77	383
b2b9762f SS	384	/* Save device type on scratchpad for low level code to use */
	385	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
	386	__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	387	else
	388	__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
	389
5e94c6e3 SS	390	save_l2x0_context();
5e94c6e3 SS	391
b2b9762f SS	392	return 0;
	393	}
	394
	395	#endif