[deliverable/linux.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR
 *	OFF		OFF		OFF(Device OFF *TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include "soc.h"
#include "common.h"
#include "omap44xx.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
#include "prcm_mpu54xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"

#ifdef CONFIG_SMP

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
	void __iomem *l2x0_sar_addr;
};

/**
 * struct cpu_pm_ops - CPU pm operations
 * @finish_suspend:	CPU suspend finisher function pointer
 * @resume:		CPU resume function pointer
 * @scu_prepare:	CPU Snoop Control program function pointer
 * @hotplug_restart:	CPU restart function pointer
 *
 * Structure holds functions pointer for CPU low power operations like
 * suspend, resume and scu programming.
 */
struct cpu_pm_ops {
	int (*finish_suspend)(unsigned long cpu_state);
	void (*resume)(void);
	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
	void (*hotplug_restart)(void);
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static void __iomem *sar_base;
static u32 cpu_context_offset;

static int default_finish_suspend(unsigned long cpu_state)
{
	omap_do_wfi();
	return 0;
}

static void dummy_cpu_resume(void)
{}

static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
{}

static struct cpu_pm_ops omap_pm_ops = {
	.finish_suspend		= default_finish_suspend,
	.resume			= dummy_cpu_resume,
	.scu_prepare		= dummy_scu_prepare,
	.hotplug_restart	= dummy_cpu_resume,
};

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->wkup_sar_addr)
		writel_relaxed(addr, pm_info->wkup_sar_addr);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	if (pm_info->scu_sar_addr)
		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
}

/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}

static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
{
	u32 reg;

	if (cpu_id) {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
	} else {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
	}
}

/*
 * Store the CPU cluster state for L2X0 low power operations.
 */
static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->l2x0_sar_addr)
		writel_relaxed(save_state, pm_info->l2x0_sar_addr);
}

/*
 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 * in every restore MPUSS OFF path.
 */
#ifdef CONFIG_CACHE_L2X0
static void __init save_l2x0_context(void)
{
	void __iomem *l2x0_base = omap4_get_l2cache_base();

	if (l2x0_base && sar_base) {
		writel_relaxed(l2x0_saved_regs.aux_ctrl,
			       sar_base + L2X0_AUXCTRL_OFFSET);
		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
			       sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	}
}
#else
static void __init save_l2x0_context(void)
{}
#endif

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
	unsigned int wakeup_cpu;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		cpu_logic_state = PWRDM_POWER_OFF;
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
			save_state = 0;
			break;
		}
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_pre_transition(NULL);

	/*
	 * Check MPUSS next state and save interrupt controller if needed.
	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
	 */
	mpuss_clear_prev_logic_pwrst();
	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
		save_state = 2;

	cpu_clear_prev_logic_pwrst(cpu);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
	omap_pm_ops.scu_prepare(cpu, power_state);
	l2x0_pwrst_prepare(cpu, save_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	if (save_state)
		cpu_suspend(save_state, omap_pm_ops.finish_suspend);
	else
		omap_pm_ops.finish_suspend(save_state);

	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
		gic_dist_enable();

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	wakeup_cpu = smp_processor_id();
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pwrdm_post_transition(NULL);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	/* Use the achievable power state for the domain */
	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
					       false, power_state);

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
	omap_pm_ops.scu_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap4_secondary_startup().
	 */
	omap_pm_ops.finish_suspend(cpu_state);

	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	return 0;
}


/*
 * Enable Mercury Fast HG retention mode by default.
 */
static void enable_mercury_retention_mode(void)
{
	u32 reg;

	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
				  OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	/* Enable HG_EN, HG_RAMPUP = fast mode */
	reg |= BIT(24) | BIT(25);
	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
				      OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
}

/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	if (cpu_is_omap44xx())
		sar_base = omap4_get_sar_ram_base();

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
		pm_info->wkup_sar_addr = sar_base +
					CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	}
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(0);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
		pm_info->wkup_sar_addr = sar_base +
					CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	}

	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(1);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	mpuss_clear_prev_logic_pwrst();

	if (sar_base) {
		/* Save device type on scratchpad for low level code to use */
		writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
			       sar_base + OMAP_TYPE_OFFSET);
		save_l2x0_context();
	}

	if (cpu_is_omap44xx()) {
		omap_pm_ops.finish_suspend = omap4_finish_suspend;
		omap_pm_ops.resume = omap4_cpu_resume;
		omap_pm_ops.scu_prepare = scu_pwrst_prepare;
		omap_pm_ops.hotplug_restart = omap4_secondary_startup;
		cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
		cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
		enable_mercury_retention_mode();
	}

	if (cpu_is_omap446x())
		omap_pm_ops.hotplug_restart = omap4460_secondary_startup;

	return 0;
}

#endif
Commit	Line	Data
b2b9762f SS	1	/*
	2	* OMAP MPUSS low power code
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	*
	7	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	8	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	9	* CPU0 and CPU1 LPRM modules.
	10	* CPU0, CPU1 and MPUSS each have there own power domain and
	11	* hence multiple low power combinations of MPUSS are possible.
	12	*
	13	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	14	* because the mode is not supported by hw constraints of dormant
	15	* mode. While waking up from the dormant mode, a reset signal
	16	* to the Cortex-A9 processor must be asserted by the external
	17	* power controller.
	18	*
	19	* With architectural inputs and hardware recommendations, only
	20	* below modes are supported from power gain vs latency point of view.
	21	*
	22	* CPU0 CPU1 MPUSS
	23	* ----------------------------------------------
	24	* ON ON ON
	25	* ON(Inactive) OFF ON(Inactive)
	26	* OFF OFF CSWR
3ba2a739 SS	27	* OFF OFF OSWR
3ba2a739 SS	28	* OFF OFF OFF(Device OFF *TBD)
b2b9762f SS	29	* ----------------------------------------------
	30	*
	31	* Note: CPU0 is the master core and it is the last CPU to go down
	32	* and first to wake-up when MPUSS low power states are excercised
	33	*
	34	*
	35	* This program is free software; you can redistribute it and/or modify
	36	* it under the terms of the GNU General Public License version 2 as
	37	* published by the Free Software Foundation.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/io.h>
	42	#include <linux/errno.h>
	43	#include <linux/linkage.h>
	44	#include <linux/smp.h>
	45
	46	#include <asm/cacheflush.h>
	47	#include <asm/tlbflush.h>
	48	#include <asm/smp_scu.h>
b2b9762f SS	49	#include <asm/pgalloc.h>
b2b9762f SS	50	#include <asm/suspend.h>
5e94c6e3	51	#include <asm/hardware/cache-l2x0.h>
b2b9762f	52
e4c060db	53	#include "soc.h"
b2b9762f	54	#include "common.h"
c49f34bc	55	#include "omap44xx.h"
b2b9762f SS	56	#include "omap4-sar-layout.h"
b2b9762f SS	57	#include "pm.h"
3ba2a739	58	#include "prcm_mpu44xx.h"
a89726d3	59	#include "prcm_mpu54xx.h"
3ba2a739 SS	60	#include "prminst44xx.h"
	61	#include "prcm44xx.h"
	62	#include "prm44xx.h"
	63	#include "prm-regbits-44xx.h"
b2b9762f SS	64
	65	#ifdef CONFIG_SMP
	66
	67	struct omap4_cpu_pm_info {
	68	struct powerdomain *pwrdm;
	69	void __iomem *scu_sar_addr;
	70	void __iomem *wkup_sar_addr;
5e94c6e3	71	void __iomem *l2x0_sar_addr;
b2b9762f SS	72	};
b2b9762f SS	73
9f192cf7 SS	74	/**
	75	* struct cpu_pm_ops - CPU pm operations
	76	* @finish_suspend: CPU suspend finisher function pointer
	77	* @resume: CPU resume function pointer
	78	* @scu_prepare: CPU Snoop Control program function pointer
e97c4eb3	79	* @hotplug_restart: CPU restart function pointer
9f192cf7 SS	80	*
	81	* Structure holds functions pointer for CPU low power operations like
	82	* suspend, resume and scu programming.
	83	*/
	84	struct cpu_pm_ops {
	85	int (*finish_suspend)(unsigned long cpu_state);
	86	void (*resume)(void);
	87	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
e97c4eb3	88	void (*hotplug_restart)(void);
9f192cf7 SS	89	};
9f192cf7 SS	90
b2b9762f	91	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	92	static struct powerdomain *mpuss_pd;
5e94c6e3	93	static void __iomem *sar_base;
a89726d3	94	static u32 cpu_context_offset;
b2b9762f	95
9f192cf7 SS	96	static int default_finish_suspend(unsigned long cpu_state)
	97	{
	98	omap_do_wfi();
	99	return 0;
	100	}
	101
	102	static void dummy_cpu_resume(void)
	103	{}
	104
	105	static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
	106	{}
	107
f734a9b3	108	static struct cpu_pm_ops omap_pm_ops = {
9f192cf7 SS	109	.finish_suspend = default_finish_suspend,
	110	.resume = dummy_cpu_resume,
	111	.scu_prepare = dummy_scu_prepare,
e97c4eb3	112	.hotplug_restart = dummy_cpu_resume,
9f192cf7 SS	113	};
9f192cf7 SS	114
b2b9762f SS	115	/*
	116	* Program the wakeup routine address for the CPU0 and CPU1
	117	* used for OFF or DORMANT wakeup.
	118	*/
	119	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	120	{
	121	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	122
325f29da RN	123	if (pm_info->wkup_sar_addr)
325f29da RN	124	writel_relaxed(addr, pm_info->wkup_sar_addr);
b2b9762f SS	125	}
b2b9762f SS	126
b2b9762f SS	127	/*
	128	* Store the SCU power status value to scratchpad memory
	129	*/
	130	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	131	{
	132	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	133	u32 scu_pwr_st;
	134
	135	switch (cpu_state) {
	136	case PWRDM_POWER_RET:
	137	scu_pwr_st = SCU_PM_DORMANT;
	138	break;
	139	case PWRDM_POWER_OFF:
	140	scu_pwr_st = SCU_PM_POWEROFF;
	141	break;
	142	case PWRDM_POWER_ON:
	143	case PWRDM_POWER_INACTIVE:
	144	default:
	145	scu_pwr_st = SCU_PM_NORMAL;
	146	break;
	147	}
	148
325f29da RN	149	if (pm_info->scu_sar_addr)
325f29da RN	150	writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
b2b9762f SS	151	}
b2b9762f SS	152
3ba2a739 SS	153	/* Helper functions for MPUSS OSWR */
	154	static inline void mpuss_clear_prev_logic_pwrst(void)
	155	{
	156	u32 reg;
	157
	158	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	159	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	160	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
	161	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	162	}
	163
	164	static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
	165	{
	166	u32 reg;
	167
	168	if (cpu_id) {
	169	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	170	cpu_context_offset);
3ba2a739	171	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	172	cpu_context_offset);
3ba2a739 SS	173	} else {
3ba2a739 SS	174	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	175	cpu_context_offset);
3ba2a739	176	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	177	cpu_context_offset);
3ba2a739 SS	178	}
	179	}
	180
5e94c6e3 SS	181	/*
	182	* Store the CPU cluster state for L2X0 low power operations.
	183	*/
	184	static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
	185	{
	186	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	187
325f29da RN	188	if (pm_info->l2x0_sar_addr)
325f29da RN	189	writel_relaxed(save_state, pm_info->l2x0_sar_addr);
5e94c6e3 SS	190	}
	191
	192	/*
	193	* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
	194	* in every restore MPUSS OFF path.
	195	*/
	196	#ifdef CONFIG_CACHE_L2X0
7a09b28e	197	static void __init save_l2x0_context(void)
5e94c6e3	198	{
325f29da RN	199	void __iomem *l2x0_base = omap4_get_l2cache_base();
	200
	201	if (l2x0_base && sar_base) {
	202	writel_relaxed(l2x0_saved_regs.aux_ctrl,
	203	sar_base + L2X0_AUXCTRL_OFFSET);
	204	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
	205	sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	206	}
5e94c6e3 SS	207	}
5e94c6e3 SS	208	#else
7a09b28e	209	static void __init save_l2x0_context(void)
5e94c6e3 SS	210	{}
	211	#endif
	212
b2b9762f SS	213	/**
	214	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
	215	* The purpose of this function is to manage low power programming
	216	* of OMAP4 MPUSS subsystem
	217	* @cpu : CPU ID
	218	* @power_state: Low power state.
e44f9a77 SS	219	*
	220	* MPUSS states for the context save:
	221	* save_state =
	222	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	223	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	224	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	225	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	226	*/
	227	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	228	{
32d174ed	229	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
a30d81b9	230	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
b2b9762f SS	231	unsigned int wakeup_cpu;
	232
	233	if (omap_rev() == OMAP4430_REV_ES1_0)
	234	return -ENXIO;
	235
	236	switch (power_state) {
	237	case PWRDM_POWER_ON:
	238	case PWRDM_POWER_INACTIVE:
	239	save_state = 0;
	240	break;
	241	case PWRDM_POWER_OFF:
a30d81b9	242	cpu_logic_state = PWRDM_POWER_OFF;
b2b9762f SS	243	save_state = 1;
	244	break;
	245	case PWRDM_POWER_RET:
6099dd37 RN	246	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
	247	save_state = 0;
	248	break;
	249	}
b2b9762f SS	250	default:
	251	/*
	252	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	253	* doesn't make much scense, since logic is lost and $L1
	254	* needs to be cleaned because of coherency. This makes
	255	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	256	*/
	257	WARN_ON(1);
	258	return -ENXIO;
	259	}
	260
e0555489	261	pwrdm_pre_transition(NULL);
49404dd0	262
3ba2a739 SS	263	/*
	264	* Check MPUSS next state and save interrupt controller if needed.
	265	* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
	266	*/
	267	mpuss_clear_prev_logic_pwrst();
3ba2a739 SS	268	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
	269	(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
	270	save_state = 2;
	271
3ba2a739	272	cpu_clear_prev_logic_pwrst(cpu);
32d174ed	273	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
a30d81b9	274	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
9f192cf7 SS	275	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
9f192cf7 SS	276	omap_pm_ops.scu_prepare(cpu, power_state);
5e94c6e3	277	l2x0_pwrst_prepare(cpu, save_state);
b2b9762f SS	278
	279	/*
	280	* Call low level function with targeted low power state.
	281	*/
72433eba	282	if (save_state)
9f192cf7	283	cpu_suspend(save_state, omap_pm_ops.finish_suspend);
72433eba	284	else
9f192cf7	285	omap_pm_ops.finish_suspend(save_state);
b2b9762f	286
74ed7bdc SG	287	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
	288	gic_dist_enable();
	289
b2b9762f SS	290	/*
	291	* Restore the CPUx power state to ON otherwise CPUx
	292	* power domain can transitions to programmed low power
	293	* state while doing WFI outside the low powe code. On
	294	* secure devices, CPUx does WFI which can result in
	295	* domain transition
	296	*/
	297	wakeup_cpu = smp_processor_id();
32d174ed	298	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b2b9762f	299
e0555489	300	pwrdm_post_transition(NULL);
49404dd0	301
b2b9762f SS	302	return 0;
	303	}
	304
b5b4f288 SS	305	/**
	306	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	307	* @cpu : CPU ID
	308	* @power_state: CPU low power state.
	309	*/
8bd26e3a	310	int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
b5b4f288	311	{
ff999b8a	312	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
32d174ed	313	unsigned int cpu_state = 0;
b5b4f288 SS	314
	315	if (omap_rev() == OMAP4430_REV_ES1_0)
	316	return -ENXIO;
	317
3e6a1c94 NM	318	/* Use the achievable power state for the domain */
	319	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
	320	false, power_state);
	321
b5b4f288 SS	322	if (power_state == PWRDM_POWER_OFF)
	323	cpu_state = 1;
	324
32d174ed PW	325	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
32d174ed PW	326	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
e97c4eb3	327	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
9f192cf7	328	omap_pm_ops.scu_prepare(cpu, power_state);
b5b4f288 SS	329
b5b4f288 SS	330	/*
260db902	331	* CPU never retuns back if targeted power state is OFF mode.
b5b4f288	332	* CPU ONLINE follows normal CPU ONLINE ptah via
baf4b7d3	333	* omap4_secondary_startup().
b5b4f288	334	*/
9f192cf7	335	omap_pm_ops.finish_suspend(cpu_state);
b5b4f288	336
32d174ed	337	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b5b4f288 SS	338	return 0;
	339	}
	340
	341
6d846c46 SS	342	/*
	343	* Enable Mercury Fast HG retention mode by default.
	344	*/
	345	static void enable_mercury_retention_mode(void)
	346	{
	347	u32 reg;
	348
	349	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
	350	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	351	/* Enable HG_EN, HG_RAMPUP = fast mode */
	352	reg \|= BIT(24) \| BIT(25);
	353	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
	354	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	355	}
	356
b2b9762f SS	357	/*
	358	* Initialise OMAP4 MPUSS
	359	*/
	360	int __init omap4_mpuss_init(void)
	361	{
	362	struct omap4_cpu_pm_info *pm_info;
b2b9762f SS	363
	364	if (omap_rev() == OMAP4430_REV_ES1_0) {
	365	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	366	return -ENODEV;
	367	}
	368
325f29da RN	369	if (cpu_is_omap44xx())
325f29da RN	370	sar_base = omap4_get_sar_ram_base();
5e94c6e3	371
b2b9762f SS	372	/* Initilaise per CPU PM information */
b2b9762f SS	373	pm_info = &per_cpu(omap4_pm_info, 0x0);
325f29da RN	374	if (sar_base) {
	375	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	376	pm_info->wkup_sar_addr = sar_base +
	377	CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	378	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	379	}
b2b9762f SS	380	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	381	if (!pm_info->pwrdm) {
	382	pr_err("Lookup failed for CPU0 pwrdm\n");
	383	return -ENODEV;
	384	}
	385
	386	/* Clear CPU previous power domain state */
	387	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	388	cpu_clear_prev_logic_pwrst(0);
b2b9762f SS	389
	390	/* Initialise CPU0 power domain state to ON */
	391	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	392
	393	pm_info = &per_cpu(omap4_pm_info, 0x1);
325f29da RN	394	if (sar_base) {
	395	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	396	pm_info->wkup_sar_addr = sar_base +
	397	CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	398	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	399	}
ff999b8a	400
b2b9762f SS	401	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	402	if (!pm_info->pwrdm) {
	403	pr_err("Lookup failed for CPU1 pwrdm\n");
	404	return -ENODEV;
	405	}
	406
	407	/* Clear CPU previous power domain state */
	408	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	409	cpu_clear_prev_logic_pwrst(1);
b2b9762f SS	410
	411	/* Initialise CPU1 power domain state to ON */
	412	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	413
e44f9a77 SS	414	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	415	if (!mpuss_pd) {
	416	pr_err("Failed to lookup MPUSS power domain\n");
	417	return -ENODEV;
	418	}
	419	pwrdm_clear_all_prev_pwrst(mpuss_pd);
3ba2a739	420	mpuss_clear_prev_logic_pwrst();
e44f9a77	421
325f29da RN	422	if (sar_base) {
	423	/* Save device type on scratchpad for low level code to use */
	424	writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
	425	sar_base + OMAP_TYPE_OFFSET);
	426	save_l2x0_context();
	427	}
5e94c6e3	428
9f192cf7 SS	429	if (cpu_is_omap44xx()) {
	430	omap_pm_ops.finish_suspend = omap4_finish_suspend;
	431	omap_pm_ops.resume = omap4_cpu_resume;
	432	omap_pm_ops.scu_prepare = scu_pwrst_prepare;
e97c4eb3	433	omap_pm_ops.hotplug_restart = omap4_secondary_startup;
a89726d3 SS	434	cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	435	} else if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
	436	cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
6d846c46	437	enable_mercury_retention_mode();
9f192cf7 SS	438	}
9f192cf7 SS	439
e97c4eb3 SS	440	if (cpu_is_omap446x())
	441	omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
	442
b2b9762f SS	443	return 0;
	444	}
	445
	446	#endif