[deliverable/linux.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR (*TBD)
 *	OFF		OFF		OFF* (*TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/system.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>

#include <plat/omap44xx.h>

#include "common.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "powerdomain.h"

#ifdef CONFIG_SMP

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	__raw_writel(addr, pm_info->wkup_sar_addr);
}

/*
 * Set the CPUx powerdomain's previous power state
 */
static inline void set_cpu_next_pwrst(unsigned int cpu_id,
				unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
}

/*
 * Read CPU's previous power state
 */
static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
}

/*
 * Clear the CPUx powerdomain's previous power state
 */
static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
}

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	unsigned int save_state = 0;
	unsigned int wakeup_cpu;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	clear_cpu_prev_pwrst(cpu);
	set_cpu_next_pwrst(cpu, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
	scu_pwrst_prepare(cpu, power_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	cpu_suspend(save_state, omap4_finish_suspend);

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	wakeup_cpu = smp_processor_id();
	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	clear_cpu_prev_pwrst(cpu);
	set_cpu_next_pwrst(cpu, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
	scu_pwrst_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targetted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap_secondary_startup().
	 */
	omap4_finish_suspend(cpu_state);

	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
	return 0;
}


/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;
	void __iomem *sar_base = omap4_get_sar_ram_base();

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);

	/* Save device type on scratchpad for low level code to use */
	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
		__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	else
		__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);

	return 0;
}

#endif
Commit	Line	Data
b2b9762f SS	1	/*
	2	* OMAP MPUSS low power code
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	*
	7	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	8	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	9	* CPU0 and CPU1 LPRM modules.
	10	* CPU0, CPU1 and MPUSS each have there own power domain and
	11	* hence multiple low power combinations of MPUSS are possible.
	12	*
	13	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	14	* because the mode is not supported by hw constraints of dormant
	15	* mode. While waking up from the dormant mode, a reset signal
	16	* to the Cortex-A9 processor must be asserted by the external
	17	* power controller.
	18	*
	19	* With architectural inputs and hardware recommendations, only
	20	* below modes are supported from power gain vs latency point of view.
	21	*
	22	* CPU0 CPU1 MPUSS
	23	* ----------------------------------------------
	24	* ON ON ON
	25	* ON(Inactive) OFF ON(Inactive)
	26	* OFF OFF CSWR
	27	* OFF OFF OSWR (*TBD)
	28	* OFF OFF OFF* (*TBD)
	29	* ----------------------------------------------
	30	*
	31	* Note: CPU0 is the master core and it is the last CPU to go down
	32	* and first to wake-up when MPUSS low power states are excercised
	33	*
	34	*
	35	* This program is free software; you can redistribute it and/or modify
	36	* it under the terms of the GNU General Public License version 2 as
	37	* published by the Free Software Foundation.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/io.h>
	42	#include <linux/errno.h>
	43	#include <linux/linkage.h>
	44	#include <linux/smp.h>
	45
	46	#include <asm/cacheflush.h>
	47	#include <asm/tlbflush.h>
	48	#include <asm/smp_scu.h>
	49	#include <asm/system.h>
	50	#include <asm/pgalloc.h>
	51	#include <asm/suspend.h>
	52
	53	#include <plat/omap44xx.h>
	54
	55	#include "common.h"
	56	#include "omap4-sar-layout.h"
	57	#include "pm.h"
	58	#include "powerdomain.h"
	59
	60	#ifdef CONFIG_SMP
	61
	62	struct omap4_cpu_pm_info {
	63	struct powerdomain *pwrdm;
	64	void __iomem *scu_sar_addr;
65	void __iomem *wkup_sar_addr;
66	};
67
68	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	69	static struct powerdomain *mpuss_pd;
b2b9762f SS	70
	71	/*
	72	* Program the wakeup routine address for the CPU0 and CPU1
	73	* used for OFF or DORMANT wakeup.
	74	*/
	75	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	76	{
	77	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	78
	79	__raw_writel(addr, pm_info->wkup_sar_addr);
	80	}
	81
	82	/*
	83	* Set the CPUx powerdomain's previous power state
	84	*/
	85	static inline void set_cpu_next_pwrst(unsigned int cpu_id,
	86	unsigned int power_state)
	87	{
	88	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	89
	90	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	91	}
	92
	93	/*
	94	* Read CPU's previous power state
	95	*/
	96	static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
	97	{
	98	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	99
	100	return pwrdm_read_prev_pwrst(pm_info->pwrdm);
	101	}
	102
	103	/*
	104	* Clear the CPUx powerdomain's previous power state
	105	*/
	106	static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
	107	{
	108	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	109
	110	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	111	}
	112
	113	/*
	114	* Store the SCU power status value to scratchpad memory
	115	*/
	116	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	117	{
	118	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	119	u32 scu_pwr_st;
	120
	121	switch (cpu_state) {
	122	case PWRDM_POWER_RET:
	123	scu_pwr_st = SCU_PM_DORMANT;
	124	break;
	125	case PWRDM_POWER_OFF:
	126	scu_pwr_st = SCU_PM_POWEROFF;
	127	break;
	128	case PWRDM_POWER_ON:
	129	case PWRDM_POWER_INACTIVE:
	130	default:
	131	scu_pwr_st = SCU_PM_NORMAL;
	132	break;
	133	}
134
135	__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
136	}
137
138	/**
139	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
140	* The purpose of this function is to manage low power programming
141	* of OMAP4 MPUSS subsystem
142	* @cpu : CPU ID
143	* @power_state: Low power state.
e44f9a77 SS	144	*
	145	* MPUSS states for the context save:
	146	* save_state =
	147	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	148	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	149	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	150	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	151	*/
	152	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	153	{
	154	unsigned int save_state = 0;
	155	unsigned int wakeup_cpu;
	156
	157	if (omap_rev() == OMAP4430_REV_ES1_0)
	158	return -ENXIO;
	159
	160	switch (power_state) {
	161	case PWRDM_POWER_ON:
	162	case PWRDM_POWER_INACTIVE:
	163	save_state = 0;
	164	break;
	165	case PWRDM_POWER_OFF:
	166	save_state = 1;
	167	break;
	168	case PWRDM_POWER_RET:
	169	default:
	170	/*
	171	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	172	* doesn't make much scense, since logic is lost and $L1
	173	* needs to be cleaned because of coherency. This makes
	174	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	175	*/
	176	WARN_ON(1);
	177	return -ENXIO;
	178	}
	179
e44f9a77	180	pwrdm_clear_all_prev_pwrst(mpuss_pd);
b2b9762f SS	181	clear_cpu_prev_pwrst(cpu);
	182	set_cpu_next_pwrst(cpu, power_state);
	183	set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
	184	scu_pwrst_prepare(cpu, power_state);
	185
	186	/*
	187	* Call low level function with targeted low power state.
	188	*/
	189	cpu_suspend(save_state, omap4_finish_suspend);
	190
	191	/*
	192	* Restore the CPUx power state to ON otherwise CPUx
	193	* power domain can transitions to programmed low power
	194	* state while doing WFI outside the low powe code. On
	195	* secure devices, CPUx does WFI which can result in
	196	* domain transition
	197	*/
	198	wakeup_cpu = smp_processor_id();
	199	set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
	200
	201	return 0;
	202	}
	203
b5b4f288 SS	204	/**
	205	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	206	* @cpu : CPU ID
	207	* @power_state: CPU low power state.
	208	*/
	209	int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
	210	{
	211	unsigned int cpu_state = 0;
	212
	213	if (omap_rev() == OMAP4430_REV_ES1_0)
	214	return -ENXIO;
	215
	216	if (power_state == PWRDM_POWER_OFF)
	217	cpu_state = 1;
	218
	219	clear_cpu_prev_pwrst(cpu);
	220	set_cpu_next_pwrst(cpu, power_state);
	221	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
	222	scu_pwrst_prepare(cpu, power_state);
	223
	224	/*
	225	* CPU never retuns back if targetted power state is OFF mode.
	226	* CPU ONLINE follows normal CPU ONLINE ptah via
	227	* omap_secondary_startup().
	228	*/
	229	omap4_finish_suspend(cpu_state);
	230
	231	set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
	232	return 0;
	233	}
	234
	235
b2b9762f SS	236	/*
	237	* Initialise OMAP4 MPUSS
	238	*/
	239	int __init omap4_mpuss_init(void)
	240	{
	241	struct omap4_cpu_pm_info *pm_info;
	242	void __iomem *sar_base = omap4_get_sar_ram_base();
	243
	244	if (omap_rev() == OMAP4430_REV_ES1_0) {
	245	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	246	return -ENODEV;
	247	}
	248
	249	/* Initilaise per CPU PM information */
	250	pm_info = &per_cpu(omap4_pm_info, 0x0);
	251	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	252	pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	253	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	254	if (!pm_info->pwrdm) {
	255	pr_err("Lookup failed for CPU0 pwrdm\n");
	256	return -ENODEV;
	257	}
	258
	259	/* Clear CPU previous power domain state */
	260	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	261
	262	/* Initialise CPU0 power domain state to ON */
	263	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	264
	265	pm_info = &per_cpu(omap4_pm_info, 0x1);
	266	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	267	pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	268	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	269	if (!pm_info->pwrdm) {
	270	pr_err("Lookup failed for CPU1 pwrdm\n");
	271	return -ENODEV;
	272	}
	273
	274	/* Clear CPU previous power domain state */
	275	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	276
	277	/* Initialise CPU1 power domain state to ON */
	278	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	279
e44f9a77 SS	280	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	281	if (!mpuss_pd) {
	282	pr_err("Failed to lookup MPUSS power domain\n");
	283	return -ENODEV;
	284	}
	285	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	286
b2b9762f SS	287	/* Save device type on scratchpad for low level code to use */
	288	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
	289	__raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
	290	else
	291	__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
	292
	293	return 0;
	294	}
	295
	296	#endif