[deliverable/linux.git] / arch / arm / mach-omap2 / omap-smp.c

/*
 * OMAP4 SMP source file. It contains platform specific functions
 * needed for the linux smp kernel.
 *
 * Copyright (C) 2009 Texas Instruments, Inc.
 *
 * Author:
 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * Platform file needed for the OMAP4 SMP. This file is based on arm
 * realview smp platform.
 * * Copyright (c) 2002 ARM Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>

#include <asm/smp_scu.h>

#include "omap-secure.h"
#include "omap-wakeupgen.h"
#include <asm/cputype.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "clockdomain.h"
#include "pm.h"

#define CPU_MASK		0xff0ffff0
#define CPU_CORTEX_A9		0x410FC090
#define CPU_CORTEX_A15		0x410FC0F0

#define OMAP5_CORE_COUNT	0x2

/* SCU base address */
static void __iomem *scu_base;

static DEFINE_SPINLOCK(boot_lock);

void __iomem *omap4_get_scu_base(void)
{
	return scu_base;
}

static void omap4_secondary_init(unsigned int cpu)
{
	/*
	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
	 * OMAP443X GP devices- SMP bit isn't accessible.
	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
	 */
	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
							4, 0, 0, 0, 0, 0);

	/*
	 * Configure the CNTFRQ register for the secondary cpu's which
	 * indicates the frequency of the cpu local timers.
	 */
	if (soc_is_omap54xx() || soc_is_dra7xx())
		set_cntfreq();

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	static struct clockdomain *cpu1_clkdm;
	static bool booted;
	static struct powerdomain *cpu1_pwrdm;
	void __iomem *base = omap_get_wakeupgen_base();

	/*
	 * Set synchronisation state between this boot processor
	 * and the secondary one
	 */
	spin_lock(&boot_lock);

	/*
	 * Update the AuxCoreBoot0 with boot state for secondary core.
	 * omap4_secondary_startup() routine will hold the secondary core till
	 * the AuxCoreBoot1 register is updated with cpu state
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_modify_auxcoreboot0(0x200, 0xfffffdff);
	else
		writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);

	if (!cpu1_clkdm && !cpu1_pwrdm) {
		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
		cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
	}

	/*
	 * The SGI(Software Generated Interrupts) are not wakeup capable
	 * from low power states. This is known limitation on OMAP4 and
	 * needs to be worked around by using software forced clockdomain
	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
	 * software force wakeup. The clockdomain is then put back to
	 * hardware supervised mode.
	 * More details can be found in OMAP4430 TRM - Version J
	 * Section :
	 *	4.3.4.2 Power States of CPU0 and CPU1
	 */
	if (booted && cpu1_pwrdm && cpu1_clkdm) {
		/*
		 * GIC distributor control register has changed between
		 * CortexA9 r1pX and r2pX. The Control Register secure
		 * banked version is now composed of 2 bits:
		 * bit 0 == Secure Enable
		 * bit 1 == Non-Secure Enable
		 * The Non-Secure banked register has not changed
		 * Because the ROM Code is based on the r1pX GIC, the CPU1
		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
		 * The workaround must be:
		 * 1) Before doing the CPU1 wakeup, CPU0 must disable
		 * the GIC distributor
		 * 2) CPU1 must re-enable the GIC distributor on
		 * it's wakeup path.
		 */
		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
			local_irq_disable();
			gic_dist_disable();
		}

		/*
		 * Ensure that CPU power state is set to ON to avoid CPU
		 * powerdomain transition on wfi
		 */
		clkdm_wakeup(cpu1_clkdm);
		omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
		clkdm_allow_idle(cpu1_clkdm);

		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
			while (gic_dist_disabled()) {
				udelay(1);
				cpu_relax();
			}
			gic_timer_retrigger();
			local_irq_enable();
		}
	} else {
		dsb_sev();
		booted = true;
	}

	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

	/*
	 * Now the secondary core is starting up let it run its
	 * calibrations, then wait for it to finish
	 */
	spin_unlock(&boot_lock);

	return 0;
}

/*
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
static void __init omap4_smp_init_cpus(void)
{
	unsigned int i = 0, ncores = 1, cpu_id;

	/* Use ARM cpuid check here, as SoC detection will not work so early */
	cpu_id = read_cpuid_id() & CPU_MASK;
	if (cpu_id == CPU_CORTEX_A9) {
		/*
		 * Currently we can't call ioremap here because
		 * SoC detection won't work until after init_early.
		 */
		scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
		BUG_ON(!scu_base);
		ncores = scu_get_core_count(scu_base);
	} else if (cpu_id == CPU_CORTEX_A15) {
		ncores = OMAP5_CORE_COUNT;
	}

	/* sanity check */
	if (ncores > nr_cpu_ids) {
		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
			ncores, nr_cpu_ids);
		ncores = nr_cpu_ids;
	}

	for (i = 0; i < ncores; i++)
		set_cpu_possible(i, true);
}

static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{
	void *startup_addr = omap4_secondary_startup;
	void __iomem *base = omap_get_wakeupgen_base();

	/*
	 * Initialise the SCU and wake up the secondary core using
	 * wakeup_secondary().
	 */
	if (scu_base)
		scu_enable(scu_base);

	if (cpu_is_omap446x())
		startup_addr = omap4460_secondary_startup;

	/*
	 * Write the address of secondary startup routine into the
	 * AuxCoreBoot1 where ROM code will jump and start executing
	 * on secondary core once out of WFE
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	else
		writel_relaxed(virt_to_phys(omap5_secondary_startup),
			       base + OMAP_AUX_CORE_BOOT_1);

}

struct smp_operations omap4_smp_ops __initdata = {
	.smp_init_cpus		= omap4_smp_init_cpus,
	.smp_prepare_cpus	= omap4_smp_prepare_cpus,
	.smp_secondary_init	= omap4_secondary_init,
	.smp_boot_secondary	= omap4_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= omap4_cpu_die,
#endif
};
Commit	Line	Data
367cd31e	1	/*
b6b24852	2	* OMAP4 SMP source file. It contains platform specific functions
367cd31e SS	3	* needed for the linux smp kernel.
	4	*
	5	* Copyright (C) 2009 Texas Instruments, Inc.
	6	*
	7	* Author:
	8	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	9	*
	10	* Platform file needed for the OMAP4 SMP. This file is based on arm
	11	* realview smp platform.
	12	* * Copyright (c) 2002 ARM Limited.
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18	#include <linux/init.h>
	19	#include <linux/device.h>
367cd31e SS	20	#include <linux/smp.h>
367cd31e SS	21	#include <linux/io.h>
520f7bd7	22	#include <linux/irqchip/arm-gic.h>
367cd31e	23
367cd31e	24	#include <asm/smp_scu.h>
ee0839c2	25
c1db9d73	26	#include "omap-secure.h"
732231a7	27	#include "omap-wakeupgen.h"
247c445c	28	#include <asm/cputype.h>
4e65331c	29
dbc04161	30	#include "soc.h"
ee0839c2	31	#include "iomap.h"
4e65331c	32	#include "common.h"
e97ca477	33	#include "clockdomain.h"
ff999b8a	34	#include "pm.h"
e97ca477	35
283f708c SS	36	#define CPU_MASK 0xff0ffff0
	37	#define CPU_CORTEX_A9 0x410FC090
	38	#define CPU_CORTEX_A15 0x410FC0F0
	39
	40	#define OMAP5_CORE_COUNT 0x2
	41
367cd31e	42	/* SCU base address */
e4e7a13a	43	static void __iomem *scu_base;
367cd31e	44
367cd31e SS	45	static DEFINE_SPINLOCK(boot_lock);
367cd31e SS	46
02afe8a7 SS	47	void __iomem *omap4_get_scu_base(void)
	48	{
	49	return scu_base;
	50	}
	51
8bd26e3a	52	static void omap4_secondary_init(unsigned int cpu)
367cd31e	53	{
b2b9762f SS	54	/*
	55	* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
	56	* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
	57	* init and for CPU1, a secure PPA API provided. CPU0 must be ON
	58	* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
	59	* OMAP443X GP devices- SMP bit isn't accessible.
	60	* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
	61	*/
	62	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
	63	omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
	64	4, 0, 0, 0, 0, 0);
	65
5523e409 S	66	/*
	67	* Configure the CNTFRQ register for the secondary cpu's which
	68	* indicates the frequency of the cpu local timers.
	69	*/
	70	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	71	set_cntfreq();
	72
367cd31e SS	73	/*
	74	* Synchronise with the boot thread.
	75	*/
	76	spin_lock(&boot_lock);
	77	spin_unlock(&boot_lock);
	78	}
	79
8bd26e3a	80	static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
367cd31e	81	{
e97ca477 SS	82	static struct clockdomain *cpu1_clkdm;
e97ca477 SS	83	static bool booted;
b7806dc7	84	static struct powerdomain *cpu1_pwrdm;
247c445c SS	85	void __iomem *base = omap_get_wakeupgen_base();
247c445c SS	86
367cd31e SS	87	/*
	88	* Set synchronisation state between this boot processor
	89	* and the secondary one
	90	*/
	91	spin_lock(&boot_lock);
	92
	93	/*
942e2c9e	94	* Update the AuxCoreBoot0 with boot state for secondary core.
baf4b7d3	95	* omap4_secondary_startup() routine will hold the secondary core till
367cd31e SS	96	* the AuxCoreBoot1 register is updated with cpu state
	97	* A barrier is added to ensure that write buffer is drained
	98	*/
247c445c SS	99	if (omap_secure_apis_support())
	100	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
	101	else
edfaf05c	102	writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
247c445c	103
b7806dc7	104	if (!cpu1_clkdm && !cpu1_pwrdm) {
e97ca477	105	cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
b7806dc7 SS	106	cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
b7806dc7 SS	107	}
e97ca477 SS	108
	109	/*
	110	* The SGI(Software Generated Interrupts) are not wakeup capable
	111	* from low power states. This is known limitation on OMAP4 and
	112	* needs to be worked around by using software forced clockdomain
	113	* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
	114	* software force wakeup. The clockdomain is then put back to
	115	* hardware supervised mode.
	116	* More details can be found in OMAP4430 TRM - Version J
	117	* Section :
	118	* 4.3.4.2 Power States of CPU0 and CPU1
	119	*/
b7806dc7	120	if (booted && cpu1_pwrdm && cpu1_clkdm) {
ff999b8a SS	121	/*
	122	* GIC distributor control register has changed between
	123	* CortexA9 r1pX and r2pX. The Control Register secure
	124	* banked version is now composed of 2 bits:
	125	* bit 0 == Secure Enable
	126	* bit 1 == Non-Secure Enable
	127	* The Non-Secure banked register has not changed
	128	* Because the ROM Code is based on the r1pX GIC, the CPU1
	129	* GIC restoration will cause a problem to CPU0 Non-Secure SW.
	130	* The workaround must be:
	131	* 1) Before doing the CPU1 wakeup, CPU0 must disable
	132	* the GIC distributor
	133	* 2) CPU1 must re-enable the GIC distributor on
	134	* it's wakeup path.
	135	*/
cd8ce159 CC	136	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
cd8ce159 CC	137	local_irq_disable();
ff999b8a	138	gic_dist_disable();
cd8ce159	139	}
ff999b8a	140
b7806dc7 SS	141	/*
	142	* Ensure that CPU power state is set to ON to avoid CPU
	143	* powerdomain transition on wfi
	144	*/
e97ca477	145	clkdm_wakeup(cpu1_clkdm);
b7806dc7	146	omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
e97ca477	147	clkdm_allow_idle(cpu1_clkdm);
cd8ce159 CC	148
	149	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
	150	while (gic_dist_disabled()) {
	151	udelay(1);
	152	cpu_relax();
	153	}
	154	gic_timer_retrigger();
	155	local_irq_enable();
	156	}
e97ca477 SS	157	} else {
	158	dsb_sev();
	159	booted = true;
	160	}
	161
b1cffebf	162	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
367cd31e	163
367cd31e SS	164	/*
	165	* Now the secondary core is starting up let it run its
	166	* calibrations, then wait for it to finish
	167	*/
	168	spin_unlock(&boot_lock);
	169
	170	return 0;
	171	}
	172
367cd31e SS	173	/*
	174	* Initialise the CPU possible map early - this describes the CPUs
	175	* which may be present or become present in the system.
	176	*/
06915321	177	static void __init omap4_smp_init_cpus(void)
367cd31e	178	{
283f708c SS	179	unsigned int i = 0, ncores = 1, cpu_id;
	180
	181	/* Use ARM cpuid check here, as SoC detection will not work so early */
ac52e83f	182	cpu_id = read_cpuid_id() & CPU_MASK;
283f708c SS	183	if (cpu_id == CPU_CORTEX_A9) {
	184	/*
	185	* Currently we can't call ioremap here because
	186	* SoC detection won't work until after init_early.
	187	*/
80d93756	188	scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
283f708c SS	189	BUG_ON(!scu_base);
	190	ncores = scu_get_core_count(scu_base);
	191	} else if (cpu_id == CPU_CORTEX_A15) {
	192	ncores = OMAP5_CORE_COUNT;
	193	}
367cd31e SS	194
367cd31e SS	195	/* sanity check */
a06f916b RK	196	if (ncores > nr_cpu_ids) {
	197	pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
	198	ncores, nr_cpu_ids);
	199	ncores = nr_cpu_ids;
367cd31e	200	}
367cd31e	201
bbc3d14e RK	202	for (i = 0; i < ncores; i++)
	203	set_cpu_possible(i, true);
	204	}
	205
06915321	206	static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
bbc3d14e	207	{
baf4b7d3	208	void *startup_addr = omap4_secondary_startup;
b699ddd1	209	void __iomem *base = omap_get_wakeupgen_base();
367cd31e	210
05c74a6c RK	211	/*
	212	* Initialise the SCU and wake up the secondary core using
	213	* wakeup_secondary().
	214	*/
283f708c SS	215	if (scu_base)
283f708c SS	216	scu_enable(scu_base);
b699ddd1	217
de70af49	218	if (cpu_is_omap446x())
baf4b7d3	219	startup_addr = omap4460_secondary_startup;
b699ddd1 SS	220
	221	/*
	222	* Write the address of secondary startup routine into the
	223	* AuxCoreBoot1 where ROM code will jump and start executing
	224	* on secondary core once out of WFE
	225	* A barrier is added to ensure that write buffer is drained
	226	*/
	227	if (omap_secure_apis_support())
	228	omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	229	else
edfaf05c VK	230	writel_relaxed(virt_to_phys(omap5_secondary_startup),
edfaf05c VK	231	base + OMAP_AUX_CORE_BOOT_1);
b699ddd1	232
367cd31e	233	}
06915321 MZ	234
	235	struct smp_operations omap4_smp_ops __initdata = {
	236	.smp_init_cpus = omap4_smp_init_cpus,
	237	.smp_prepare_cpus = omap4_smp_prepare_cpus,
	238	.smp_secondary_init = omap4_secondary_init,
	239	.smp_boot_secondary = omap4_boot_secondary,
	240	#ifdef CONFIG_HOTPLUG_CPU
	241	.cpu_die = omap4_cpu_die,
	242	#endif
	243	};