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367cd31e SS |
1 | /* |
2 | * OMAP4 SMP source file. It contains platform specific fucntions | |
3 | * needed for the linux smp kernel. | |
4 | * | |
5 | * Copyright (C) 2009 Texas Instruments, Inc. | |
6 | * | |
7 | * Author: | |
8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
10 | * Platform file needed for the OMAP4 SMP. This file is based on arm | |
11 | * realview smp platform. | |
12 | * * Copyright (c) 2002 ARM Limited. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
367cd31e SS |
20 | #include <linux/smp.h> |
21 | #include <linux/io.h> | |
22 | ||
942e2c9e | 23 | #include <asm/cacheflush.h> |
0f7b332f | 24 | #include <asm/hardware/gic.h> |
367cd31e | 25 | #include <asm/smp_scu.h> |
ee0839c2 | 26 | |
c1db9d73 | 27 | #include "omap-secure.h" |
732231a7 | 28 | #include "omap-wakeupgen.h" |
247c445c | 29 | #include <asm/cputype.h> |
4e65331c | 30 | |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
4e65331c | 33 | #include "common.h" |
e97ca477 | 34 | #include "clockdomain.h" |
ff999b8a | 35 | #include "pm.h" |
e97ca477 | 36 | |
283f708c SS |
37 | #define CPU_MASK 0xff0ffff0 |
38 | #define CPU_CORTEX_A9 0x410FC090 | |
39 | #define CPU_CORTEX_A15 0x410FC0F0 | |
40 | ||
41 | #define OMAP5_CORE_COUNT 0x2 | |
42 | ||
93640735 KH |
43 | u16 pm44xx_errata; |
44 | ||
367cd31e | 45 | /* SCU base address */ |
e4e7a13a | 46 | static void __iomem *scu_base; |
367cd31e | 47 | |
367cd31e SS |
48 | static DEFINE_SPINLOCK(boot_lock); |
49 | ||
02afe8a7 SS |
50 | void __iomem *omap4_get_scu_base(void) |
51 | { | |
52 | return scu_base; | |
53 | } | |
54 | ||
06915321 | 55 | static void __cpuinit omap4_secondary_init(unsigned int cpu) |
367cd31e | 56 | { |
b2b9762f SS |
57 | /* |
58 | * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. | |
59 | * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA | |
60 | * init and for CPU1, a secure PPA API provided. CPU0 must be ON | |
61 | * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. | |
62 | * OMAP443X GP devices- SMP bit isn't accessible. | |
63 | * OMAP446X GP devices - SMP bit access is enabled on both CPUs. | |
64 | */ | |
65 | if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) | |
66 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, | |
67 | 4, 0, 0, 0, 0, 0); | |
68 | ||
367cd31e SS |
69 | /* |
70 | * If any interrupts are already enabled for the primary | |
71 | * core (e.g. timer irq), then they will not have been enabled | |
72 | * for us: do so | |
73 | */ | |
38489533 | 74 | gic_secondary_init(0); |
367cd31e SS |
75 | |
76 | /* | |
77 | * Synchronise with the boot thread. | |
78 | */ | |
79 | spin_lock(&boot_lock); | |
80 | spin_unlock(&boot_lock); | |
81 | } | |
82 | ||
06915321 | 83 | static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) |
367cd31e | 84 | { |
e97ca477 SS |
85 | static struct clockdomain *cpu1_clkdm; |
86 | static bool booted; | |
247c445c SS |
87 | void __iomem *base = omap_get_wakeupgen_base(); |
88 | ||
367cd31e SS |
89 | /* |
90 | * Set synchronisation state between this boot processor | |
91 | * and the secondary one | |
92 | */ | |
93 | spin_lock(&boot_lock); | |
94 | ||
95 | /* | |
942e2c9e | 96 | * Update the AuxCoreBoot0 with boot state for secondary core. |
367cd31e SS |
97 | * omap_secondary_startup() routine will hold the secondary core till |
98 | * the AuxCoreBoot1 register is updated with cpu state | |
99 | * A barrier is added to ensure that write buffer is drained | |
100 | */ | |
247c445c SS |
101 | if (omap_secure_apis_support()) |
102 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); | |
103 | else | |
104 | __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); | |
105 | ||
942e2c9e | 106 | flush_cache_all(); |
367cd31e | 107 | smp_wmb(); |
e97ca477 SS |
108 | |
109 | if (!cpu1_clkdm) | |
110 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); | |
111 | ||
112 | /* | |
113 | * The SGI(Software Generated Interrupts) are not wakeup capable | |
114 | * from low power states. This is known limitation on OMAP4 and | |
115 | * needs to be worked around by using software forced clockdomain | |
116 | * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to | |
117 | * software force wakeup. The clockdomain is then put back to | |
118 | * hardware supervised mode. | |
119 | * More details can be found in OMAP4430 TRM - Version J | |
120 | * Section : | |
121 | * 4.3.4.2 Power States of CPU0 and CPU1 | |
122 | */ | |
123 | if (booted) { | |
ff999b8a SS |
124 | /* |
125 | * GIC distributor control register has changed between | |
126 | * CortexA9 r1pX and r2pX. The Control Register secure | |
127 | * banked version is now composed of 2 bits: | |
128 | * bit 0 == Secure Enable | |
129 | * bit 1 == Non-Secure Enable | |
130 | * The Non-Secure banked register has not changed | |
131 | * Because the ROM Code is based on the r1pX GIC, the CPU1 | |
132 | * GIC restoration will cause a problem to CPU0 Non-Secure SW. | |
133 | * The workaround must be: | |
134 | * 1) Before doing the CPU1 wakeup, CPU0 must disable | |
135 | * the GIC distributor | |
136 | * 2) CPU1 must re-enable the GIC distributor on | |
137 | * it's wakeup path. | |
138 | */ | |
cd8ce159 CC |
139 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { |
140 | local_irq_disable(); | |
ff999b8a | 141 | gic_dist_disable(); |
cd8ce159 | 142 | } |
ff999b8a | 143 | |
e97ca477 SS |
144 | clkdm_wakeup(cpu1_clkdm); |
145 | clkdm_allow_idle(cpu1_clkdm); | |
cd8ce159 CC |
146 | |
147 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { | |
148 | while (gic_dist_disabled()) { | |
149 | udelay(1); | |
150 | cpu_relax(); | |
151 | } | |
152 | gic_timer_retrigger(); | |
153 | local_irq_enable(); | |
154 | } | |
e97ca477 SS |
155 | } else { |
156 | dsb_sev(); | |
157 | booted = true; | |
158 | } | |
159 | ||
79d15ce9 | 160 | gic_raise_softirq(cpumask_of(cpu), 0); |
367cd31e | 161 | |
367cd31e SS |
162 | /* |
163 | * Now the secondary core is starting up let it run its | |
164 | * calibrations, then wait for it to finish | |
165 | */ | |
166 | spin_unlock(&boot_lock); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static void __init wakeup_secondary(void) | |
172 | { | |
ff999b8a | 173 | void *startup_addr = omap_secondary_startup; |
247c445c | 174 | void __iomem *base = omap_get_wakeupgen_base(); |
ff999b8a SS |
175 | |
176 | if (cpu_is_omap446x()) { | |
177 | startup_addr = omap_secondary_startup_4460; | |
178 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; | |
179 | } | |
180 | ||
367cd31e SS |
181 | /* |
182 | * Write the address of secondary startup routine into the | |
942e2c9e | 183 | * AuxCoreBoot1 where ROM code will jump and start executing |
367cd31e SS |
184 | * on secondary core once out of WFE |
185 | * A barrier is added to ensure that write buffer is drained | |
186 | */ | |
247c445c | 187 | if (omap_secure_apis_support()) |
ff999b8a | 188 | omap_auxcoreboot_addr(virt_to_phys(startup_addr)); |
247c445c SS |
189 | else |
190 | __raw_writel(virt_to_phys(omap5_secondary_startup), | |
191 | base + OMAP_AUX_CORE_BOOT_1); | |
192 | ||
367cd31e SS |
193 | smp_wmb(); |
194 | ||
195 | /* | |
196 | * Send a 'sev' to wake the secondary core from WFE. | |
942e2c9e | 197 | * Drain the outstanding writes to memory |
367cd31e | 198 | */ |
a4192d32 | 199 | dsb_sev(); |
367cd31e SS |
200 | mb(); |
201 | } | |
202 | ||
203 | /* | |
204 | * Initialise the CPU possible map early - this describes the CPUs | |
205 | * which may be present or become present in the system. | |
206 | */ | |
06915321 | 207 | static void __init omap4_smp_init_cpus(void) |
367cd31e | 208 | { |
283f708c SS |
209 | unsigned int i = 0, ncores = 1, cpu_id; |
210 | ||
211 | /* Use ARM cpuid check here, as SoC detection will not work so early */ | |
212 | cpu_id = read_cpuid(CPUID_ID) & CPU_MASK; | |
213 | if (cpu_id == CPU_CORTEX_A9) { | |
214 | /* | |
215 | * Currently we can't call ioremap here because | |
216 | * SoC detection won't work until after init_early. | |
217 | */ | |
218 | scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); | |
219 | BUG_ON(!scu_base); | |
220 | ncores = scu_get_core_count(scu_base); | |
221 | } else if (cpu_id == CPU_CORTEX_A15) { | |
222 | ncores = OMAP5_CORE_COUNT; | |
223 | } | |
367cd31e SS |
224 | |
225 | /* sanity check */ | |
a06f916b RK |
226 | if (ncores > nr_cpu_ids) { |
227 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
228 | ncores, nr_cpu_ids); | |
229 | ncores = nr_cpu_ids; | |
367cd31e | 230 | } |
367cd31e | 231 | |
bbc3d14e RK |
232 | for (i = 0; i < ncores; i++) |
233 | set_cpu_possible(i, true); | |
0f7b332f RK |
234 | |
235 | set_smp_cross_call(gic_raise_softirq); | |
bbc3d14e RK |
236 | } |
237 | ||
06915321 | 238 | static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) |
bbc3d14e | 239 | { |
367cd31e | 240 | |
05c74a6c RK |
241 | /* |
242 | * Initialise the SCU and wake up the secondary core using | |
243 | * wakeup_secondary(). | |
244 | */ | |
283f708c SS |
245 | if (scu_base) |
246 | scu_enable(scu_base); | |
05c74a6c | 247 | wakeup_secondary(); |
367cd31e | 248 | } |
06915321 MZ |
249 | |
250 | struct smp_operations omap4_smp_ops __initdata = { | |
251 | .smp_init_cpus = omap4_smp_init_cpus, | |
252 | .smp_prepare_cpus = omap4_smp_prepare_cpus, | |
253 | .smp_secondary_init = omap4_secondary_init, | |
254 | .smp_boot_secondary = omap4_boot_secondary, | |
255 | #ifdef CONFIG_HOTPLUG_CPU | |
256 | .cpu_die = omap4_cpu_die, | |
257 | #endif | |
258 | }; |