Commit | Line | Data |
---|---|---|
367cd31e SS |
1 | /* |
2 | * OMAP4 SMP source file. It contains platform specific fucntions | |
3 | * needed for the linux smp kernel. | |
4 | * | |
5 | * Copyright (C) 2009 Texas Instruments, Inc. | |
6 | * | |
7 | * Author: | |
8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
10 | * Platform file needed for the OMAP4 SMP. This file is based on arm | |
11 | * realview smp platform. | |
12 | * * Copyright (c) 2002 ARM Limited. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
367cd31e SS |
20 | #include <linux/smp.h> |
21 | #include <linux/io.h> | |
22 | ||
942e2c9e | 23 | #include <asm/cacheflush.h> |
0f7b332f | 24 | #include <asm/hardware/gic.h> |
367cd31e SS |
25 | #include <asm/smp_scu.h> |
26 | #include <mach/hardware.h> | |
fbc9be10 | 27 | #include <mach/omap4-common.h> |
367cd31e | 28 | |
367cd31e | 29 | /* SCU base address */ |
e4e7a13a | 30 | static void __iomem *scu_base; |
367cd31e | 31 | |
367cd31e SS |
32 | static DEFINE_SPINLOCK(boot_lock); |
33 | ||
34 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
35 | { | |
367cd31e SS |
36 | /* |
37 | * If any interrupts are already enabled for the primary | |
38 | * core (e.g. timer irq), then they will not have been enabled | |
39 | * for us: do so | |
40 | */ | |
38489533 | 41 | gic_secondary_init(0); |
367cd31e SS |
42 | |
43 | /* | |
44 | * Synchronise with the boot thread. | |
45 | */ | |
46 | spin_lock(&boot_lock); | |
47 | spin_unlock(&boot_lock); | |
48 | } | |
49 | ||
50 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
51 | { | |
367cd31e SS |
52 | /* |
53 | * Set synchronisation state between this boot processor | |
54 | * and the secondary one | |
55 | */ | |
56 | spin_lock(&boot_lock); | |
57 | ||
58 | /* | |
942e2c9e | 59 | * Update the AuxCoreBoot0 with boot state for secondary core. |
367cd31e SS |
60 | * omap_secondary_startup() routine will hold the secondary core till |
61 | * the AuxCoreBoot1 register is updated with cpu state | |
62 | * A barrier is added to ensure that write buffer is drained | |
63 | */ | |
7d35b8d0 | 64 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
942e2c9e | 65 | flush_cache_all(); |
367cd31e | 66 | smp_wmb(); |
0f7b332f | 67 | gic_raise_softirq(cpumask_of(cpu), 1); |
367cd31e | 68 | |
367cd31e SS |
69 | /* |
70 | * Now the secondary core is starting up let it run its | |
71 | * calibrations, then wait for it to finish | |
72 | */ | |
73 | spin_unlock(&boot_lock); | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
78 | static void __init wakeup_secondary(void) | |
79 | { | |
80 | /* | |
81 | * Write the address of secondary startup routine into the | |
942e2c9e | 82 | * AuxCoreBoot1 where ROM code will jump and start executing |
367cd31e SS |
83 | * on secondary core once out of WFE |
84 | * A barrier is added to ensure that write buffer is drained | |
85 | */ | |
942e2c9e | 86 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
367cd31e SS |
87 | smp_wmb(); |
88 | ||
89 | /* | |
90 | * Send a 'sev' to wake the secondary core from WFE. | |
942e2c9e | 91 | * Drain the outstanding writes to memory |
367cd31e | 92 | */ |
a4192d32 | 93 | dsb_sev(); |
367cd31e SS |
94 | mb(); |
95 | } | |
96 | ||
97 | /* | |
98 | * Initialise the CPU possible map early - this describes the CPUs | |
99 | * which may be present or become present in the system. | |
100 | */ | |
101 | void __init smp_init_cpus(void) | |
102 | { | |
e4e7a13a TL |
103 | unsigned int i, ncores; |
104 | ||
4c3cf901 TL |
105 | /* |
106 | * Currently we can't call ioremap here because | |
107 | * SoC detection won't work until after init_early. | |
108 | */ | |
109 | scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); | |
e4e7a13a TL |
110 | BUG_ON(!scu_base); |
111 | ||
fd778f0a | 112 | ncores = scu_get_core_count(scu_base); |
367cd31e SS |
113 | |
114 | /* sanity check */ | |
a06f916b RK |
115 | if (ncores > nr_cpu_ids) { |
116 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
117 | ncores, nr_cpu_ids); | |
118 | ncores = nr_cpu_ids; | |
367cd31e | 119 | } |
367cd31e | 120 | |
bbc3d14e RK |
121 | for (i = 0; i < ncores; i++) |
122 | set_cpu_possible(i, true); | |
0f7b332f RK |
123 | |
124 | set_smp_cross_call(gic_raise_softirq); | |
bbc3d14e RK |
125 | } |
126 | ||
05c74a6c | 127 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
bbc3d14e | 128 | { |
367cd31e | 129 | |
05c74a6c RK |
130 | /* |
131 | * Initialise the SCU and wake up the secondary core using | |
132 | * wakeup_secondary(). | |
133 | */ | |
134 | scu_enable(scu_base); | |
135 | wakeup_secondary(); | |
367cd31e | 136 | } |