Commit | Line | Data |
---|---|---|
4a79acdc | 1 | /* |
4a79acdc PW |
2 | * This file contains the processor specific definitions of the TI OMAP34XX. |
3 | * | |
4 | * Copyright (C) 2007 Texas Instruments. | |
5 | * Copyright (C) 2007 Nokia Corporation. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
a8eb7ca0 TL |
22 | #ifndef __ASM_ARCH_OMAP3_H |
23 | #define __ASM_ARCH_OMAP3_H | |
4a79acdc PW |
24 | |
25 | /* | |
26 | * Please place only base defines here and put the rest in device | |
27 | * specific headers. | |
28 | */ | |
29 | ||
30 | #define L4_34XX_BASE 0x48000000 | |
31 | #define L4_WK_34XX_BASE 0x48300000 | |
4a79acdc | 32 | #define L4_PER_34XX_BASE 0x49000000 |
4a79acdc | 33 | #define L4_EMU_34XX_BASE 0x54000000 |
4a79acdc | 34 | #define L3_34XX_BASE 0x68000000 |
4a79acdc | 35 | |
1e6cb146 AM |
36 | #define L4_WK_AM33XX_BASE 0x44C00000 |
37 | ||
4a79acdc PW |
38 | #define OMAP3430_32KSYNCT_BASE 0x48320000 |
39 | #define OMAP3430_CM_BASE 0x48004800 | |
40 | #define OMAP3430_PRM_BASE 0x48306800 | |
41 | #define OMAP343X_SMS_BASE 0x6C000000 | |
42 | #define OMAP343X_SDRC_BASE 0x6D000000 | |
43 | #define OMAP34XX_GPMC_BASE 0x6E000000 | |
44 | #define OMAP343X_SCM_BASE 0x48002000 | |
45 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE | |
46 | ||
47 | #define OMAP34XX_IC_BASE 0x48200000 | |
828c707e TL |
48 | |
49 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) | |
50 | #define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) | |
51 | #define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) | |
52 | #define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) | |
53 | #define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) | |
54 | #define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) | |
55 | #define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) | |
56 | #define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) | |
57 | #define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) | |
58 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) | |
6817a69a TT |
59 | #define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800) |
60 | #define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970) | |
61 | #define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0) | |
62 | #define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00) | |
63 | #define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70) | |
64 | #define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0) | |
828c707e TL |
65 | |
66 | #define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) | |
67 | #define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) | |
68 | #define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) | |
69 | #define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) | |
70 | #define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) | |
71 | #define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) | |
72 | #define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) | |
73 | #define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) | |
74 | #define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) | |
75 | #define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) | |
6817a69a TT |
76 | #define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F) |
77 | #define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B) | |
78 | #define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F) | |
79 | #define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F) | |
80 | #define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B) | |
81 | #define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F) | |
828c707e | 82 | |
4a79acdc | 83 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) |
4a79acdc | 84 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) |
58a5491c FB |
85 | #define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000) |
86 | #define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400) | |
87 | #define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800) | |
88 | #define OMAP34XX_SR1_BASE 0x480C9000 | |
89 | #define OMAP34XX_SR2_BASE 0x480CB000 | |
4a79acdc | 90 | |
9e495834 | 91 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) |
4a79acdc | 92 | |
ee5500c4 DK |
93 | /* Security */ |
94 | #define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000) | |
95 | #define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) | |
96 | #define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) | |
97 | ||
a8eb7ca0 | 98 | #endif /* __ASM_ARCH_OMAP3_H */ |
4a79acdc | 99 |