projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a79acdc | 1 | /* |
| 4a79acdc PW |
2 | * This file contains the processor specific definitions of the TI OMAP34XX. |
| 3 | * | |
| 4 | * Copyright (C) 2007 Texas Instruments. | |
| 5 | * Copyright (C) 2007 Nokia Corporation. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; either version 2 of the License, or | |
| 10 | * (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 20 | */ | |
| 21 | ||
| a8eb7ca0 TL |
22 | #ifndef __ASM_ARCH_OMAP3_H |
| 23 | #define __ASM_ARCH_OMAP3_H | |
| 4a79acdc PW |
24 | |
| 25 | /* | |
| 26 | * Please place only base defines here and put the rest in device | |
| 27 | * specific headers. | |
| 28 | */ | |
| 29 | ||
| 30 | #define L4_34XX_BASE 0x48000000 | |
| 31 | #define L4_WK_34XX_BASE 0x48300000 | |
| 4a79acdc | 32 | #define L4_PER_34XX_BASE 0x49000000 |
| 4a79acdc | 33 | #define L4_EMU_34XX_BASE 0x54000000 |
| 4a79acdc | 34 | #define L3_34XX_BASE 0x68000000 |
| 4a79acdc | 35 | |
| 1e6cb146 AM |
36 | #define L4_WK_AM33XX_BASE 0x44C00000 |
| 37 | ||
| 4a79acdc PW |
38 | #define OMAP3430_32KSYNCT_BASE 0x48320000 |
| 39 | #define OMAP3430_CM_BASE 0x48004800 | |
| 40 | #define OMAP3430_PRM_BASE 0x48306800 | |
| 41 | #define OMAP343X_SMS_BASE 0x6C000000 | |
| 42 | #define OMAP343X_SDRC_BASE 0x6D000000 | |
| 43 | #define OMAP34XX_GPMC_BASE 0x6E000000 | |
| 44 | #define OMAP343X_SCM_BASE 0x48002000 | |
| 45 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE | |
| 46 | ||
| 47 | #define OMAP34XX_IC_BASE 0x48200000 | |
| 828c707e | 48 | |
| 8644cdf9 SA |
49 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) |
| 50 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) | |
| 51 | #define OMAP3430_ISP_BASE2 (OMAP3430_ISP_BASE + 0x1800) | |
| 828c707e | 52 | |
| 4a79acdc | 53 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) |
| 4a79acdc | 54 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) |
| 58a5491c FB |
55 | #define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000) |
| 56 | #define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400) | |
| 57 | #define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800) | |
| 58 | #define OMAP34XX_SR1_BASE 0x480C9000 | |
| 59 | #define OMAP34XX_SR2_BASE 0x480CB000 | |
| 4a79acdc | 60 | |
| 9e495834 | 61 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) |
| 4a79acdc | 62 | |
| ee5500c4 DK |
63 | /* Security */ |
| 64 | #define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000) | |
| 65 | #define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000) | |
| 66 | #define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000) | |
| 67 | ||
| a8eb7ca0 | 68 | #endif /* __ASM_ARCH_OMAP3_H */ |
| 4a79acdc | 69 |