[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_address.h>

#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <asm/smp_twd.h>

#include "omap-wakeupgen.h"
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "mmc.h"
#include "hsmmc.h"
#include "prminst44xx.h"
#include "prcm_mpu44xx.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"
#include "sram.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;
static void __iomem *gic_dist_base_addr;
static void __iomem *twd_base;

#define IRQ_LOCALTIMER		29

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void __init gic_init_irq(void)
{
	void __iomem *omap_irq_base;

	/* Static mapping, never released */
	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	BUG_ON(!gic_dist_base_addr);

	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
	BUG_ON(!twd_base);

	/* Static mapping, never released */
	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
	BUG_ON(!omap_irq_base);

	omap_wakeupgen_init();

	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}

void gic_dist_disable(void)
{
	if (gic_dist_base_addr)
		__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}

bool gic_dist_disabled(void)
{
	return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}

void gic_timer_retrigger(void)
{
	u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
	u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);

	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
		/*
		 * The local timer interrupt got lost while the distributor was
		 * disabled.  Ack the pending interrupt, and retrigger it.
		 */
		pr_warn("%s: lost localtimer interrupt\n", __func__);
		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
			__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
			__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
		}
	}
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2x0_disable(void)
{
	/* Disable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x0);
}

static void omap4_l2x0_set_debug(unsigned long val)
{
	/* Program PL310 L2 Cache controller debug register */
	omap_smc1(0x100, val);
}

static int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl = 0;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/*
	 * 16-way associativity, parity disabled
	 * Way size - 32KB (es1.0)
	 * Way size - 64KB (es2.0 +)
	 */
	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
			(0x1 << 25) |
			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
	} else {
		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
	}
	if (omap_rev() != OMAP4430_REV_ES1_0)
		omap_smc1(0x109, aux_ctrl);

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	if (of_have_populated_dt())
		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	else
		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);

	/*
	 * Override default outer_cache.disable with a OMAP4
	 * specific one
	*/
	outer_cache.disable = omap4_l2x0_disable;
	outer_cache.set_debug = omap4_l2x0_set_debug;

	return 0;
}
omap_early_initcall(omap_l2_cache_init);
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	unsigned long sar_base;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (cpu_is_omap44xx())
		sar_base = OMAP44XX_SAR_RAM_BASE;
	else if (soc_is_omap54xx())
		sar_base = OMAP54XX_SAR_RAM_BASE;
	else
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(sar_base, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
omap_early_initcall(omap4_sar_ram_init);

void __init omap_gic_of_init(void)
{
	struct device_node *np;

	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	if (!cpu_is_omap446x())
		goto skip_errata_init;

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	gic_dist_base_addr = of_iomap(np, 0);
	WARN_ON(!gic_dist_base_addr);

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	twd_base = of_iomap(np, 0);
	WARN_ON(!twd_base);

skip_errata_init:
	omap_wakeupgen_init();
	irqchip_init();
}

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
	int irq = 0;
	struct platform_device *pdev = container_of(dev,
				struct platform_device, dev);
	struct omap_mmc_platform_data *pdata = dev->platform_data;

	/* Setting MMC1 Card detect Irq */
	if (pdev->id == 0) {
		irq = twl6030_mmc_card_detect_config();
		if (irq < 0) {
			dev_err(dev, "%s: Error card detect config(%d)\n",
				__func__, irq);
			return irq;
		}
		pdata->slots[0].card_detect_irq = irq;
		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	}
	return 0;
}

static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
{
	struct omap_mmc_platform_data *pdata;

	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	if (!dev) {
		pr_err("Failed %s\n", __func__);
		return;
	}
	pdata = dev->platform_data;
	pdata->init =	omap4_twl6030_hsmmc_late_init;
}

int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;

	omap_hsmmc_init(controllers);
	for (c = controllers; c->mmc; c++) {
		/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
		if (!c->pdev)
			continue;
		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	}

	return 0;
}
#else
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	return 0;
}
#endif

/**
 * omap44xx_restart - trigger a software restart of the SoC
 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
 * @cmd: passed from the userspace program rebooting the system (if provided)
 *
 * Resets the SoC.  For @cmd, see the 'reboot' syscall in
 * kernel/sys.c.  No return value.
 */
void omap44xx_restart(char mode, const char *cmd)
{
	/* XXX Should save 'cmd' into scratchpad for use after reboot */
	omap4_prminst_global_warm_sw_reset(); /* never returns */
	while (1);
}
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
cd8ce159	17	#include <linux/irq.h>
0529e315	18	#include <linux/irqchip.h>
fbc9be10	19	#include <linux/platform_device.h>
137d105d	20	#include <linux/memblock.h>
7d7e1eba TL	21	#include <linux/of_irq.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/export.h>
520f7bd7	24	#include <linux/irqchip/arm-gic.h>
fd1c0786	25	#include <linux/of_address.h>
fbc9be10	26
fbc9be10	27	#include <asm/hardware/cache-l2x0.h>
137d105d	28	#include <asm/mach/map.h>
716a3dc2	29	#include <asm/memblock.h>
cd8ce159	30	#include <asm/smp_twd.h>
fbc9be10	31
732231a7	32	#include "omap-wakeupgen.h"
dbc04161	33	#include "soc.h"
b6a4226c	34	#include "iomap.h"
4e65331c	35	#include "common.h"
68f39e74	36	#include "mmc.h"
1ee47b0a	37	#include "hsmmc.h"
2f334a38	38	#include "prminst44xx.h"
d9a16f9a	39	#include "prcm_mpu44xx.h"
501f0c75	40	#include "omap4-sar-layout.h"
f7a9b8a1	41	#include "omap-secure.h"
bb772094	42	#include "sram.h"
fbc9be10 SS	43
fbc9be10 SS	44	#ifdef CONFIG_CACHE_L2X0
02afe8a7	45	static void __iomem *l2cache_base;
fbc9be10 SS	46	#endif
fbc9be10 SS	47
501f0c75	48	static void __iomem *sar_ram_base;
ff999b8a	49	static void __iomem *gic_dist_base_addr;
cd8ce159 CC	50	static void __iomem *twd_base;
	51
	52	#define IRQ_LOCALTIMER 29
501f0c75	53
137d105d SS	54	#ifdef CONFIG_OMAP4_ERRATA_I688
	55	/* Used to implement memory barrier on DRAM path */
	56	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	57
	58	void __iomem dram_sync, sram_sync;
	59
2ec1fc4e SS	60	static phys_addr_t paddr;
	61	static u32 size;
	62
137d105d SS	63	void omap_bus_sync(void)
	64	{
	65	if (dram_sync && sram_sync) {
	66	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	67	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	68	isb();
	69	}
	70	}
cc4ad907	71	EXPORT_SYMBOL(omap_bus_sync);
137d105d	72
2ec1fc4e SS	73	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	74	int __init omap_barrier_reserve_memblock(void)
137d105d	75	{
137d105d SS	76
137d105d SS	77	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	78	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	79
2ec1fc4e SS	80	return 0;
	81	}
	82
	83	void __init omap_barriers_init(void)
	84	{
	85	struct map_desc dram_io_desc[1];
	86
137d105d SS	87	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	88	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	89	dram_io_desc[0].length = size;
	90	dram_io_desc[0].type = MT_MEMORY_SO;
	91	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	92	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	93	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	94
	95	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	96	(long long) paddr, dram_io_desc[0].virtual);
	97
137d105d	98	}
2ec1fc4e SS	99	#else
	100	void __init omap_barriers_init(void)
	101	{}
137d105d SS	102	#endif
137d105d SS	103
fbc9be10 SS	104	void __init gic_init_irq(void)
fbc9be10 SS	105	{
ab65be26	106	void __iomem *omap_irq_base;
ab65be26	107
fbc9be10 SS	108	/* Static mapping, never released */
	109	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	110	BUG_ON(!gic_dist_base_addr);
fbc9be10	111
cd8ce159 CC	112	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
	113	BUG_ON(!twd_base);
	114
fbc9be10	115	/* Static mapping, never released */
741e3a89 TL	116	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
741e3a89 TL	117	BUG_ON(!omap_irq_base);
b580b899	118
fcf6efa3 SS	119	omap_wakeupgen_init();
fcf6efa3 SS	120
741e3a89	121	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
fbc9be10 SS	122	}
fbc9be10 SS	123
ff999b8a SS	124	void gic_dist_disable(void)
	125	{
	126	if (gic_dist_base_addr)
	127	__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
	128	}
	129
cd8ce159 CC	130	bool gic_dist_disabled(void)
	131	{
	132	return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
	133	}
	134
	135	void gic_timer_retrigger(void)
	136	{
	137	u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
	138	u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	139	u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
	140
	141	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
	142	/*
	143	* The local timer interrupt got lost while the distributor was
	144	* disabled. Ack the pending interrupt, and retrigger it.
	145	*/
	146	pr_warn("%s: lost localtimer interrupt\n", __func__);
	147	__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
	148	if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
	149	__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
	150	twd_ctrl \|= TWD_TIMER_CONTROL_ENABLE;
	151	__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
	152	}
	153	}
	154	}
	155
fbc9be10	156	#ifdef CONFIG_CACHE_L2X0
4e803c40	157
02afe8a7 SS	158	void __iomem *omap4_get_l2cache_base(void)
	159	{
	160	return l2cache_base;
	161	}
	162
4e803c40 SS	163	static void omap4_l2x0_disable(void)
	164	{
	165	/* Disable PL310 L2 Cache controller */
	166	omap_smc1(0x102, 0x0);
	167	}
	168
4bdb1577 SS	169	static void omap4_l2x0_set_debug(unsigned long val)
	170	{
	171	/* Program PL310 L2 Cache controller debug register */
	172	omap_smc1(0x100, val);
	173	}
	174
fbc9be10 SS	175	static int __init omap_l2_cache_init(void)
fbc9be10 SS	176	{
1773e60a SS	177	u32 aux_ctrl = 0;
1773e60a SS	178
fbc9be10 SS	179	/*
	180	* To avoid code running on other OMAPs in
	181	* multi-omap builds
	182	*/
	183	if (!cpu_is_omap44xx())
	184	return -ENODEV;
	185
	186	/* Static mapping, never released */
	187	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	188	if (WARN_ON(!l2cache_base))
0db1803e SS	189	return -ENOMEM;
fbc9be10	190
fbc9be10	191	/*
a777b727 SS	192	* 16-way associativity, parity disabled
	193	* Way size - 32KB (es1.0)
	194	* Way size - 64KB (es2.0 +)
fbc9be10	195	*/
1773e60a SS	196	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
	197	(0x1 << 25) \|
	198	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
	199	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
	200
11e02640	201	if (omap_rev() == OMAP4430_REV_ES1_0) {
1773e60a	202	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
11e02640 MR	203	} else {
11e02640 MR	204	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
b0f20ff9	205	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
11e02640	206	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
b89cd71a SS	207	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
b89cd71a SS	208	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
11e02640 MR	209	}
	210	if (omap_rev() != OMAP4430_REV_ES1_0)
	211	omap_smc1(0x109, aux_ctrl);
	212
	213	/* Enable PL310 L2 Cache controller */
	214	omap_smc1(0x102, 0x1);
1773e60a	215
926fd45b SS	216	if (of_have_populated_dt())
	217	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	218	else
	219	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
fbc9be10	220
4e803c40 SS	221	/*
	222	* Override default outer_cache.disable with a OMAP4
	223	* specific one
	224	*/
	225	outer_cache.disable = omap4_l2x0_disable;
4bdb1577	226	outer_cache.set_debug = omap4_l2x0_set_debug;
4e803c40	227
fbc9be10 SS	228	return 0;
fbc9be10 SS	229	}
b76c8b19	230	omap_early_initcall(omap_l2_cache_init);
fbc9be10	231	#endif
501f0c75 SS	232
	233	void __iomem *omap4_get_sar_ram_base(void)
	234	{
	235	return sar_ram_base;
	236	}
	237
	238	/*
	239	* SAR RAM used to save and restore the HW
	240	* context in low power modes
	241	*/
	242	static int __init omap4_sar_ram_init(void)
	243	{
da0e02a1 SS	244	unsigned long sar_base;
da0e02a1 SS	245
501f0c75 SS	246	/*
	247	* To avoid code running on other OMAPs in
	248	* multi-omap builds
	249	*/
da0e02a1 SS	250	if (cpu_is_omap44xx())
	251	sar_base = OMAP44XX_SAR_RAM_BASE;
	252	else if (soc_is_omap54xx())
	253	sar_base = OMAP54XX_SAR_RAM_BASE;
	254	else
501f0c75 SS	255	return -ENOMEM;
	256
	257	/* Static mapping, never released */
da0e02a1	258	sar_ram_base = ioremap(sar_base, SZ_16K);
501f0c75 SS	259	if (WARN_ON(!sar_ram_base))
	260	return -ENOMEM;
	261
	262	return 0;
	263	}
b76c8b19	264	omap_early_initcall(omap4_sar_ram_init);
1ee47b0a	265
c4082d49 S	266	void __init omap_gic_of_init(void)
c4082d49 S	267	{
fd1c0786 SS	268	struct device_node *np;
	269
	270	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	271	if (!cpu_is_omap446x())
	272	goto skip_errata_init;
	273
	274	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	275	gic_dist_base_addr = of_iomap(np, 0);
	276	WARN_ON(!gic_dist_base_addr);
	277
	278	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	279	twd_base = of_iomap(np, 0);
	280	WARN_ON(!twd_base);
	281
	282	skip_errata_init:
c4082d49	283	omap_wakeupgen_init();
0529e315	284	irqchip_init();
c4082d49 S	285	}
c4082d49 S	286
1ee47b0a B	287	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
	288	static int omap4_twl6030_hsmmc_late_init(struct device *dev)
	289	{
	290	int irq = 0;
	291	struct platform_device *pdev = container_of(dev,
	292	struct platform_device, dev);
	293	struct omap_mmc_platform_data *pdata = dev->platform_data;
	294
	295	/* Setting MMC1 Card detect Irq */
	296	if (pdev->id == 0) {
	297	irq = twl6030_mmc_card_detect_config();
	298	if (irq < 0) {
	299	dev_err(dev, "%s: Error card detect config(%d)\n",
	300	__func__, irq);
	301	return irq;
	302	}
	303	pdata->slots[0].card_detect_irq = irq;
	304	pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	305	}
	306	return 0;
	307	}
	308
	309	static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
	310	{
	311	struct omap_mmc_platform_data *pdata;
	312
	313	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	314	if (!dev) {
	315	pr_err("Failed %s\n", __func__);
	316	return;
	317	}
	318	pdata = dev->platform_data;
	319	pdata->init = omap4_twl6030_hsmmc_late_init;
	320	}
	321
	322	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	323	{
	324	struct omap2_hsmmc_info *c;
	325
	326	omap_hsmmc_init(controllers);
	327	for (c = controllers; c->mmc; c++) {
	328	/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
	329	if (!c->pdev)
	330	continue;
	331	omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	332	}
	333
	334	return 0;
	335	}
	336	#else
	337	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	338	{
	339	return 0;
	340	}
	341	#endif
2f334a38 PW	342
	343	/**
	344	* omap44xx_restart - trigger a software restart of the SoC
	345	* @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
	346	* @cmd: passed from the userspace program rebooting the system (if provided)
	347	*
	348	* Resets the SoC. For @cmd, see the 'reboot' syscall in
	349	* kernel/sys.c. No return value.
	350	*/
	351	void omap44xx_restart(char mode, const char *cmd)
	352	{
	353	/* XXX Should save 'cmd' into scratchpad for use after reboot */
	354	omap4_prminst_global_warm_sw_reset(); /* never returns */
	355	while (1);
	356	}
	357