Commit | Line | Data |
---|---|---|
fbc9be10 SS |
1 | /* |
2 | * OMAP4 specific common source file. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Author: | |
6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
7 | * | |
8 | * | |
9 | * This program is free software,you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
cd8ce159 | 17 | #include <linux/irq.h> |
fbc9be10 | 18 | #include <linux/platform_device.h> |
137d105d | 19 | #include <linux/memblock.h> |
7d7e1eba TL |
20 | #include <linux/of_irq.h> |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/export.h> | |
fbc9be10 SS |
23 | |
24 | #include <asm/hardware/gic.h> | |
25 | #include <asm/hardware/cache-l2x0.h> | |
137d105d | 26 | #include <asm/mach/map.h> |
716a3dc2 | 27 | #include <asm/memblock.h> |
cd8ce159 | 28 | #include <asm/smp_twd.h> |
fbc9be10 | 29 | |
732231a7 | 30 | #include "omap-wakeupgen.h" |
dbc04161 | 31 | #include "soc.h" |
b6a4226c | 32 | #include "iomap.h" |
4e65331c | 33 | #include "common.h" |
68f39e74 | 34 | #include "mmc.h" |
1ee47b0a | 35 | #include "hsmmc.h" |
2f334a38 | 36 | #include "prminst44xx.h" |
d9a16f9a | 37 | #include "prcm_mpu44xx.h" |
501f0c75 | 38 | #include "omap4-sar-layout.h" |
f7a9b8a1 | 39 | #include "omap-secure.h" |
bb772094 | 40 | #include "sram.h" |
fbc9be10 SS |
41 | |
42 | #ifdef CONFIG_CACHE_L2X0 | |
02afe8a7 | 43 | static void __iomem *l2cache_base; |
fbc9be10 SS |
44 | #endif |
45 | ||
501f0c75 | 46 | static void __iomem *sar_ram_base; |
ff999b8a | 47 | static void __iomem *gic_dist_base_addr; |
cd8ce159 CC |
48 | static void __iomem *twd_base; |
49 | ||
50 | #define IRQ_LOCALTIMER 29 | |
501f0c75 | 51 | |
137d105d SS |
52 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
53 | /* Used to implement memory barrier on DRAM path */ | |
54 | #define OMAP4_DRAM_BARRIER_VA 0xfe600000 | |
55 | ||
56 | void __iomem *dram_sync, *sram_sync; | |
57 | ||
2ec1fc4e SS |
58 | static phys_addr_t paddr; |
59 | static u32 size; | |
60 | ||
137d105d SS |
61 | void omap_bus_sync(void) |
62 | { | |
63 | if (dram_sync && sram_sync) { | |
64 | writel_relaxed(readl_relaxed(dram_sync), dram_sync); | |
65 | writel_relaxed(readl_relaxed(sram_sync), sram_sync); | |
66 | isb(); | |
67 | } | |
68 | } | |
cc4ad907 | 69 | EXPORT_SYMBOL(omap_bus_sync); |
137d105d | 70 | |
2ec1fc4e SS |
71 | /* Steal one page physical memory for barrier implementation */ |
72 | int __init omap_barrier_reserve_memblock(void) | |
137d105d | 73 | { |
137d105d SS |
74 | |
75 | size = ALIGN(PAGE_SIZE, SZ_1M); | |
716a3dc2 RK |
76 | paddr = arm_memblock_steal(size, SZ_1M); |
77 | ||
2ec1fc4e SS |
78 | return 0; |
79 | } | |
80 | ||
81 | void __init omap_barriers_init(void) | |
82 | { | |
83 | struct map_desc dram_io_desc[1]; | |
84 | ||
137d105d SS |
85 | dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; |
86 | dram_io_desc[0].pfn = __phys_to_pfn(paddr); | |
87 | dram_io_desc[0].length = size; | |
88 | dram_io_desc[0].type = MT_MEMORY_SO; | |
89 | iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); | |
90 | dram_sync = (void __iomem *) dram_io_desc[0].virtual; | |
91 | sram_sync = (void __iomem *) OMAP4_SRAM_VA; | |
92 | ||
93 | pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", | |
94 | (long long) paddr, dram_io_desc[0].virtual); | |
95 | ||
137d105d | 96 | } |
2ec1fc4e SS |
97 | #else |
98 | void __init omap_barriers_init(void) | |
99 | {} | |
137d105d SS |
100 | #endif |
101 | ||
fbc9be10 SS |
102 | void __init gic_init_irq(void) |
103 | { | |
ab65be26 | 104 | void __iomem *omap_irq_base; |
ab65be26 | 105 | |
fbc9be10 SS |
106 | /* Static mapping, never released */ |
107 | gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); | |
108 | BUG_ON(!gic_dist_base_addr); | |
fbc9be10 | 109 | |
cd8ce159 CC |
110 | twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K); |
111 | BUG_ON(!twd_base); | |
112 | ||
fbc9be10 | 113 | /* Static mapping, never released */ |
741e3a89 TL |
114 | omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); |
115 | BUG_ON(!omap_irq_base); | |
b580b899 | 116 | |
fcf6efa3 SS |
117 | omap_wakeupgen_init(); |
118 | ||
741e3a89 | 119 | gic_init(0, 29, gic_dist_base_addr, omap_irq_base); |
fbc9be10 SS |
120 | } |
121 | ||
ff999b8a SS |
122 | void gic_dist_disable(void) |
123 | { | |
124 | if (gic_dist_base_addr) | |
125 | __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL); | |
126 | } | |
127 | ||
cd8ce159 CC |
128 | bool gic_dist_disabled(void) |
129 | { | |
130 | return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); | |
131 | } | |
132 | ||
133 | void gic_timer_retrigger(void) | |
134 | { | |
135 | u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT); | |
136 | u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET); | |
137 | u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); | |
138 | ||
139 | if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { | |
140 | /* | |
141 | * The local timer interrupt got lost while the distributor was | |
142 | * disabled. Ack the pending interrupt, and retrigger it. | |
143 | */ | |
144 | pr_warn("%s: lost localtimer interrupt\n", __func__); | |
145 | __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); | |
146 | if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { | |
147 | __raw_writel(1, twd_base + TWD_TIMER_COUNTER); | |
148 | twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; | |
149 | __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL); | |
150 | } | |
151 | } | |
152 | } | |
153 | ||
fbc9be10 | 154 | #ifdef CONFIG_CACHE_L2X0 |
4e803c40 | 155 | |
02afe8a7 SS |
156 | void __iomem *omap4_get_l2cache_base(void) |
157 | { | |
158 | return l2cache_base; | |
159 | } | |
160 | ||
4e803c40 SS |
161 | static void omap4_l2x0_disable(void) |
162 | { | |
163 | /* Disable PL310 L2 Cache controller */ | |
164 | omap_smc1(0x102, 0x0); | |
165 | } | |
166 | ||
4bdb1577 SS |
167 | static void omap4_l2x0_set_debug(unsigned long val) |
168 | { | |
169 | /* Program PL310 L2 Cache controller debug register */ | |
170 | omap_smc1(0x100, val); | |
171 | } | |
172 | ||
fbc9be10 SS |
173 | static int __init omap_l2_cache_init(void) |
174 | { | |
1773e60a SS |
175 | u32 aux_ctrl = 0; |
176 | ||
fbc9be10 SS |
177 | /* |
178 | * To avoid code running on other OMAPs in | |
179 | * multi-omap builds | |
180 | */ | |
181 | if (!cpu_is_omap44xx()) | |
182 | return -ENODEV; | |
183 | ||
184 | /* Static mapping, never released */ | |
185 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | |
0db1803e SS |
186 | if (WARN_ON(!l2cache_base)) |
187 | return -ENOMEM; | |
fbc9be10 | 188 | |
fbc9be10 | 189 | /* |
a777b727 SS |
190 | * 16-way associativity, parity disabled |
191 | * Way size - 32KB (es1.0) | |
192 | * Way size - 64KB (es2.0 +) | |
fbc9be10 | 193 | */ |
1773e60a SS |
194 | aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | |
195 | (0x1 << 25) | | |
196 | (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | | |
197 | (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); | |
198 | ||
11e02640 | 199 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
1773e60a | 200 | aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; |
11e02640 MR |
201 | } else { |
202 | aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | | |
b0f20ff9 | 203 | (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | |
11e02640 | 204 | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | |
b89cd71a SS |
205 | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | |
206 | (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); | |
11e02640 MR |
207 | } |
208 | if (omap_rev() != OMAP4430_REV_ES1_0) | |
209 | omap_smc1(0x109, aux_ctrl); | |
210 | ||
211 | /* Enable PL310 L2 Cache controller */ | |
212 | omap_smc1(0x102, 0x1); | |
1773e60a | 213 | |
926fd45b SS |
214 | if (of_have_populated_dt()) |
215 | l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); | |
216 | else | |
217 | l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); | |
fbc9be10 | 218 | |
4e803c40 SS |
219 | /* |
220 | * Override default outer_cache.disable with a OMAP4 | |
221 | * specific one | |
222 | */ | |
223 | outer_cache.disable = omap4_l2x0_disable; | |
4bdb1577 | 224 | outer_cache.set_debug = omap4_l2x0_set_debug; |
4e803c40 | 225 | |
fbc9be10 SS |
226 | return 0; |
227 | } | |
228 | early_initcall(omap_l2_cache_init); | |
229 | #endif | |
501f0c75 SS |
230 | |
231 | void __iomem *omap4_get_sar_ram_base(void) | |
232 | { | |
233 | return sar_ram_base; | |
234 | } | |
235 | ||
236 | /* | |
237 | * SAR RAM used to save and restore the HW | |
238 | * context in low power modes | |
239 | */ | |
240 | static int __init omap4_sar_ram_init(void) | |
241 | { | |
242 | /* | |
243 | * To avoid code running on other OMAPs in | |
244 | * multi-omap builds | |
245 | */ | |
246 | if (!cpu_is_omap44xx()) | |
247 | return -ENOMEM; | |
248 | ||
249 | /* Static mapping, never released */ | |
250 | sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); | |
251 | if (WARN_ON(!sar_ram_base)) | |
252 | return -ENOMEM; | |
253 | ||
254 | return 0; | |
255 | } | |
256 | early_initcall(omap4_sar_ram_init); | |
1ee47b0a | 257 | |
c4082d49 S |
258 | static struct of_device_id irq_match[] __initdata = { |
259 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, | |
0c1b6fac | 260 | { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, }, |
c4082d49 S |
261 | { } |
262 | }; | |
263 | ||
264 | void __init omap_gic_of_init(void) | |
265 | { | |
266 | omap_wakeupgen_init(); | |
267 | of_irq_init(irq_match); | |
268 | } | |
269 | ||
1ee47b0a B |
270 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) |
271 | static int omap4_twl6030_hsmmc_late_init(struct device *dev) | |
272 | { | |
273 | int irq = 0; | |
274 | struct platform_device *pdev = container_of(dev, | |
275 | struct platform_device, dev); | |
276 | struct omap_mmc_platform_data *pdata = dev->platform_data; | |
277 | ||
278 | /* Setting MMC1 Card detect Irq */ | |
279 | if (pdev->id == 0) { | |
280 | irq = twl6030_mmc_card_detect_config(); | |
281 | if (irq < 0) { | |
282 | dev_err(dev, "%s: Error card detect config(%d)\n", | |
283 | __func__, irq); | |
284 | return irq; | |
285 | } | |
286 | pdata->slots[0].card_detect_irq = irq; | |
287 | pdata->slots[0].card_detect = twl6030_mmc_card_detect; | |
288 | } | |
289 | return 0; | |
290 | } | |
291 | ||
292 | static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) | |
293 | { | |
294 | struct omap_mmc_platform_data *pdata; | |
295 | ||
296 | /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ | |
297 | if (!dev) { | |
298 | pr_err("Failed %s\n", __func__); | |
299 | return; | |
300 | } | |
301 | pdata = dev->platform_data; | |
302 | pdata->init = omap4_twl6030_hsmmc_late_init; | |
303 | } | |
304 | ||
305 | int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) | |
306 | { | |
307 | struct omap2_hsmmc_info *c; | |
308 | ||
309 | omap_hsmmc_init(controllers); | |
310 | for (c = controllers; c->mmc; c++) { | |
311 | /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */ | |
312 | if (!c->pdev) | |
313 | continue; | |
314 | omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); | |
315 | } | |
316 | ||
317 | return 0; | |
318 | } | |
319 | #else | |
320 | int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) | |
321 | { | |
322 | return 0; | |
323 | } | |
324 | #endif | |
2f334a38 PW |
325 | |
326 | /** | |
327 | * omap44xx_restart - trigger a software restart of the SoC | |
328 | * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c | |
329 | * @cmd: passed from the userspace program rebooting the system (if provided) | |
330 | * | |
331 | * Resets the SoC. For @cmd, see the 'reboot' syscall in | |
332 | * kernel/sys.c. No return value. | |
333 | */ | |
334 | void omap44xx_restart(char mode, const char *cmd) | |
335 | { | |
336 | /* XXX Should save 'cmd' into scratchpad for use after reboot */ | |
337 | omap4_prminst_global_warm_sw_reset(); /* never returns */ | |
338 | while (1); | |
339 | } | |
340 |