[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/irq-crossbar.h>
#include <linux/of_address.h>
#include <linux/reboot.h>

#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <asm/smp_twd.h>

#include "omap-wakeupgen.h"
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "mmc.h"
#include "prminst44xx.h"
#include "prcm_mpu44xx.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"
#include "sram.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;
static void __iomem *gic_dist_base_addr;
static void __iomem *twd_base;

#define IRQ_LOCALTIMER		29

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_RW_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void __init gic_init_irq(void)
{
	void __iomem *omap_irq_base;

	/* Static mapping, never released */
	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	BUG_ON(!gic_dist_base_addr);

	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
	BUG_ON(!twd_base);

	/* Static mapping, never released */
	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
	BUG_ON(!omap_irq_base);

	omap_wakeupgen_init();

	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}

void gic_dist_disable(void)
{
	if (gic_dist_base_addr)
		__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}

void gic_dist_enable(void)
{
	if (gic_dist_base_addr)
		__raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
}

bool gic_dist_disabled(void)
{
	return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}

void gic_timer_retrigger(void)
{
	u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
	u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);

	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
		/*
		 * The local timer interrupt got lost while the distributor was
		 * disabled.  Ack the pending interrupt, and retrigger it.
		 */
		pr_warn("%s: lost localtimer interrupt\n", __func__);
		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
			__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
			__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
		}
	}
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2x0_disable(void)
{
	outer_flush_all();
	/* Disable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x0);
}

static void omap4_l2x0_set_debug(unsigned long val)
{
	/* Program PL310 L2 Cache controller debug register */
	omap_smc1(0x100, val);
}

static int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl = 0;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/*
	 * 16-way associativity, parity disabled
	 * Way size - 32KB (es1.0)
	 * Way size - 64KB (es2.0 +)
	 */
	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
			(0x1 << 25) |
			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
	} else {
		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
	}
	if (omap_rev() != OMAP4430_REV_ES1_0)
		omap_smc1(0x109, aux_ctrl);

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	if (of_have_populated_dt())
		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	else
		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);

	/*
	 * Override default outer_cache.disable with a OMAP4
	 * specific one
	*/
	outer_cache.disable = omap4_l2x0_disable;
	outer_cache.set_debug = omap4_l2x0_set_debug;

	return 0;
}
omap_early_initcall(omap_l2_cache_init);
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	unsigned long sar_base;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (cpu_is_omap44xx())
		sar_base = OMAP44XX_SAR_RAM_BASE;
	else if (soc_is_omap54xx())
		sar_base = OMAP54XX_SAR_RAM_BASE;
	else
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(sar_base, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
omap_early_initcall(omap4_sar_ram_init);

void __init omap_gic_of_init(void)
{
	struct device_node *np;

	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	if (!cpu_is_omap446x())
		goto skip_errata_init;

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	gic_dist_base_addr = of_iomap(np, 0);
	WARN_ON(!gic_dist_base_addr);

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	twd_base = of_iomap(np, 0);
	WARN_ON(!twd_base);

skip_errata_init:
	omap_wakeupgen_init();
#ifdef CONFIG_IRQ_CROSSBAR
	irqcrossbar_init();
#endif
	irqchip_init();
}
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
cd8ce159	17	#include <linux/irq.h>
0529e315	18	#include <linux/irqchip.h>
fbc9be10	19	#include <linux/platform_device.h>
137d105d	20	#include <linux/memblock.h>
7d7e1eba TL	21	#include <linux/of_irq.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/export.h>
520f7bd7	24	#include <linux/irqchip/arm-gic.h>
5c61e619	25	#include <linux/irqchip/irq-crossbar.h>
fd1c0786	26	#include <linux/of_address.h>
7b6d864b	27	#include <linux/reboot.h>
fbc9be10	28
fbc9be10	29	#include <asm/hardware/cache-l2x0.h>
137d105d	30	#include <asm/mach/map.h>
716a3dc2	31	#include <asm/memblock.h>
cd8ce159	32	#include <asm/smp_twd.h>
fbc9be10	33
732231a7	34	#include "omap-wakeupgen.h"
dbc04161	35	#include "soc.h"
b6a4226c	36	#include "iomap.h"
4e65331c	37	#include "common.h"
68f39e74	38	#include "mmc.h"
2f334a38	39	#include "prminst44xx.h"
d9a16f9a	40	#include "prcm_mpu44xx.h"
501f0c75	41	#include "omap4-sar-layout.h"
f7a9b8a1	42	#include "omap-secure.h"
bb772094	43	#include "sram.h"
fbc9be10 SS	44
fbc9be10 SS	45	#ifdef CONFIG_CACHE_L2X0
02afe8a7	46	static void __iomem *l2cache_base;
fbc9be10 SS	47	#endif
fbc9be10 SS	48
501f0c75	49	static void __iomem *sar_ram_base;
ff999b8a	50	static void __iomem *gic_dist_base_addr;
cd8ce159 CC	51	static void __iomem *twd_base;
	52
	53	#define IRQ_LOCALTIMER 29
501f0c75	54
137d105d SS	55	#ifdef CONFIG_OMAP4_ERRATA_I688
	56	/* Used to implement memory barrier on DRAM path */
	57	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	58
	59	void __iomem dram_sync, sram_sync;
	60
2ec1fc4e SS	61	static phys_addr_t paddr;
	62	static u32 size;
	63
137d105d SS	64	void omap_bus_sync(void)
	65	{
	66	if (dram_sync && sram_sync) {
	67	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	68	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	69	isb();
	70	}
	71	}
cc4ad907	72	EXPORT_SYMBOL(omap_bus_sync);
137d105d	73
2ec1fc4e SS	74	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	75	int __init omap_barrier_reserve_memblock(void)
137d105d	76	{
137d105d SS	77
137d105d SS	78	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	79	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	80
2ec1fc4e SS	81	return 0;
	82	}
	83
	84	void __init omap_barriers_init(void)
	85	{
	86	struct map_desc dram_io_desc[1];
	87
137d105d SS	88	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	89	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	90	dram_io_desc[0].length = size;
2e2c9de2	91	dram_io_desc[0].type = MT_MEMORY_RW_SO;
137d105d SS	92	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	93	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	94	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	95
	96	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	97	(long long) paddr, dram_io_desc[0].virtual);
	98
137d105d	99	}
2ec1fc4e SS	100	#else
	101	void __init omap_barriers_init(void)
	102	{}
137d105d SS	103	#endif
137d105d SS	104
fbc9be10 SS	105	void __init gic_init_irq(void)
fbc9be10 SS	106	{
ab65be26	107	void __iomem *omap_irq_base;
ab65be26	108
fbc9be10 SS	109	/* Static mapping, never released */
	110	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	111	BUG_ON(!gic_dist_base_addr);
fbc9be10	112
cd8ce159 CC	113	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
	114	BUG_ON(!twd_base);
	115
fbc9be10	116	/* Static mapping, never released */
741e3a89 TL	117	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
741e3a89 TL	118	BUG_ON(!omap_irq_base);
b580b899	119
fcf6efa3 SS	120	omap_wakeupgen_init();
fcf6efa3 SS	121
741e3a89	122	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
fbc9be10 SS	123	}
fbc9be10 SS	124
ff999b8a SS	125	void gic_dist_disable(void)
	126	{
	127	if (gic_dist_base_addr)
	128	__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
	129	}
	130
74ed7bdc SG	131	void gic_dist_enable(void)
	132	{
	133	if (gic_dist_base_addr)
	134	__raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
	135	}
	136
cd8ce159 CC	137	bool gic_dist_disabled(void)
	138	{
	139	return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
	140	}
	141
	142	void gic_timer_retrigger(void)
	143	{
	144	u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
	145	u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	146	u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
	147
	148	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
	149	/*
	150	* The local timer interrupt got lost while the distributor was
	151	* disabled. Ack the pending interrupt, and retrigger it.
	152	*/
	153	pr_warn("%s: lost localtimer interrupt\n", __func__);
	154	__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
	155	if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
	156	__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
	157	twd_ctrl \|= TWD_TIMER_CONTROL_ENABLE;
	158	__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
	159	}
	160	}
	161	}
	162
fbc9be10	163	#ifdef CONFIG_CACHE_L2X0
4e803c40	164
02afe8a7 SS	165	void __iomem *omap4_get_l2cache_base(void)
	166	{
	167	return l2cache_base;
	168	}
	169
4e803c40 SS	170	static void omap4_l2x0_disable(void)
4e803c40 SS	171	{
b25f3e1c	172	outer_flush_all();
4e803c40 SS	173	/* Disable PL310 L2 Cache controller */
	174	omap_smc1(0x102, 0x0);
	175	}
	176
4bdb1577 SS	177	static void omap4_l2x0_set_debug(unsigned long val)
	178	{
	179	/* Program PL310 L2 Cache controller debug register */
	180	omap_smc1(0x100, val);
	181	}
	182
fbc9be10 SS	183	static int __init omap_l2_cache_init(void)
fbc9be10 SS	184	{
1773e60a SS	185	u32 aux_ctrl = 0;
1773e60a SS	186
fbc9be10 SS	187	/*
	188	* To avoid code running on other OMAPs in
	189	* multi-omap builds
	190	*/
	191	if (!cpu_is_omap44xx())
	192	return -ENODEV;
	193
	194	/* Static mapping, never released */
	195	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	196	if (WARN_ON(!l2cache_base))
0db1803e SS	197	return -ENOMEM;
fbc9be10	198
fbc9be10	199	/*
a777b727 SS	200	* 16-way associativity, parity disabled
	201	* Way size - 32KB (es1.0)
	202	* Way size - 64KB (es2.0 +)
fbc9be10	203	*/
1773e60a SS	204	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
	205	(0x1 << 25) \|
	206	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
	207	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
	208
11e02640	209	if (omap_rev() == OMAP4430_REV_ES1_0) {
1773e60a	210	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
11e02640 MR	211	} else {
11e02640 MR	212	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
b0f20ff9	213	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
11e02640	214	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
b89cd71a SS	215	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
b89cd71a SS	216	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
11e02640 MR	217	}
	218	if (omap_rev() != OMAP4430_REV_ES1_0)
	219	omap_smc1(0x109, aux_ctrl);
	220
	221	/* Enable PL310 L2 Cache controller */
	222	omap_smc1(0x102, 0x1);
1773e60a	223
926fd45b SS	224	if (of_have_populated_dt())
	225	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	226	else
	227	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
fbc9be10	228
4e803c40 SS	229	/*
	230	* Override default outer_cache.disable with a OMAP4
	231	* specific one
	232	*/
	233	outer_cache.disable = omap4_l2x0_disable;
4bdb1577	234	outer_cache.set_debug = omap4_l2x0_set_debug;
4e803c40	235
fbc9be10 SS	236	return 0;
fbc9be10 SS	237	}
b76c8b19	238	omap_early_initcall(omap_l2_cache_init);
fbc9be10	239	#endif
501f0c75 SS	240
	241	void __iomem *omap4_get_sar_ram_base(void)
	242	{
	243	return sar_ram_base;
	244	}
	245
	246	/*
	247	* SAR RAM used to save and restore the HW
	248	* context in low power modes
	249	*/
	250	static int __init omap4_sar_ram_init(void)
	251	{
da0e02a1 SS	252	unsigned long sar_base;
da0e02a1 SS	253
501f0c75 SS	254	/*
	255	* To avoid code running on other OMAPs in
	256	* multi-omap builds
	257	*/
da0e02a1 SS	258	if (cpu_is_omap44xx())
	259	sar_base = OMAP44XX_SAR_RAM_BASE;
	260	else if (soc_is_omap54xx())
	261	sar_base = OMAP54XX_SAR_RAM_BASE;
	262	else
501f0c75 SS	263	return -ENOMEM;
	264
	265	/* Static mapping, never released */
da0e02a1	266	sar_ram_base = ioremap(sar_base, SZ_16K);
501f0c75 SS	267	if (WARN_ON(!sar_ram_base))
	268	return -ENOMEM;
	269
	270	return 0;
	271	}
b76c8b19	272	omap_early_initcall(omap4_sar_ram_init);
1ee47b0a	273
c4082d49 S	274	void __init omap_gic_of_init(void)
c4082d49 S	275	{
fd1c0786 SS	276	struct device_node *np;
	277
	278	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	279	if (!cpu_is_omap446x())
	280	goto skip_errata_init;
	281
	282	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	283	gic_dist_base_addr = of_iomap(np, 0);
	284	WARN_ON(!gic_dist_base_addr);
	285
	286	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	287	twd_base = of_iomap(np, 0);
	288	WARN_ON(!twd_base);
	289
	290	skip_errata_init:
c4082d49	291	omap_wakeupgen_init();
5c61e619 S	292	#ifdef CONFIG_IRQ_CROSSBAR
	293	irqcrossbar_init();
	294	#endif
0529e315	295	irqchip_init();
c4082d49	296	}