[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/irq-crossbar.h>
#include <linux/of_address.h>
#include <linux/reboot.h>

#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <asm/smp_twd.h>

#include "omap-wakeupgen.h"
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "mmc.h"
#include "prminst44xx.h"
#include "prcm_mpu44xx.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"
#include "sram.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;
static void __iomem *gic_dist_base_addr;
static void __iomem *twd_base;

#define IRQ_LOCALTIMER		29

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_RW_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void gic_dist_disable(void)
{
	if (gic_dist_base_addr)
		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}

void gic_dist_enable(void)
{
	if (gic_dist_base_addr)
		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
}

bool gic_dist_disabled(void)
{
	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}

void gic_timer_retrigger(void)
{
	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);

	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
		/*
		 * The local timer interrupt got lost while the distributor was
		 * disabled.  Ack the pending interrupt, and retrigger it.
		 */
		pr_warn("%s: lost localtimer interrupt\n", __func__);
		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
		}
	}
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
	unsigned smc_op;

	switch (reg) {
	case L2X0_CTRL:
		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
		break;

	case L2X0_AUX_CTRL:
		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
		break;

	case L2X0_DEBUG_CTRL:
		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
		break;

	case L310_PREFETCH_CTRL:
		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
		break;

	case L310_POWER_CTRL:
		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
		return;

	default:
		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
		return;
	}

	omap_smc1(smc_op, val);
}

int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
	aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
		   L310_AUX_CTRL_DATA_PREFETCH |
		   L310_AUX_CTRL_INSTR_PREFETCH;

	outer_cache.write_sec = omap4_l2c310_write_sec;
	if (of_have_populated_dt())
		l2x0_of_init(aux_ctrl, 0xcf9fffff);
	else
		l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);

	return 0;
}
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	unsigned long sar_base;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (cpu_is_omap44xx())
		sar_base = OMAP44XX_SAR_RAM_BASE;
	else if (soc_is_omap54xx())
		sar_base = OMAP54XX_SAR_RAM_BASE;
	else
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(sar_base, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
omap_early_initcall(omap4_sar_ram_init);

void __init omap_gic_of_init(void)
{
	struct device_node *np;

	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	if (!cpu_is_omap446x())
		goto skip_errata_init;

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	gic_dist_base_addr = of_iomap(np, 0);
	WARN_ON(!gic_dist_base_addr);

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	twd_base = of_iomap(np, 0);
	WARN_ON(!twd_base);

skip_errata_init:
	omap_wakeupgen_init();
#ifdef CONFIG_IRQ_CROSSBAR
	irqcrossbar_init();
#endif
	irqchip_init();
}
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
cd8ce159	17	#include <linux/irq.h>
0529e315	18	#include <linux/irqchip.h>
fbc9be10	19	#include <linux/platform_device.h>
137d105d	20	#include <linux/memblock.h>
7d7e1eba TL	21	#include <linux/of_irq.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/export.h>
520f7bd7	24	#include <linux/irqchip/arm-gic.h>
5c61e619	25	#include <linux/irqchip/irq-crossbar.h>
fd1c0786	26	#include <linux/of_address.h>
7b6d864b	27	#include <linux/reboot.h>
fbc9be10	28
fbc9be10	29	#include <asm/hardware/cache-l2x0.h>
137d105d	30	#include <asm/mach/map.h>
716a3dc2	31	#include <asm/memblock.h>
cd8ce159	32	#include <asm/smp_twd.h>
fbc9be10	33
732231a7	34	#include "omap-wakeupgen.h"
dbc04161	35	#include "soc.h"
b6a4226c	36	#include "iomap.h"
4e65331c	37	#include "common.h"
68f39e74	38	#include "mmc.h"
2f334a38	39	#include "prminst44xx.h"
d9a16f9a	40	#include "prcm_mpu44xx.h"
501f0c75	41	#include "omap4-sar-layout.h"
f7a9b8a1	42	#include "omap-secure.h"
bb772094	43	#include "sram.h"
fbc9be10 SS	44
fbc9be10 SS	45	#ifdef CONFIG_CACHE_L2X0
02afe8a7	46	static void __iomem *l2cache_base;
fbc9be10 SS	47	#endif
fbc9be10 SS	48
501f0c75	49	static void __iomem *sar_ram_base;
ff999b8a	50	static void __iomem *gic_dist_base_addr;
cd8ce159 CC	51	static void __iomem *twd_base;
	52
	53	#define IRQ_LOCALTIMER 29
501f0c75	54
137d105d SS	55	#ifdef CONFIG_OMAP4_ERRATA_I688
	56	/* Used to implement memory barrier on DRAM path */
	57	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	58
	59	void __iomem dram_sync, sram_sync;
	60
2ec1fc4e SS	61	static phys_addr_t paddr;
	62	static u32 size;
	63
137d105d SS	64	void omap_bus_sync(void)
	65	{
	66	if (dram_sync && sram_sync) {
	67	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	68	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	69	isb();
	70	}
	71	}
cc4ad907	72	EXPORT_SYMBOL(omap_bus_sync);
137d105d	73
2ec1fc4e SS	74	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	75	int __init omap_barrier_reserve_memblock(void)
137d105d	76	{
137d105d SS	77
137d105d SS	78	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	79	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	80
2ec1fc4e SS	81	return 0;
	82	}
	83
	84	void __init omap_barriers_init(void)
	85	{
	86	struct map_desc dram_io_desc[1];
	87
137d105d SS	88	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	89	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	90	dram_io_desc[0].length = size;
2e2c9de2	91	dram_io_desc[0].type = MT_MEMORY_RW_SO;
137d105d SS	92	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	93	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	94	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	95
	96	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	97	(long long) paddr, dram_io_desc[0].virtual);
	98
137d105d	99	}
2ec1fc4e SS	100	#else
	101	void __init omap_barriers_init(void)
	102	{}
137d105d SS	103	#endif
137d105d SS	104
ff999b8a SS	105	void gic_dist_disable(void)
	106	{
	107	if (gic_dist_base_addr)
edfaf05c	108	writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
ff999b8a SS	109	}
ff999b8a SS	110
74ed7bdc SG	111	void gic_dist_enable(void)
	112	{
	113	if (gic_dist_base_addr)
edfaf05c	114	writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
74ed7bdc SG	115	}
74ed7bdc SG	116
cd8ce159 CC	117	bool gic_dist_disabled(void)
cd8ce159 CC	118	{
edfaf05c	119	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
cd8ce159 CC	120	}
	121
	122	void gic_timer_retrigger(void)
	123	{
edfaf05c VK	124	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
	125	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	126	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
cd8ce159 CC	127
	128	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
	129	/*
	130	* The local timer interrupt got lost while the distributor was
	131	* disabled. Ack the pending interrupt, and retrigger it.
	132	*/
	133	pr_warn("%s: lost localtimer interrupt\n", __func__);
edfaf05c	134	writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
cd8ce159	135	if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
edfaf05c	136	writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
cd8ce159	137	twd_ctrl \|= TWD_TIMER_CONTROL_ENABLE;
edfaf05c	138	writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
cd8ce159 CC	139	}
	140	}
	141	}
	142
fbc9be10	143	#ifdef CONFIG_CACHE_L2X0
4e803c40	144
02afe8a7 SS	145	void __iomem *omap4_get_l2cache_base(void)
	146	{
	147	return l2cache_base;
	148	}
	149
36827edd	150	static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
4e803c40	151	{
36827edd	152	unsigned smc_op;
4e803c40	153
36827edd RK	154	switch (reg) {
	155	case L2X0_CTRL:
	156	smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
	157	break;
	158
	159	case L2X0_AUX_CTRL:
	160	smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
	161	break;
	162
	163	case L2X0_DEBUG_CTRL:
	164	smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
	165	break;
	166
	167	case L310_PREFETCH_CTRL:
	168	smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
	169	break;
	170
ba394f0b SN	171	case L310_POWER_CTRL:
	172	pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
	173	return;
	174
36827edd RK	175	default:
	176	WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
	177	return;
	178	}
	179
	180	omap_smc1(smc_op, val);
4bdb1577 SS	181	}
4bdb1577 SS	182
b39b14e6	183	int __init omap_l2_cache_init(void)
fbc9be10	184	{
cef3d92c	185	u32 aux_ctrl;
fbc9be10 SS	186
	187	/* Static mapping, never released */
	188	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	189	if (WARN_ON(!l2cache_base))
0db1803e SS	190	return -ENOMEM;
fbc9be10	191
cef3d92c	192	/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
d196483d	193	aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE \|
1a5a954c	194	L310_AUX_CTRL_DATA_PREFETCH \|
36bccb11	195	L310_AUX_CTRL_INSTR_PREFETCH;
1773e60a	196
36827edd	197	outer_cache.write_sec = omap4_l2c310_write_sec;
926fd45b	198	if (of_have_populated_dt())
d196483d	199	l2x0_of_init(aux_ctrl, 0xcf9fffff);
926fd45b	200	else
d196483d	201	l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
4e803c40	202
fbc9be10 SS	203	return 0;
fbc9be10 SS	204	}
fbc9be10	205	#endif
501f0c75 SS	206
	207	void __iomem *omap4_get_sar_ram_base(void)
	208	{
	209	return sar_ram_base;
	210	}
	211
	212	/*
	213	* SAR RAM used to save and restore the HW
	214	* context in low power modes
	215	*/
	216	static int __init omap4_sar_ram_init(void)
	217	{
da0e02a1 SS	218	unsigned long sar_base;
da0e02a1 SS	219
501f0c75 SS	220	/*
	221	* To avoid code running on other OMAPs in
	222	* multi-omap builds
	223	*/
da0e02a1 SS	224	if (cpu_is_omap44xx())
	225	sar_base = OMAP44XX_SAR_RAM_BASE;
	226	else if (soc_is_omap54xx())
	227	sar_base = OMAP54XX_SAR_RAM_BASE;
	228	else
501f0c75 SS	229	return -ENOMEM;
	230
	231	/* Static mapping, never released */
da0e02a1	232	sar_ram_base = ioremap(sar_base, SZ_16K);
501f0c75 SS	233	if (WARN_ON(!sar_ram_base))
	234	return -ENOMEM;
	235
	236	return 0;
	237	}
b76c8b19	238	omap_early_initcall(omap4_sar_ram_init);
1ee47b0a	239
c4082d49 S	240	void __init omap_gic_of_init(void)
c4082d49 S	241	{
fd1c0786 SS	242	struct device_node *np;
	243
	244	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	245	if (!cpu_is_omap446x())
	246	goto skip_errata_init;
	247
	248	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	249	gic_dist_base_addr = of_iomap(np, 0);
	250	WARN_ON(!gic_dist_base_addr);
	251
	252	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	253	twd_base = of_iomap(np, 0);
	254	WARN_ON(!twd_base);
	255
	256	skip_errata_init:
c4082d49	257	omap_wakeupgen_init();
5c61e619 S	258	#ifdef CONFIG_IRQ_CROSSBAR
	259	irqcrossbar_init();
	260	#endif
0529e315	261	irqchip_init();
c4082d49	262	}