[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_address.h>
#include <linux/reboot.h>
#include <linux/genalloc.h>

#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include <asm/smp_twd.h>

#include "omap-wakeupgen.h"
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prminst44xx.h"
#include "prcm_mpu44xx.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"
#include "sram.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;
static void __iomem *gic_dist_base_addr;
static void __iomem *twd_base;

#define IRQ_LOCALTIMER		29

#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER

/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

static void __iomem *dram_sync, *sram_sync;
static phys_addr_t dram_sync_paddr;
static u32 dram_sync_size;

/*
 * The OMAP4 bus structure contains asynchronous bridges which can buffer
 * data writes from the MPU. These asynchronous bridges can be found on
 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
 *
 * We need to be careful about re-ordering which can happen as a result
 * of different accesses being performed via different paths, and
 * therefore different asynchronous bridges.
 */

/*
 * OMAP4 interconnect barrier which is called for each mb() and wmb().
 * This is to ensure that normal paths to DRAM (normal memory, cacheable
 * accesses) are properly synchronised with writes to DMA coherent memory
 * (normal memory, uncacheable) and device writes.
 *
 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
 * path, as we need to ensure that data is visible to other system
 * masters prior to writes to those system masters being seen.
 *
 * Note: the SRAM path is not synchronised via mb() and wmb().
 */
static void omap4_mb(void)
{
	if (dram_sync)
		writel_relaxed(0, dram_sync);
}

/*
 * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
 *
 * If a data is stalled inside asynchronous bridge because of back
 * pressure, it may be accepted multiple times, creating pointer
 * misalignment that will corrupt next transfers on that data path until
 * next reset of the system. No recovery procedure once the issue is hit,
 * the path remains consistently broken.
 *
 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
 * interconnects.
 *
 * This situation can happen only when the idle is initiated by a Master
 * Request Disconnection (which is trigged by software when executing WFI
 * on the CPU).
 *
 * The work-around for this errata needs all the initiators connected
 * through an async bridge to ensure that data path is properly drained
 * before issuing WFI. This condition will be met if one Strongly ordered
 * access is performed to the target right before executing the WFI.
 *
 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
 * IO barrier ensure that there is no synchronisation loss on initiators
 * operating on both interconnect port simultaneously.
 *
 * This is a stronger version of the OMAP4 memory barrier below, and
 * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
 * as well, and is necessary prior to executing a WFI.
 */
void omap_interconnect_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}

static int __init omap4_sram_init(void)
{
	struct device_node *np;
	struct gen_pool *sram_pool;

	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
	if (!np)
		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
			__func__);
	sram_pool = of_gen_pool_get(np, "sram", 0);
	if (!sram_pool)
		pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
			__func__);
	else
		sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);

	return 0;
}
omap_arch_initcall(omap4_sram_init);

/* Steal one page physical memory for barrier implementation */
void __init omap_barrier_reserve_memblock(void)
{
	dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
	dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
	dram_io_desc[0].length = dram_sync_size;
	dram_io_desc[0].type = MT_MEMORY_RW_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;

	pr_info("OMAP4: Map %pa to %p for dram barrier\n",
		&dram_sync_paddr, dram_sync);

	soc_mb = omap4_mb;
}

#endif

void gic_dist_disable(void)
{
	if (gic_dist_base_addr)
		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
}

void gic_dist_enable(void)
{
	if (gic_dist_base_addr)
		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
}

bool gic_dist_disabled(void)
{
	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
}

void gic_timer_retrigger(void)
{
	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);

	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
		/*
		 * The local timer interrupt got lost while the distributor was
		 * disabled.  Ack the pending interrupt, and retrigger it.
		 */
		pr_warn("%s: lost localtimer interrupt\n", __func__);
		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
		}
	}
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
	unsigned smc_op;

	switch (reg) {
	case L2X0_CTRL:
		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
		break;

	case L2X0_AUX_CTRL:
		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
		break;

	case L2X0_DEBUG_CTRL:
		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
		break;

	case L310_PREFETCH_CTRL:
		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
		break;

	case L310_POWER_CTRL:
		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
		return;

	default:
		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
		return;
	}

	omap_smc1(smc_op, val);
}

int __init omap_l2_cache_init(void)
{
	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;
	return 0;
}
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW context in low power modes.
 * Note that we need to initialize this very early for kexec. See
 * omap4_mpuss_early_init().
 */
void __init omap4_sar_ram_init(void)
{
	unsigned long sar_base;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (cpu_is_omap44xx())
		sar_base = OMAP44XX_SAR_RAM_BASE;
	else if (soc_is_omap54xx())
		sar_base = OMAP54XX_SAR_RAM_BASE;
	else
		return;

	/* Static mapping, never released */
	sar_ram_base = ioremap(sar_base, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return;
}

static const struct of_device_id intc_match[] = {
	{ .compatible = "ti,omap4-wugen-mpu", },
	{ .compatible = "ti,omap5-wugen-mpu", },
	{ },
};

static struct device_node *intc_node;

unsigned int omap4_xlate_irq(unsigned int hwirq)
{
	struct of_phandle_args irq_data;
	unsigned int irq;

	if (!intc_node)
		intc_node = of_find_matching_node(NULL, intc_match);

	if (WARN_ON(!intc_node))
		return hwirq;

	irq_data.np = intc_node;
	irq_data.args_count = 3;
	irq_data.args[0] = 0;
	irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
	irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;

	irq = irq_create_of_mapping(&irq_data);
	if (WARN_ON(!irq))
		irq = hwirq;

	return irq;
}

void __init omap_gic_of_init(void)
{
	struct device_node *np;

	intc_node = of_find_matching_node(NULL, intc_match);
	if (WARN_ON(!intc_node)) {
		pr_err("No WUGEN found in DT, system will misbehave.\n");
		pr_err("UPDATE YOUR DEVICE TREE!\n");
	}

	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	if (!cpu_is_omap446x())
		goto skip_errata_init;

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	gic_dist_base_addr = of_iomap(np, 0);
	WARN_ON(!gic_dist_base_addr);

	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	twd_base = of_iomap(np, 0);
	WARN_ON(!twd_base);

skip_errata_init:
	irqchip_init();
}
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
cd8ce159	17	#include <linux/irq.h>
0529e315	18	#include <linux/irqchip.h>
fbc9be10	19	#include <linux/platform_device.h>
137d105d	20	#include <linux/memblock.h>
7d7e1eba TL	21	#include <linux/of_irq.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/export.h>
520f7bd7	24	#include <linux/irqchip/arm-gic.h>
fd1c0786	25	#include <linux/of_address.h>
7b6d864b	26	#include <linux/reboot.h>
1306c08a	27	#include <linux/genalloc.h>
fbc9be10	28
fbc9be10	29	#include <asm/hardware/cache-l2x0.h>
137d105d	30	#include <asm/mach/map.h>
716a3dc2	31	#include <asm/memblock.h>
cd8ce159	32	#include <asm/smp_twd.h>
fbc9be10	33
732231a7	34	#include "omap-wakeupgen.h"
dbc04161	35	#include "soc.h"
b6a4226c	36	#include "iomap.h"
4e65331c	37	#include "common.h"
2f334a38	38	#include "prminst44xx.h"
d9a16f9a	39	#include "prcm_mpu44xx.h"
501f0c75	40	#include "omap4-sar-layout.h"
f7a9b8a1	41	#include "omap-secure.h"
bb772094	42	#include "sram.h"
fbc9be10 SS	43
fbc9be10 SS	44	#ifdef CONFIG_CACHE_L2X0
02afe8a7	45	static void __iomem *l2cache_base;
fbc9be10 SS	46	#endif
fbc9be10 SS	47
501f0c75	48	static void __iomem *sar_ram_base;
ff999b8a	49	static void __iomem *gic_dist_base_addr;
cd8ce159 CC	50	static void __iomem *twd_base;
	51
	52	#define IRQ_LOCALTIMER 29
501f0c75	53
3fa60975 RK	54	#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
3fa60975 RK	55
f746929f RK	56	/* Used to implement memory barrier on DRAM path */
	57	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	58
3fa60975 RK	59	static void __iomem dram_sync, sram_sync;
	60	static phys_addr_t dram_sync_paddr;
	61	static u32 dram_sync_size;
	62
	63	/*
6eedfcbe	64	* The OMAP4 bus structure contains asynchronous bridges which can buffer
3fa60975 RK	65	* data writes from the MPU. These asynchronous bridges can be found on
	66	* paths between the MPU to EMIF, and the MPU to L3 interconnects.
	67	*
	68	* We need to be careful about re-ordering which can happen as a result
	69	* of different accesses being performed via different paths, and
	70	* therefore different asynchronous bridges.
	71	*/
f746929f	72
3fa60975 RK	73	/*
	74	* OMAP4 interconnect barrier which is called for each mb() and wmb().
	75	* This is to ensure that normal paths to DRAM (normal memory, cacheable
	76	* accesses) are properly synchronised with writes to DMA coherent memory
	77	* (normal memory, uncacheable) and device writes.
	78	*
	79	* The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
	80	* path, as we need to ensure that data is visible to other system
	81	* masters prior to writes to those system masters being seen.
	82	*
	83	* Note: the SRAM path is not synchronised via mb() and wmb().
	84	*/
	85	static void omap4_mb(void)
	86	{
	87	if (dram_sync)
	88	writel_relaxed(0, dram_sync);
	89	}
f746929f	90
3fa60975 RK	91	/*
	92	* OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
	93	*
	94	* If a data is stalled inside asynchronous bridge because of back
	95	* pressure, it may be accepted multiple times, creating pointer
	96	* misalignment that will corrupt next transfers on that data path until
	97	* next reset of the system. No recovery procedure once the issue is hit,
	98	* the path remains consistently broken.
	99	*
	100	* Async bridges can be found on paths between MPU to EMIF and MPU to L3
	101	* interconnects.
	102	*
	103	* This situation can happen only when the idle is initiated by a Master
	104	* Request Disconnection (which is trigged by software when executing WFI
	105	* on the CPU).
	106	*
	107	* The work-around for this errata needs all the initiators connected
	108	* through an async bridge to ensure that data path is properly drained
	109	* before issuing WFI. This condition will be met if one Strongly ordered
	110	* access is performed to the target right before executing the WFI.
	111	*
	112	* In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
	113	* IO barrier ensure that there is no synchronisation loss on initiators
	114	* operating on both interconnect port simultaneously.
	115	*
	116	* This is a stronger version of the OMAP4 memory barrier below, and
	117	* operates on both the MPU->MA->EMIF path but also the MPU->OCP path
	118	* as well, and is necessary prior to executing a WFI.
	119	*/
	120	void omap_interconnect_sync(void)
f746929f RK	121	{
	122	if (dram_sync && sram_sync) {
	123	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	124	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	125	isb();
	126	}
	127	}
f746929f RK	128
	129	static int __init omap4_sram_init(void)
	130	{
	131	struct device_node *np;
	132	struct gen_pool *sram_pool;
	133
	134	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
	135	if (!np)
	136	pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
	137	__func__);
3fa60975	138	sram_pool = of_gen_pool_get(np, "sram", 0);
f746929f RK	139	if (!sram_pool)
	140	pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
	141	__func__);
	142	else
	143	sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
	144
	145	return 0;
	146	}
	147	omap_arch_initcall(omap4_sram_init);
	148
	149	/* Steal one page physical memory for barrier implementation */
3fa60975	150	void __init omap_barrier_reserve_memblock(void)
f746929f	151	{
3fa60975 RK	152	dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
3fa60975 RK	153	dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
f746929f RK	154	}
	155
	156	void __init omap_barriers_init(void)
	157	{
	158	struct map_desc dram_io_desc[1];
	159
	160	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
3fa60975 RK	161	dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
3fa60975 RK	162	dram_io_desc[0].length = dram_sync_size;
f746929f RK	163	dram_io_desc[0].type = MT_MEMORY_RW_SO;
	164	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	165	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	166
3fa60975 RK	167	pr_info("OMAP4: Map %pa to %p for dram barrier\n",
3fa60975 RK	168	&dram_sync_paddr, dram_sync);
f746929f	169
3fa60975	170	soc_mb = omap4_mb;
f746929f	171	}
3fa60975	172
f746929f RK	173	#endif
f746929f RK	174
ff999b8a SS	175	void gic_dist_disable(void)
	176	{
	177	if (gic_dist_base_addr)
edfaf05c	178	writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
ff999b8a SS	179	}
ff999b8a SS	180
74ed7bdc SG	181	void gic_dist_enable(void)
	182	{
	183	if (gic_dist_base_addr)
edfaf05c	184	writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
74ed7bdc SG	185	}
74ed7bdc SG	186
cd8ce159 CC	187	bool gic_dist_disabled(void)
cd8ce159 CC	188	{
edfaf05c	189	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
cd8ce159 CC	190	}
	191
	192	void gic_timer_retrigger(void)
	193	{
edfaf05c VK	194	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
	195	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
	196	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
cd8ce159 CC	197
	198	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
	199	/*
	200	* The local timer interrupt got lost while the distributor was
	201	* disabled. Ack the pending interrupt, and retrigger it.
	202	*/
	203	pr_warn("%s: lost localtimer interrupt\n", __func__);
edfaf05c	204	writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
cd8ce159	205	if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
edfaf05c	206	writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
cd8ce159	207	twd_ctrl \|= TWD_TIMER_CONTROL_ENABLE;
edfaf05c	208	writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
cd8ce159 CC	209	}
	210	}
	211	}
	212
fbc9be10	213	#ifdef CONFIG_CACHE_L2X0
4e803c40	214
02afe8a7 SS	215	void __iomem *omap4_get_l2cache_base(void)
	216	{
	217	return l2cache_base;
	218	}
	219
944e9df1	220	void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
4e803c40	221	{
36827edd	222	unsigned smc_op;
4e803c40	223
36827edd RK	224	switch (reg) {
	225	case L2X0_CTRL:
	226	smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
	227	break;
	228
	229	case L2X0_AUX_CTRL:
	230	smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
	231	break;
	232
	233	case L2X0_DEBUG_CTRL:
	234	smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
	235	break;
	236
	237	case L310_PREFETCH_CTRL:
	238	smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
	239	break;
	240
ba394f0b SN	241	case L310_POWER_CTRL:
	242	pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
	243	return;
	244
36827edd RK	245	default:
	246	WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
	247	return;
	248	}
	249
	250	omap_smc1(smc_op, val);
4bdb1577 SS	251	}
4bdb1577 SS	252
b39b14e6	253	int __init omap_l2_cache_init(void)
fbc9be10	254	{
fbc9be10 SS	255	/* Static mapping, never released */
fbc9be10 SS	256	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	257	if (WARN_ON(!l2cache_base))
0db1803e SS	258	return -ENOMEM;
fbc9be10 SS	259	return 0;
fbc9be10 SS	260	}
fbc9be10	261	#endif
501f0c75 SS	262
	263	void __iomem *omap4_get_sar_ram_base(void)
	264	{
	265	return sar_ram_base;
	266	}
	267
	268	/*
f4b9f40a TL	269	* SAR RAM used to save and restore the HW context in low power modes.
	270	* Note that we need to initialize this very early for kexec. See
	271	* omap4_mpuss_early_init().
501f0c75	272	*/
f4b9f40a	273	void __init omap4_sar_ram_init(void)
501f0c75	274	{
da0e02a1 SS	275	unsigned long sar_base;
da0e02a1 SS	276
501f0c75 SS	277	/*
	278	* To avoid code running on other OMAPs in
	279	* multi-omap builds
	280	*/
da0e02a1 SS	281	if (cpu_is_omap44xx())
	282	sar_base = OMAP44XX_SAR_RAM_BASE;
	283	else if (soc_is_omap54xx())
	284	sar_base = OMAP54XX_SAR_RAM_BASE;
	285	else
f4b9f40a	286	return;
501f0c75 SS	287
501f0c75 SS	288	/* Static mapping, never released */
da0e02a1	289	sar_ram_base = ioremap(sar_base, SZ_16K);
501f0c75	290	if (WARN_ON(!sar_ram_base))
f4b9f40a	291	return;
501f0c75	292	}
1ee47b0a	293
7136d457 MZ	294	static const struct of_device_id intc_match[] = {
	295	{ .compatible = "ti,omap4-wugen-mpu", },
	296	{ .compatible = "ti,omap5-wugen-mpu", },
0fb22a8f MZ	297	{ },
	298	};
	299
7136d457	300	static struct device_node *intc_node;
0fb22a8f MZ	301
	302	unsigned int omap4_xlate_irq(unsigned int hwirq)
	303	{
	304	struct of_phandle_args irq_data;
	305	unsigned int irq;
	306
7136d457 MZ	307	if (!intc_node)
7136d457 MZ	308	intc_node = of_find_matching_node(NULL, intc_match);
0fb22a8f	309
7136d457	310	if (WARN_ON(!intc_node))
0fb22a8f MZ	311	return hwirq;
0fb22a8f MZ	312
7136d457	313	irq_data.np = intc_node;
0fb22a8f MZ	314	irq_data.args_count = 3;
	315	irq_data.args[0] = 0;
	316	irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
	317	irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
	318
	319	irq = irq_create_of_mapping(&irq_data);
	320	if (WARN_ON(!irq))
	321	irq = hwirq;
	322
	323	return irq;
	324	}
	325
c4082d49 S	326	void __init omap_gic_of_init(void)
c4082d49 S	327	{
fd1c0786 SS	328	struct device_node *np;
fd1c0786 SS	329
7136d457 MZ	330	intc_node = of_find_matching_node(NULL, intc_match);
	331	if (WARN_ON(!intc_node)) {
	332	pr_err("No WUGEN found in DT, system will misbehave.\n");
	333	pr_err("UPDATE YOUR DEVICE TREE!\n");
	334	}
	335
fd1c0786 SS	336	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
	337	if (!cpu_is_omap446x())
	338	goto skip_errata_init;
	339
	340	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	341	gic_dist_base_addr = of_iomap(np, 0);
	342	WARN_ON(!gic_dist_base_addr);
	343
	344	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
	345	twd_base = of_iomap(np, 0);
	346	WARN_ON(!twd_base);
	347
	348	skip_errata_init:
0529e315	349	irqchip_init();
c4082d49	350	}