projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| fbc9be10 SS |
1 | /* |
| 2 | * OMAP4 specific common source file. | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
| 5 | * Author: | |
| 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| 7 | * | |
| 8 | * | |
| 9 | * This program is free software,you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/kernel.h> | |
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/io.h> | |
| 17 | #include <linux/platform_device.h> | |
| 18 | ||
| 19 | #include <asm/hardware/gic.h> | |
| 20 | #include <asm/hardware/cache-l2x0.h> | |
| 21 | ||
| 741e3a89 TL |
22 | #include <plat/irqs.h> |
| 23 | ||
| fbc9be10 | 24 | #include <mach/hardware.h> |
| 4e65331c TL |
25 | |
| 26 | #include "common.h" | |
| 501f0c75 | 27 | #include "omap4-sar-layout.h" |
| fbc9be10 SS |
28 | |
| 29 | #ifdef CONFIG_CACHE_L2X0 | |
| 02afe8a7 | 30 | static void __iomem *l2cache_base; |
| fbc9be10 SS |
31 | #endif |
| 32 | ||
| 501f0c75 SS |
33 | static void __iomem *sar_ram_base; |
| 34 | ||
| fbc9be10 SS |
35 | void __init gic_init_irq(void) |
| 36 | { | |
| ab65be26 MZ |
37 | void __iomem *omap_irq_base; |
| 38 | void __iomem *gic_dist_base_addr; | |
| 39 | ||
| fbc9be10 SS |
40 | /* Static mapping, never released */ |
| 41 | gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); | |
| 42 | BUG_ON(!gic_dist_base_addr); | |
| fbc9be10 SS |
43 | |
| 44 | /* Static mapping, never released */ | |
| 741e3a89 TL |
45 | omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); |
| 46 | BUG_ON(!omap_irq_base); | |
| b580b899 | 47 | |
| 741e3a89 | 48 | gic_init(0, 29, gic_dist_base_addr, omap_irq_base); |
| fbc9be10 SS |
49 | } |
| 50 | ||
| 51 | #ifdef CONFIG_CACHE_L2X0 | |
| 4e803c40 | 52 | |
| 02afe8a7 SS |
53 | void __iomem *omap4_get_l2cache_base(void) |
| 54 | { | |
| 55 | return l2cache_base; | |
| 56 | } | |
| 57 | ||
| 4e803c40 SS |
58 | static void omap4_l2x0_disable(void) |
| 59 | { | |
| 60 | /* Disable PL310 L2 Cache controller */ | |
| 61 | omap_smc1(0x102, 0x0); | |
| 62 | } | |
| 63 | ||
| 4bdb1577 SS |
64 | static void omap4_l2x0_set_debug(unsigned long val) |
| 65 | { | |
| 66 | /* Program PL310 L2 Cache controller debug register */ | |
| 67 | omap_smc1(0x100, val); | |
| 68 | } | |
| 69 | ||
| fbc9be10 SS |
70 | static int __init omap_l2_cache_init(void) |
| 71 | { | |
| 1773e60a SS |
72 | u32 aux_ctrl = 0; |
| 73 | ||
| fbc9be10 SS |
74 | /* |
| 75 | * To avoid code running on other OMAPs in | |
| 76 | * multi-omap builds | |
| 77 | */ | |
| 78 | if (!cpu_is_omap44xx()) | |
| 79 | return -ENODEV; | |
| 80 | ||
| 81 | /* Static mapping, never released */ | |
| 82 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | |
| 0db1803e SS |
83 | if (WARN_ON(!l2cache_base)) |
| 84 | return -ENOMEM; | |
| fbc9be10 | 85 | |
| fbc9be10 | 86 | /* |
| a777b727 SS |
87 | * 16-way associativity, parity disabled |
| 88 | * Way size - 32KB (es1.0) | |
| 89 | * Way size - 64KB (es2.0 +) | |
| fbc9be10 | 90 | */ |
| 1773e60a SS |
91 | aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | |
| 92 | (0x1 << 25) | | |
| 93 | (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | | |
| 94 | (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); | |
| 95 | ||
| 11e02640 | 96 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 1773e60a | 97 | aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; |
| 11e02640 MR |
98 | } else { |
| 99 | aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | | |
| b0f20ff9 | 100 | (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | |
| 11e02640 | 101 | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | |
| b89cd71a SS |
102 | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | |
| 103 | (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); | |
| 11e02640 MR |
104 | } |
| 105 | if (omap_rev() != OMAP4430_REV_ES1_0) | |
| 106 | omap_smc1(0x109, aux_ctrl); | |
| 107 | ||
| 108 | /* Enable PL310 L2 Cache controller */ | |
| 109 | omap_smc1(0x102, 0x1); | |
| 1773e60a SS |
110 | |
| 111 | l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); | |
| fbc9be10 | 112 | |
| 4e803c40 SS |
113 | /* |
| 114 | * Override default outer_cache.disable with a OMAP4 | |
| 115 | * specific one | |
| 116 | */ | |
| 117 | outer_cache.disable = omap4_l2x0_disable; | |
| 4bdb1577 | 118 | outer_cache.set_debug = omap4_l2x0_set_debug; |
| 4e803c40 | 119 | |
| fbc9be10 SS |
120 | return 0; |
| 121 | } | |
| 122 | early_initcall(omap_l2_cache_init); | |
| 123 | #endif | |
| 501f0c75 SS |
124 | |
| 125 | void __iomem *omap4_get_sar_ram_base(void) | |
| 126 | { | |
| 127 | return sar_ram_base; | |
| 128 | } | |
| 129 | ||
| 130 | /* | |
| 131 | * SAR RAM used to save and restore the HW | |
| 132 | * context in low power modes | |
| 133 | */ | |
| 134 | static int __init omap4_sar_ram_init(void) | |
| 135 | { | |
| 136 | /* | |
| 137 | * To avoid code running on other OMAPs in | |
| 138 | * multi-omap builds | |
| 139 | */ | |
| 140 | if (!cpu_is_omap44xx()) | |
| 141 | return -ENOMEM; | |
| 142 | ||
| 143 | /* Static mapping, never released */ | |
| 144 | sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); | |
| 145 | if (WARN_ON(!sar_ram_base)) | |
| 146 | return -ENOMEM; | |
| 147 | ||
| 148 | return 0; | |
| 149 | } | |
| 150 | early_initcall(omap4_sar_ram_init); |