Commit | Line | Data |
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fbc9be10 SS |
1 | /* |
2 | * OMAP4 specific common source file. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Author: | |
6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
7 | * | |
8 | * | |
9 | * This program is free software,you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
cd8ce159 | 17 | #include <linux/irq.h> |
0529e315 | 18 | #include <linux/irqchip.h> |
fbc9be10 | 19 | #include <linux/platform_device.h> |
137d105d | 20 | #include <linux/memblock.h> |
7d7e1eba TL |
21 | #include <linux/of_irq.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/export.h> | |
520f7bd7 | 24 | #include <linux/irqchip/arm-gic.h> |
5c61e619 | 25 | #include <linux/irqchip/irq-crossbar.h> |
fd1c0786 | 26 | #include <linux/of_address.h> |
7b6d864b | 27 | #include <linux/reboot.h> |
fbc9be10 | 28 | |
fbc9be10 | 29 | #include <asm/hardware/cache-l2x0.h> |
137d105d | 30 | #include <asm/mach/map.h> |
716a3dc2 | 31 | #include <asm/memblock.h> |
cd8ce159 | 32 | #include <asm/smp_twd.h> |
fbc9be10 | 33 | |
732231a7 | 34 | #include "omap-wakeupgen.h" |
dbc04161 | 35 | #include "soc.h" |
b6a4226c | 36 | #include "iomap.h" |
4e65331c | 37 | #include "common.h" |
68f39e74 | 38 | #include "mmc.h" |
2f334a38 | 39 | #include "prminst44xx.h" |
d9a16f9a | 40 | #include "prcm_mpu44xx.h" |
501f0c75 | 41 | #include "omap4-sar-layout.h" |
f7a9b8a1 | 42 | #include "omap-secure.h" |
bb772094 | 43 | #include "sram.h" |
fbc9be10 SS |
44 | |
45 | #ifdef CONFIG_CACHE_L2X0 | |
02afe8a7 | 46 | static void __iomem *l2cache_base; |
fbc9be10 SS |
47 | #endif |
48 | ||
501f0c75 | 49 | static void __iomem *sar_ram_base; |
ff999b8a | 50 | static void __iomem *gic_dist_base_addr; |
cd8ce159 CC |
51 | static void __iomem *twd_base; |
52 | ||
53 | #define IRQ_LOCALTIMER 29 | |
501f0c75 | 54 | |
137d105d SS |
55 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
56 | /* Used to implement memory barrier on DRAM path */ | |
57 | #define OMAP4_DRAM_BARRIER_VA 0xfe600000 | |
58 | ||
59 | void __iomem *dram_sync, *sram_sync; | |
60 | ||
2ec1fc4e SS |
61 | static phys_addr_t paddr; |
62 | static u32 size; | |
63 | ||
137d105d SS |
64 | void omap_bus_sync(void) |
65 | { | |
66 | if (dram_sync && sram_sync) { | |
67 | writel_relaxed(readl_relaxed(dram_sync), dram_sync); | |
68 | writel_relaxed(readl_relaxed(sram_sync), sram_sync); | |
69 | isb(); | |
70 | } | |
71 | } | |
cc4ad907 | 72 | EXPORT_SYMBOL(omap_bus_sync); |
137d105d | 73 | |
2ec1fc4e SS |
74 | /* Steal one page physical memory for barrier implementation */ |
75 | int __init omap_barrier_reserve_memblock(void) | |
137d105d | 76 | { |
137d105d SS |
77 | |
78 | size = ALIGN(PAGE_SIZE, SZ_1M); | |
716a3dc2 RK |
79 | paddr = arm_memblock_steal(size, SZ_1M); |
80 | ||
2ec1fc4e SS |
81 | return 0; |
82 | } | |
83 | ||
84 | void __init omap_barriers_init(void) | |
85 | { | |
86 | struct map_desc dram_io_desc[1]; | |
87 | ||
137d105d SS |
88 | dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; |
89 | dram_io_desc[0].pfn = __phys_to_pfn(paddr); | |
90 | dram_io_desc[0].length = size; | |
2e2c9de2 | 91 | dram_io_desc[0].type = MT_MEMORY_RW_SO; |
137d105d SS |
92 | iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); |
93 | dram_sync = (void __iomem *) dram_io_desc[0].virtual; | |
94 | sram_sync = (void __iomem *) OMAP4_SRAM_VA; | |
95 | ||
96 | pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", | |
97 | (long long) paddr, dram_io_desc[0].virtual); | |
98 | ||
137d105d | 99 | } |
2ec1fc4e SS |
100 | #else |
101 | void __init omap_barriers_init(void) | |
102 | {} | |
137d105d SS |
103 | #endif |
104 | ||
ff999b8a SS |
105 | void gic_dist_disable(void) |
106 | { | |
107 | if (gic_dist_base_addr) | |
edfaf05c | 108 | writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); |
ff999b8a SS |
109 | } |
110 | ||
74ed7bdc SG |
111 | void gic_dist_enable(void) |
112 | { | |
113 | if (gic_dist_base_addr) | |
edfaf05c | 114 | writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); |
74ed7bdc SG |
115 | } |
116 | ||
cd8ce159 CC |
117 | bool gic_dist_disabled(void) |
118 | { | |
edfaf05c | 119 | return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); |
cd8ce159 CC |
120 | } |
121 | ||
122 | void gic_timer_retrigger(void) | |
123 | { | |
edfaf05c VK |
124 | u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); |
125 | u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); | |
126 | u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); | |
cd8ce159 CC |
127 | |
128 | if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { | |
129 | /* | |
130 | * The local timer interrupt got lost while the distributor was | |
131 | * disabled. Ack the pending interrupt, and retrigger it. | |
132 | */ | |
133 | pr_warn("%s: lost localtimer interrupt\n", __func__); | |
edfaf05c | 134 | writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); |
cd8ce159 | 135 | if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { |
edfaf05c | 136 | writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); |
cd8ce159 | 137 | twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; |
edfaf05c | 138 | writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); |
cd8ce159 CC |
139 | } |
140 | } | |
141 | } | |
142 | ||
fbc9be10 | 143 | #ifdef CONFIG_CACHE_L2X0 |
4e803c40 | 144 | |
02afe8a7 SS |
145 | void __iomem *omap4_get_l2cache_base(void) |
146 | { | |
147 | return l2cache_base; | |
148 | } | |
149 | ||
36827edd | 150 | static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) |
4e803c40 | 151 | { |
36827edd | 152 | unsigned smc_op; |
4e803c40 | 153 | |
36827edd RK |
154 | switch (reg) { |
155 | case L2X0_CTRL: | |
156 | smc_op = OMAP4_MON_L2X0_CTRL_INDEX; | |
157 | break; | |
158 | ||
159 | case L2X0_AUX_CTRL: | |
160 | smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX; | |
161 | break; | |
162 | ||
163 | case L2X0_DEBUG_CTRL: | |
164 | smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX; | |
165 | break; | |
166 | ||
167 | case L310_PREFETCH_CTRL: | |
168 | smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; | |
169 | break; | |
170 | ||
171 | default: | |
172 | WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); | |
173 | return; | |
174 | } | |
175 | ||
176 | omap_smc1(smc_op, val); | |
4bdb1577 SS |
177 | } |
178 | ||
b39b14e6 | 179 | int __init omap_l2_cache_init(void) |
fbc9be10 | 180 | { |
cef3d92c | 181 | u32 aux_ctrl; |
fbc9be10 SS |
182 | |
183 | /* Static mapping, never released */ | |
184 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | |
0db1803e SS |
185 | if (WARN_ON(!l2cache_base)) |
186 | return -ENOMEM; | |
fbc9be10 | 187 | |
cef3d92c | 188 | /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ |
d196483d | 189 | aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE | |
1a5a954c | 190 | L310_AUX_CTRL_DATA_PREFETCH | |
36bccb11 | 191 | L310_AUX_CTRL_INSTR_PREFETCH; |
1773e60a | 192 | |
36827edd | 193 | outer_cache.write_sec = omap4_l2c310_write_sec; |
926fd45b | 194 | if (of_have_populated_dt()) |
d196483d | 195 | l2x0_of_init(aux_ctrl, 0xcf9fffff); |
926fd45b | 196 | else |
d196483d | 197 | l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff); |
4e803c40 | 198 | |
fbc9be10 SS |
199 | return 0; |
200 | } | |
fbc9be10 | 201 | #endif |
501f0c75 SS |
202 | |
203 | void __iomem *omap4_get_sar_ram_base(void) | |
204 | { | |
205 | return sar_ram_base; | |
206 | } | |
207 | ||
208 | /* | |
209 | * SAR RAM used to save and restore the HW | |
210 | * context in low power modes | |
211 | */ | |
212 | static int __init omap4_sar_ram_init(void) | |
213 | { | |
da0e02a1 SS |
214 | unsigned long sar_base; |
215 | ||
501f0c75 SS |
216 | /* |
217 | * To avoid code running on other OMAPs in | |
218 | * multi-omap builds | |
219 | */ | |
da0e02a1 SS |
220 | if (cpu_is_omap44xx()) |
221 | sar_base = OMAP44XX_SAR_RAM_BASE; | |
222 | else if (soc_is_omap54xx()) | |
223 | sar_base = OMAP54XX_SAR_RAM_BASE; | |
224 | else | |
501f0c75 SS |
225 | return -ENOMEM; |
226 | ||
227 | /* Static mapping, never released */ | |
da0e02a1 | 228 | sar_ram_base = ioremap(sar_base, SZ_16K); |
501f0c75 SS |
229 | if (WARN_ON(!sar_ram_base)) |
230 | return -ENOMEM; | |
231 | ||
232 | return 0; | |
233 | } | |
b76c8b19 | 234 | omap_early_initcall(omap4_sar_ram_init); |
1ee47b0a | 235 | |
c4082d49 S |
236 | void __init omap_gic_of_init(void) |
237 | { | |
fd1c0786 SS |
238 | struct device_node *np; |
239 | ||
240 | /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ | |
241 | if (!cpu_is_omap446x()) | |
242 | goto skip_errata_init; | |
243 | ||
244 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); | |
245 | gic_dist_base_addr = of_iomap(np, 0); | |
246 | WARN_ON(!gic_dist_base_addr); | |
247 | ||
248 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); | |
249 | twd_base = of_iomap(np, 0); | |
250 | WARN_ON(!twd_base); | |
251 | ||
252 | skip_errata_init: | |
c4082d49 | 253 | omap_wakeupgen_init(); |
5c61e619 S |
254 | #ifdef CONFIG_IRQ_CROSSBAR |
255 | irqcrossbar_init(); | |
256 | #endif | |
0529e315 | 257 | irqchip_init(); |
c4082d49 | 258 | } |