[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>

#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>

#include "omap-wakeupgen.h"
#include "soc.h"
#include "common.h"
#include "mmc.h"
#include "hsmmc.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void __init gic_init_irq(void)
{
	void __iomem *omap_irq_base;
	void __iomem *gic_dist_base_addr;

	/* Static mapping, never released */
	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	BUG_ON(!gic_dist_base_addr);

	/* Static mapping, never released */
	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
	BUG_ON(!omap_irq_base);

	omap_wakeupgen_init();

	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2x0_disable(void)
{
	/* Disable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x0);
}

static void omap4_l2x0_set_debug(unsigned long val)
{
	/* Program PL310 L2 Cache controller debug register */
	omap_smc1(0x100, val);
}

static int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl = 0;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/*
	 * 16-way associativity, parity disabled
	 * Way size - 32KB (es1.0)
	 * Way size - 64KB (es2.0 +)
	 */
	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
			(0x1 << 25) |
			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
	} else {
		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
	}
	if (omap_rev() != OMAP4430_REV_ES1_0)
		omap_smc1(0x109, aux_ctrl);

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	if (of_have_populated_dt())
		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	else
		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);

	/*
	 * Override default outer_cache.disable with a OMAP4
	 * specific one
	*/
	outer_cache.disable = omap4_l2x0_disable;
	outer_cache.set_debug = omap4_l2x0_set_debug;

	return 0;
}
early_initcall(omap_l2_cache_init);
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
early_initcall(omap4_sar_ram_init);

static struct of_device_id irq_match[] __initdata = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
	{ }
};

void __init omap_gic_of_init(void)
{
	omap_wakeupgen_init();
	of_irq_init(irq_match);
}

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
	int irq = 0;
	struct platform_device *pdev = container_of(dev,
				struct platform_device, dev);
	struct omap_mmc_platform_data *pdata = dev->platform_data;

	/* Setting MMC1 Card detect Irq */
	if (pdev->id == 0) {
		irq = twl6030_mmc_card_detect_config();
		if (irq < 0) {
			dev_err(dev, "%s: Error card detect config(%d)\n",
				__func__, irq);
			return irq;
		}
		pdata->slots[0].card_detect_irq = irq;
		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	}
	return 0;
}

static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
{
	struct omap_mmc_platform_data *pdata;

	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	if (!dev) {
		pr_err("Failed %s\n", __func__);
		return;
	}
	pdata = dev->platform_data;
	pdata->init =	omap4_twl6030_hsmmc_late_init;
}

int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;

	omap_hsmmc_init(controllers);
	for (c = controllers; c->mmc; c++) {
		/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
		if (!c->pdev)
			continue;
		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	}

	return 0;
}
#else
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	return 0;
}
#endif
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/platform_device.h>
137d105d	18	#include <linux/memblock.h>
7d7e1eba TL	19	#include <linux/of_irq.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/export.h>
fbc9be10 SS	22
	23	#include <asm/hardware/gic.h>
	24	#include <asm/hardware/cache-l2x0.h>
137d105d	25	#include <asm/mach/map.h>
716a3dc2	26	#include <asm/memblock.h>
fbc9be10	27
622297fd	28	#include "omap-wakeupgen.h"
dbc04161	29	#include "soc.h"
4e65331c	30	#include "common.h"
68f39e74	31	#include "mmc.h"
1ee47b0a	32	#include "hsmmc.h"
501f0c75	33	#include "omap4-sar-layout.h"
f7a9b8a1	34	#include "omap-secure.h"
fbc9be10 SS	35
fbc9be10 SS	36	#ifdef CONFIG_CACHE_L2X0
02afe8a7	37	static void __iomem *l2cache_base;
fbc9be10 SS	38	#endif
fbc9be10 SS	39
501f0c75 SS	40	static void __iomem *sar_ram_base;
501f0c75 SS	41
137d105d SS	42	#ifdef CONFIG_OMAP4_ERRATA_I688
	43	/* Used to implement memory barrier on DRAM path */
	44	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	45
	46	void __iomem dram_sync, sram_sync;
	47
2ec1fc4e SS	48	static phys_addr_t paddr;
	49	static u32 size;
	50
137d105d SS	51	void omap_bus_sync(void)
	52	{
	53	if (dram_sync && sram_sync) {
	54	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	55	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	56	isb();
	57	}
	58	}
cc4ad907	59	EXPORT_SYMBOL(omap_bus_sync);
137d105d	60
2ec1fc4e SS	61	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	62	int __init omap_barrier_reserve_memblock(void)
137d105d	63	{
137d105d SS	64
137d105d SS	65	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	66	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	67
2ec1fc4e SS	68	return 0;
	69	}
	70
	71	void __init omap_barriers_init(void)
	72	{
	73	struct map_desc dram_io_desc[1];
	74
137d105d SS	75	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	76	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	77	dram_io_desc[0].length = size;
	78	dram_io_desc[0].type = MT_MEMORY_SO;
	79	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	80	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	81	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	82
	83	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	84	(long long) paddr, dram_io_desc[0].virtual);
	85
137d105d	86	}
2ec1fc4e SS	87	#else
	88	void __init omap_barriers_init(void)
	89	{}
137d105d SS	90	#endif
137d105d SS	91
fbc9be10 SS	92	void __init gic_init_irq(void)
fbc9be10 SS	93	{
ab65be26 MZ	94	void __iomem *omap_irq_base;
	95	void __iomem *gic_dist_base_addr;
	96
fbc9be10 SS	97	/* Static mapping, never released */
	98	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	99	BUG_ON(!gic_dist_base_addr);
fbc9be10 SS	100
fbc9be10 SS	101	/* Static mapping, never released */
741e3a89 TL	102	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
741e3a89 TL	103	BUG_ON(!omap_irq_base);
b580b899	104
fcf6efa3 SS	105	omap_wakeupgen_init();
fcf6efa3 SS	106
741e3a89	107	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
fbc9be10 SS	108	}
	109
	110	#ifdef CONFIG_CACHE_L2X0
4e803c40	111
02afe8a7 SS	112	void __iomem *omap4_get_l2cache_base(void)
	113	{
	114	return l2cache_base;
	115	}
	116
4e803c40 SS	117	static void omap4_l2x0_disable(void)
	118	{
	119	/* Disable PL310 L2 Cache controller */
	120	omap_smc1(0x102, 0x0);
	121	}
	122
4bdb1577 SS	123	static void omap4_l2x0_set_debug(unsigned long val)
	124	{
	125	/* Program PL310 L2 Cache controller debug register */
	126	omap_smc1(0x100, val);
	127	}
	128
fbc9be10 SS	129	static int __init omap_l2_cache_init(void)
fbc9be10 SS	130	{
1773e60a SS	131	u32 aux_ctrl = 0;
1773e60a SS	132
fbc9be10 SS	133	/*
	134	* To avoid code running on other OMAPs in
	135	* multi-omap builds
	136	*/
	137	if (!cpu_is_omap44xx())
	138	return -ENODEV;
	139
	140	/* Static mapping, never released */
	141	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	142	if (WARN_ON(!l2cache_base))
0db1803e SS	143	return -ENOMEM;
fbc9be10	144
fbc9be10	145	/*
a777b727 SS	146	* 16-way associativity, parity disabled
	147	* Way size - 32KB (es1.0)
	148	* Way size - 64KB (es2.0 +)
fbc9be10	149	*/
1773e60a SS	150	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
	151	(0x1 << 25) \|
	152	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
	153	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
	154
11e02640	155	if (omap_rev() == OMAP4430_REV_ES1_0) {
1773e60a	156	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
11e02640 MR	157	} else {
11e02640 MR	158	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
b0f20ff9	159	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
11e02640	160	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
b89cd71a SS	161	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
b89cd71a SS	162	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
11e02640 MR	163	}
	164	if (omap_rev() != OMAP4430_REV_ES1_0)
	165	omap_smc1(0x109, aux_ctrl);
	166
	167	/* Enable PL310 L2 Cache controller */
	168	omap_smc1(0x102, 0x1);
1773e60a	169
926fd45b SS	170	if (of_have_populated_dt())
	171	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	172	else
	173	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
fbc9be10	174
4e803c40 SS	175	/*
	176	* Override default outer_cache.disable with a OMAP4
	177	* specific one
	178	*/
	179	outer_cache.disable = omap4_l2x0_disable;
4bdb1577	180	outer_cache.set_debug = omap4_l2x0_set_debug;
4e803c40	181
fbc9be10 SS	182	return 0;
	183	}
	184	early_initcall(omap_l2_cache_init);
	185	#endif
501f0c75 SS	186
	187	void __iomem *omap4_get_sar_ram_base(void)
	188	{
	189	return sar_ram_base;
	190	}
	191
	192	/*
	193	* SAR RAM used to save and restore the HW
	194	* context in low power modes
	195	*/
	196	static int __init omap4_sar_ram_init(void)
	197	{
	198	/*
	199	* To avoid code running on other OMAPs in
	200	* multi-omap builds
	201	*/
	202	if (!cpu_is_omap44xx())
	203	return -ENOMEM;
	204
	205	/* Static mapping, never released */
	206	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	207	if (WARN_ON(!sar_ram_base))
	208	return -ENOMEM;
	209
	210	return 0;
	211	}
	212	early_initcall(omap4_sar_ram_init);
1ee47b0a	213
c4082d49 S	214	static struct of_device_id irq_match[] __initdata = {
c4082d49 S	215	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
0c1b6fac	216	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
c4082d49 S	217	{ }
	218	};
	219
	220	void __init omap_gic_of_init(void)
	221	{
	222	omap_wakeupgen_init();
	223	of_irq_init(irq_match);
	224	}
	225
1ee47b0a B	226	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
	227	static int omap4_twl6030_hsmmc_late_init(struct device *dev)
	228	{
	229	int irq = 0;
	230	struct platform_device *pdev = container_of(dev,
	231	struct platform_device, dev);
	232	struct omap_mmc_platform_data *pdata = dev->platform_data;
	233
	234	/* Setting MMC1 Card detect Irq */
	235	if (pdev->id == 0) {
	236	irq = twl6030_mmc_card_detect_config();
	237	if (irq < 0) {
	238	dev_err(dev, "%s: Error card detect config(%d)\n",
	239	__func__, irq);
	240	return irq;
	241	}
	242	pdata->slots[0].card_detect_irq = irq;
	243	pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	244	}
	245	return 0;
	246	}
	247
	248	static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
	249	{
	250	struct omap_mmc_platform_data *pdata;
	251
	252	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	253	if (!dev) {
	254	pr_err("Failed %s\n", __func__);
	255	return;
	256	}
	257	pdata = dev->platform_data;
	258	pdata->init = omap4_twl6030_hsmmc_late_init;
	259	}
	260
	261	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	262	{
	263	struct omap2_hsmmc_info *c;
	264
	265	omap_hsmmc_init(controllers);
	266	for (c = controllers; c->mmc; c++) {
	267	/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
	268	if (!c->pdev)
	269	continue;
	270	omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	271	}
	272
	273	return 0;
	274	}
	275	#else
	276	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	277	{
	278	return 0;
	279	}
	280	#endif