Commit | Line | Data |
---|---|---|
63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
63c85238 | 140 | |
4e65331c | 141 | #include "common.h" |
ce491cf8 | 142 | #include <plat/cpu.h> |
1540f214 | 143 | #include "clockdomain.h" |
72e06d08 | 144 | #include "powerdomain.h" |
ce491cf8 TL |
145 | #include <plat/clock.h> |
146 | #include <plat/omap_hwmod.h> | |
5365efbe | 147 | #include <plat/prcm.h> |
63c85238 | 148 | |
59fb659b | 149 | #include "cm2xxx_3xxx.h" |
d0f0631d | 150 | #include "cminst44xx.h" |
59fb659b | 151 | #include "prm2xxx_3xxx.h" |
d198b514 | 152 | #include "prm44xx.h" |
eaac329d | 153 | #include "prminst44xx.h" |
8d9af88f | 154 | #include "mux.h" |
63c85238 | 155 | |
5365efbe BC |
156 | /* Maximum microseconds to wait for OMAP module to softreset */ |
157 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
158 | |
159 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 160 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
161 | |
162 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
163 | static LIST_HEAD(omap_hwmod_list); | |
164 | ||
63c85238 PW |
165 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
166 | static struct omap_hwmod *mpu_oh; | |
167 | ||
63c85238 PW |
168 | |
169 | /* Private functions */ | |
170 | ||
5d95dde7 PW |
171 | /** |
172 | * _fetch_next_ocp_if - return @i'th OCP interface in an array | |
173 | * @p: ptr to a ptr to the list_head inside the ocp_if to return (not yet used) | |
174 | * @old: ptr to an array of struct omap_hwmod_ocp_if records | |
175 | * @i: pointer to the index into the @old array | |
176 | * | |
177 | * Return a pointer to the next struct omap_hwmod_ocp_if record in a | |
178 | * sequence. Currently returns a struct omap_hwmod_ocp_if record | |
179 | * corresponding to the element index pointed to by @i in the @old | |
180 | * array, and increments the index pointed to by @i. | |
181 | */ | |
182 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
183 | struct omap_hwmod_ocp_if **old, | |
184 | int *i) | |
185 | { | |
186 | struct omap_hwmod_ocp_if *oi; | |
187 | ||
188 | oi = old[*i]; | |
189 | *i = *i + 1; | |
190 | ||
191 | return oi; | |
192 | } | |
193 | ||
63c85238 PW |
194 | /** |
195 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
196 | * @oh: struct omap_hwmod * | |
197 | * | |
198 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
199 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
200 | * OCP_SYSCONFIG register or 0 upon success. | |
201 | */ | |
202 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
203 | { | |
43b40992 PW |
204 | if (!oh->class->sysc) { |
205 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
206 | return -EINVAL; |
207 | } | |
208 | ||
209 | /* XXX ensure module interface clock is up */ | |
210 | ||
cc7a1d2a | 211 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 212 | |
43b40992 | 213 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 214 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
215 | |
216 | return 0; | |
217 | } | |
218 | ||
219 | /** | |
220 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
221 | * @v: OCP_SYSCONFIG value to write | |
222 | * @oh: struct omap_hwmod * | |
223 | * | |
43b40992 PW |
224 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
225 | * one. No return value. | |
63c85238 PW |
226 | */ |
227 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
228 | { | |
43b40992 PW |
229 | if (!oh->class->sysc) { |
230 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
231 | return; |
232 | } | |
233 | ||
234 | /* XXX ensure module interface clock is up */ | |
235 | ||
233cbe5b RN |
236 | /* Module might have lost context, always update cache and register */ |
237 | oh->_sysc_cache = v; | |
238 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
239 | } |
240 | ||
241 | /** | |
242 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
243 | * @oh: struct omap_hwmod * | |
244 | * @standbymode: MIDLEMODE field bits | |
245 | * @v: pointer to register contents to modify | |
246 | * | |
247 | * Update the master standby mode bits in @v to be @standbymode for | |
248 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
249 | * upon error or 0 upon success. | |
250 | */ | |
251 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
252 | u32 *v) | |
253 | { | |
358f0e63 TG |
254 | u32 mstandby_mask; |
255 | u8 mstandby_shift; | |
256 | ||
43b40992 PW |
257 | if (!oh->class->sysc || |
258 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
259 | return -EINVAL; |
260 | ||
43b40992 PW |
261 | if (!oh->class->sysc->sysc_fields) { |
262 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
263 | return -EINVAL; |
264 | } | |
265 | ||
43b40992 | 266 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
267 | mstandby_mask = (0x3 << mstandby_shift); |
268 | ||
269 | *v &= ~mstandby_mask; | |
270 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
275 | /** | |
276 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
277 | * @oh: struct omap_hwmod * | |
278 | * @idlemode: SIDLEMODE field bits | |
279 | * @v: pointer to register contents to modify | |
280 | * | |
281 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
282 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
283 | * or 0 upon success. | |
284 | */ | |
285 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
286 | { | |
358f0e63 TG |
287 | u32 sidle_mask; |
288 | u8 sidle_shift; | |
289 | ||
43b40992 PW |
290 | if (!oh->class->sysc || |
291 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
292 | return -EINVAL; |
293 | ||
43b40992 PW |
294 | if (!oh->class->sysc->sysc_fields) { |
295 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
296 | return -EINVAL; |
297 | } | |
298 | ||
43b40992 | 299 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
300 | sidle_mask = (0x3 << sidle_shift); |
301 | ||
302 | *v &= ~sidle_mask; | |
303 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /** | |
309 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
310 | * @oh: struct omap_hwmod * | |
311 | * @clockact: CLOCKACTIVITY field bits | |
312 | * @v: pointer to register contents to modify | |
313 | * | |
314 | * Update the clockactivity mode bits in @v to be @clockact for the | |
315 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
316 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
317 | * success. | |
318 | */ | |
319 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
320 | { | |
358f0e63 TG |
321 | u32 clkact_mask; |
322 | u8 clkact_shift; | |
323 | ||
43b40992 PW |
324 | if (!oh->class->sysc || |
325 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
326 | return -EINVAL; |
327 | ||
43b40992 PW |
328 | if (!oh->class->sysc->sysc_fields) { |
329 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
330 | return -EINVAL; |
331 | } | |
332 | ||
43b40992 | 333 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
334 | clkact_mask = (0x3 << clkact_shift); |
335 | ||
336 | *v &= ~clkact_mask; | |
337 | *v |= clockact << clkact_shift; | |
63c85238 PW |
338 | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /** | |
343 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
344 | * @oh: struct omap_hwmod * | |
345 | * @v: pointer to register contents to modify | |
346 | * | |
347 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
348 | * error or 0 upon success. | |
349 | */ | |
350 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
351 | { | |
358f0e63 TG |
352 | u32 softrst_mask; |
353 | ||
43b40992 PW |
354 | if (!oh->class->sysc || |
355 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
356 | return -EINVAL; |
357 | ||
43b40992 PW |
358 | if (!oh->class->sysc->sysc_fields) { |
359 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
360 | return -EINVAL; |
361 | } | |
362 | ||
43b40992 | 363 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
364 | |
365 | *v |= softrst_mask; | |
63c85238 PW |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
726072e5 PW |
370 | /** |
371 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
372 | * @oh: struct omap_hwmod * | |
373 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
374 | * @v: pointer to register contents to modify | |
375 | * | |
376 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
377 | * hwmod. The autoidle bit controls whether the module can gate | |
378 | * internal clocks automatically when it isn't doing anything; the | |
379 | * exact function of this bit varies on a per-module basis. This | |
380 | * function does not write to the hardware. Returns -EINVAL upon | |
381 | * error or 0 upon success. | |
382 | */ | |
383 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
384 | u32 *v) | |
385 | { | |
358f0e63 TG |
386 | u32 autoidle_mask; |
387 | u8 autoidle_shift; | |
388 | ||
43b40992 PW |
389 | if (!oh->class->sysc || |
390 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
391 | return -EINVAL; |
392 | ||
43b40992 PW |
393 | if (!oh->class->sysc->sysc_fields) { |
394 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
395 | return -EINVAL; |
396 | } | |
397 | ||
43b40992 | 398 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 399 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
400 | |
401 | *v &= ~autoidle_mask; | |
402 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
403 | |
404 | return 0; | |
405 | } | |
406 | ||
eceec009 G |
407 | /** |
408 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
409 | * @oh: struct omap_hwmod * | |
410 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
411 | * | |
412 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
413 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
414 | * in memory. If the hwmod is currently idled, and the new idle | |
415 | * values don't match the previous ones, this function will also | |
416 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
417 | * currently idled, this function won't touch the hardware: the new | |
418 | * mux settings are written to the SCM PADCTRL registers when the | |
419 | * hwmod is idled. No return value. | |
420 | */ | |
421 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
422 | { | |
423 | struct omap_device_pad *pad; | |
424 | bool change = false; | |
425 | u16 prev_idle; | |
426 | int j; | |
427 | ||
428 | if (!oh->mux || !oh->mux->enabled) | |
429 | return; | |
430 | ||
431 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
432 | pad = oh->mux->pads_dynamic[j]; | |
433 | ||
434 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
435 | continue; | |
436 | ||
437 | prev_idle = pad->idle; | |
438 | ||
439 | if (set_wake) | |
440 | pad->idle |= OMAP_WAKEUP_EN; | |
441 | else | |
442 | pad->idle &= ~OMAP_WAKEUP_EN; | |
443 | ||
444 | if (prev_idle != pad->idle) | |
445 | change = true; | |
446 | } | |
447 | ||
448 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
449 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
450 | } | |
451 | ||
63c85238 PW |
452 | /** |
453 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
454 | * @oh: struct omap_hwmod * | |
455 | * | |
456 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
457 | * upon error or 0 upon success. | |
458 | */ | |
5a7ddcbd | 459 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 460 | { |
43b40992 | 461 | if (!oh->class->sysc || |
86009eb3 | 462 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
463 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
464 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
465 | return -EINVAL; |
466 | ||
43b40992 PW |
467 | if (!oh->class->sysc->sysc_fields) { |
468 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
469 | return -EINVAL; |
470 | } | |
471 | ||
1fe74113 BC |
472 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
473 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 474 | |
86009eb3 BC |
475 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
476 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
477 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
478 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 479 | |
63c85238 PW |
480 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
481 | ||
482 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | /** | |
488 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
489 | * @oh: struct omap_hwmod * | |
490 | * | |
491 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
492 | * upon error or 0 upon success. | |
493 | */ | |
5a7ddcbd | 494 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 495 | { |
43b40992 | 496 | if (!oh->class->sysc || |
86009eb3 | 497 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
498 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
499 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
500 | return -EINVAL; |
501 | ||
43b40992 PW |
502 | if (!oh->class->sysc->sysc_fields) { |
503 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
504 | return -EINVAL; |
505 | } | |
506 | ||
1fe74113 BC |
507 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
508 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 509 | |
86009eb3 BC |
510 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
511 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 BC |
512 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
513 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 514 | |
63c85238 PW |
515 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
516 | ||
517 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | /** | |
523 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
524 | * @oh: struct omap_hwmod * | |
525 | * | |
526 | * Prevent the hardware module @oh from entering idle while the | |
527 | * hardare module initiator @init_oh is active. Useful when a module | |
528 | * will be accessed by a particular initiator (e.g., if a module will | |
529 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
530 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
531 | * mode. If the clockdomain is marked as not needing autodeps, return |
532 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
533 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
534 | */ |
535 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
536 | { | |
537 | if (!oh->_clk) | |
538 | return -EINVAL; | |
539 | ||
570b54c7 PW |
540 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
541 | return 0; | |
542 | ||
55ed9694 | 543 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
544 | } |
545 | ||
546 | /** | |
547 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
548 | * @oh: struct omap_hwmod * | |
549 | * | |
550 | * Allow the hardware module @oh to enter idle while the hardare | |
551 | * module initiator @init_oh is active. Useful when a module will not | |
552 | * be accessed by a particular initiator (e.g., if a module will not | |
553 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
554 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
555 | * mode. If the clockdomain is marked as not needing autodeps, return |
556 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
557 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
558 | */ |
559 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
560 | { | |
561 | if (!oh->_clk) | |
562 | return -EINVAL; | |
563 | ||
570b54c7 PW |
564 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
565 | return 0; | |
566 | ||
55ed9694 | 567 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
568 | } |
569 | ||
570 | /** | |
571 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
572 | * @oh: struct omap_hwmod * | |
573 | * | |
574 | * Called from _init_clocks(). Populates the @oh _clk (main | |
575 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
576 | * success or -EINVAL on error. | |
577 | */ | |
578 | static int _init_main_clk(struct omap_hwmod *oh) | |
579 | { | |
63c85238 PW |
580 | int ret = 0; |
581 | ||
50ebdac2 | 582 | if (!oh->main_clk) |
63c85238 PW |
583 | return 0; |
584 | ||
63403384 | 585 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 586 | if (!oh->_clk) { |
20383d82 BC |
587 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
588 | oh->name, oh->main_clk); | |
63403384 | 589 | return -EINVAL; |
dc75925d | 590 | } |
63c85238 | 591 | |
63403384 BC |
592 | if (!oh->_clk->clkdm) |
593 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
594 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 595 | |
63c85238 PW |
596 | return ret; |
597 | } | |
598 | ||
599 | /** | |
887adeac | 600 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
601 | * @oh: struct omap_hwmod * |
602 | * | |
603 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
604 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
605 | */ | |
606 | static int _init_interface_clks(struct omap_hwmod *oh) | |
607 | { | |
5d95dde7 | 608 | struct omap_hwmod_ocp_if *os; |
63c85238 | 609 | struct clk *c; |
5d95dde7 | 610 | int i = 0; |
63c85238 PW |
611 | int ret = 0; |
612 | ||
5d95dde7 PW |
613 | while (i < oh->slaves_cnt) { |
614 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
50ebdac2 | 615 | if (!os->clk) |
63c85238 PW |
616 | continue; |
617 | ||
50ebdac2 | 618 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 619 | if (!c) { |
20383d82 BC |
620 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
621 | oh->name, os->clk); | |
63c85238 | 622 | ret = -EINVAL; |
dc75925d | 623 | } |
63c85238 PW |
624 | os->_clk = c; |
625 | } | |
626 | ||
627 | return ret; | |
628 | } | |
629 | ||
630 | /** | |
631 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
632 | * @oh: struct omap_hwmod * | |
633 | * | |
634 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
635 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
636 | */ | |
637 | static int _init_opt_clks(struct omap_hwmod *oh) | |
638 | { | |
639 | struct omap_hwmod_opt_clk *oc; | |
640 | struct clk *c; | |
641 | int i; | |
642 | int ret = 0; | |
643 | ||
644 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 645 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 646 | if (!c) { |
20383d82 BC |
647 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
648 | oh->name, oc->clk); | |
63c85238 | 649 | ret = -EINVAL; |
dc75925d | 650 | } |
63c85238 PW |
651 | oc->_clk = c; |
652 | } | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
657 | /** | |
658 | * _enable_clocks - enable hwmod main clock and interface clocks | |
659 | * @oh: struct omap_hwmod * | |
660 | * | |
661 | * Enables all clocks necessary for register reads and writes to succeed | |
662 | * on the hwmod @oh. Returns 0. | |
663 | */ | |
664 | static int _enable_clocks(struct omap_hwmod *oh) | |
665 | { | |
5d95dde7 PW |
666 | struct omap_hwmod_ocp_if *os; |
667 | int i = 0; | |
63c85238 PW |
668 | |
669 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
670 | ||
4d3ae5a9 | 671 | if (oh->_clk) |
63c85238 PW |
672 | clk_enable(oh->_clk); |
673 | ||
5d95dde7 PW |
674 | while (i < oh->slaves_cnt) { |
675 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
63c85238 | 676 | |
5d95dde7 PW |
677 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
678 | clk_enable(os->_clk); | |
63c85238 PW |
679 | } |
680 | ||
681 | /* The opt clocks are controlled by the device driver. */ | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | /** | |
687 | * _disable_clocks - disable hwmod main clock and interface clocks | |
688 | * @oh: struct omap_hwmod * | |
689 | * | |
690 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
691 | */ | |
692 | static int _disable_clocks(struct omap_hwmod *oh) | |
693 | { | |
5d95dde7 PW |
694 | struct omap_hwmod_ocp_if *os; |
695 | int i = 0; | |
63c85238 PW |
696 | |
697 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
698 | ||
4d3ae5a9 | 699 | if (oh->_clk) |
63c85238 PW |
700 | clk_disable(oh->_clk); |
701 | ||
5d95dde7 PW |
702 | while (i < oh->slaves_cnt) { |
703 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
63c85238 | 704 | |
5d95dde7 PW |
705 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
706 | clk_disable(os->_clk); | |
63c85238 PW |
707 | } |
708 | ||
709 | /* The opt clocks are controlled by the device driver. */ | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
96835af9 BC |
714 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
715 | { | |
716 | struct omap_hwmod_opt_clk *oc; | |
717 | int i; | |
718 | ||
719 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
720 | ||
721 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
722 | if (oc->_clk) { | |
723 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
724 | oc->_clk->name); | |
725 | clk_enable(oc->_clk); | |
726 | } | |
727 | } | |
728 | ||
729 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
730 | { | |
731 | struct omap_hwmod_opt_clk *oc; | |
732 | int i; | |
733 | ||
734 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
735 | ||
736 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
737 | if (oc->_clk) { | |
738 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
739 | oc->_clk->name); | |
740 | clk_disable(oc->_clk); | |
741 | } | |
742 | } | |
743 | ||
45c38252 BC |
744 | /** |
745 | * _enable_module - enable CLKCTRL modulemode on OMAP4 | |
746 | * @oh: struct omap_hwmod * | |
747 | * | |
748 | * Enables the PRCM module mode related to the hwmod @oh. | |
749 | * No return value. | |
750 | */ | |
751 | static void _enable_module(struct omap_hwmod *oh) | |
752 | { | |
753 | /* The module mode does not exist prior OMAP4 */ | |
754 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
755 | return; | |
756 | ||
757 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
758 | return; | |
759 | ||
760 | pr_debug("omap_hwmod: %s: _enable_module: %d\n", | |
761 | oh->name, oh->prcm.omap4.modulemode); | |
762 | ||
763 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
764 | oh->clkdm->prcm_partition, | |
765 | oh->clkdm->cm_inst, | |
766 | oh->clkdm->clkdm_offs, | |
767 | oh->prcm.omap4.clkctrl_offs); | |
768 | } | |
769 | ||
770 | /** | |
bfc141e3 BC |
771 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
772 | * @oh: struct omap_hwmod * | |
773 | * | |
774 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
775 | * does not have an IDLEST bit or if the module successfully enters | |
776 | * slave idle; otherwise, pass along the return value of the | |
777 | * appropriate *_cm*_wait_module_idle() function. | |
778 | */ | |
779 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
780 | { | |
781 | if (!cpu_is_omap44xx()) | |
782 | return 0; | |
783 | ||
784 | if (!oh) | |
785 | return -EINVAL; | |
786 | ||
787 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
788 | return 0; | |
789 | ||
790 | if (oh->flags & HWMOD_NO_IDLEST) | |
791 | return 0; | |
792 | ||
793 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
794 | oh->clkdm->cm_inst, | |
795 | oh->clkdm->clkdm_offs, | |
796 | oh->prcm.omap4.clkctrl_offs); | |
797 | } | |
798 | ||
212738a4 PW |
799 | /** |
800 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
801 | * @oh: struct omap_hwmod *oh | |
802 | * | |
803 | * Count and return the number of MPU IRQs associated with the hwmod | |
804 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
805 | * NULL. | |
806 | */ | |
807 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
808 | { | |
809 | struct omap_hwmod_irq_info *ohii; | |
810 | int i = 0; | |
811 | ||
812 | if (!oh || !oh->mpu_irqs) | |
813 | return 0; | |
814 | ||
815 | do { | |
816 | ohii = &oh->mpu_irqs[i++]; | |
817 | } while (ohii->irq != -1); | |
818 | ||
cc1b0765 | 819 | return i-1; |
212738a4 PW |
820 | } |
821 | ||
bc614958 PW |
822 | /** |
823 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
824 | * @oh: struct omap_hwmod *oh | |
825 | * | |
826 | * Count and return the number of SDMA request lines associated with | |
827 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
828 | * if @oh is NULL. | |
829 | */ | |
830 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
831 | { | |
832 | struct omap_hwmod_dma_info *ohdi; | |
833 | int i = 0; | |
834 | ||
835 | if (!oh || !oh->sdma_reqs) | |
836 | return 0; | |
837 | ||
838 | do { | |
839 | ohdi = &oh->sdma_reqs[i++]; | |
840 | } while (ohdi->dma_req != -1); | |
841 | ||
cc1b0765 | 842 | return i-1; |
bc614958 PW |
843 | } |
844 | ||
78183f3f PW |
845 | /** |
846 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
847 | * @oh: struct omap_hwmod *oh | |
848 | * | |
849 | * Count and return the number of address space ranges associated with | |
850 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
851 | * if @oh is NULL. | |
852 | */ | |
853 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
854 | { | |
855 | struct omap_hwmod_addr_space *mem; | |
856 | int i = 0; | |
857 | ||
858 | if (!os || !os->addr) | |
859 | return 0; | |
860 | ||
861 | do { | |
862 | mem = &os->addr[i++]; | |
863 | } while (mem->pa_start != mem->pa_end); | |
864 | ||
cc1b0765 | 865 | return i-1; |
78183f3f PW |
866 | } |
867 | ||
5e8370f1 PW |
868 | /** |
869 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
870 | * @oh: struct omap_hwmod * to operate on | |
871 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
872 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
873 | * | |
874 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
875 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
876 | * into the address pointed to by @dma. When @name is non-null, the | |
877 | * IRQ line number associated with the named entry will be returned. | |
878 | * If @name is null, the first matching entry will be returned. Data | |
879 | * order is not meaningful in hwmod data, so callers are strongly | |
880 | * encouraged to use a non-null @name whenever possible to avoid | |
881 | * unpredictable effects if hwmod data is later added that causes data | |
882 | * ordering to change. Returns 0 upon success or a negative error | |
883 | * code upon error. | |
884 | */ | |
885 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
886 | unsigned int *irq) | |
887 | { | |
888 | int i; | |
889 | bool found = false; | |
890 | ||
891 | if (!oh->mpu_irqs) | |
892 | return -ENOENT; | |
893 | ||
894 | i = 0; | |
895 | while (oh->mpu_irqs[i].irq != -1) { | |
896 | if (name == oh->mpu_irqs[i].name || | |
897 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
898 | found = true; | |
899 | break; | |
900 | } | |
901 | i++; | |
902 | } | |
903 | ||
904 | if (!found) | |
905 | return -ENOENT; | |
906 | ||
907 | *irq = oh->mpu_irqs[i].irq; | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
914 | * @oh: struct omap_hwmod * to operate on | |
915 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
916 | * @dma: pointer to an unsigned int to store the request line ID to | |
917 | * | |
918 | * Retrieve an SDMA request line ID named by @name on the IP block | |
919 | * pointed to by @oh. The ID will be filled into the address pointed | |
920 | * to by @dma. When @name is non-null, the request line ID associated | |
921 | * with the named entry will be returned. If @name is null, the first | |
922 | * matching entry will be returned. Data order is not meaningful in | |
923 | * hwmod data, so callers are strongly encouraged to use a non-null | |
924 | * @name whenever possible to avoid unpredictable effects if hwmod | |
925 | * data is later added that causes data ordering to change. Returns 0 | |
926 | * upon success or a negative error code upon error. | |
927 | */ | |
928 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
929 | unsigned int *dma) | |
930 | { | |
931 | int i; | |
932 | bool found = false; | |
933 | ||
934 | if (!oh->sdma_reqs) | |
935 | return -ENOENT; | |
936 | ||
937 | i = 0; | |
938 | while (oh->sdma_reqs[i].dma_req != -1) { | |
939 | if (name == oh->sdma_reqs[i].name || | |
940 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
941 | found = true; | |
942 | break; | |
943 | } | |
944 | i++; | |
945 | } | |
946 | ||
947 | if (!found) | |
948 | return -ENOENT; | |
949 | ||
950 | *dma = oh->sdma_reqs[i].dma_req; | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | /** | |
956 | * _get_addr_space_by_name - fetch address space start & end by name | |
957 | * @oh: struct omap_hwmod * to operate on | |
958 | * @name: pointer to the name of the address space to fetch (optional) | |
959 | * @pa_start: pointer to a u32 to store the starting address to | |
960 | * @pa_end: pointer to a u32 to store the ending address to | |
961 | * | |
962 | * Retrieve address space start and end addresses for the IP block | |
963 | * pointed to by @oh. The data will be filled into the addresses | |
964 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
965 | * address space data associated with the named entry will be | |
966 | * returned. If @name is null, the first matching entry will be | |
967 | * returned. Data order is not meaningful in hwmod data, so callers | |
968 | * are strongly encouraged to use a non-null @name whenever possible | |
969 | * to avoid unpredictable effects if hwmod data is later added that | |
970 | * causes data ordering to change. Returns 0 upon success or a | |
971 | * negative error code upon error. | |
972 | */ | |
973 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
974 | u32 *pa_start, u32 *pa_end) | |
975 | { | |
976 | int i, j; | |
977 | struct omap_hwmod_ocp_if *os; | |
978 | bool found = false; | |
979 | ||
5d95dde7 PW |
980 | i = 0; |
981 | while (i < oh->slaves_cnt) { | |
982 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
5e8370f1 PW |
983 | |
984 | if (!os->addr) | |
985 | return -ENOENT; | |
986 | ||
987 | j = 0; | |
988 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
989 | if (name == os->addr[j].name || | |
990 | !strcmp(name, os->addr[j].name)) { | |
991 | found = true; | |
992 | break; | |
993 | } | |
994 | j++; | |
995 | } | |
996 | ||
997 | if (found) | |
998 | break; | |
999 | } | |
1000 | ||
1001 | if (!found) | |
1002 | return -ENOENT; | |
1003 | ||
1004 | *pa_start = os->addr[j].pa_start; | |
1005 | *pa_end = os->addr[j].pa_end; | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
63c85238 PW |
1010 | /** |
1011 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
1012 | * @oh: struct omap_hwmod * | |
1013 | * | |
1014 | * Returns the array index of the OCP slave port that the MPU | |
1015 | * addresses the device on, or -EINVAL upon error or not found. | |
1016 | */ | |
01592df9 | 1017 | static int __init _find_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1018 | { |
5d95dde7 PW |
1019 | struct omap_hwmod_ocp_if *os; |
1020 | int i = 0; | |
63c85238 PW |
1021 | int found = 0; |
1022 | ||
5d95dde7 | 1023 | if (!oh) |
63c85238 PW |
1024 | return -EINVAL; |
1025 | ||
5d95dde7 PW |
1026 | while (i < oh->slaves_cnt) { |
1027 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
63c85238 PW |
1028 | if (os->user & OCP_USER_MPU) { |
1029 | found = 1; | |
1030 | break; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | if (found) | |
1035 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
5d95dde7 | 1036 | oh->name, i - 1); |
63c85238 PW |
1037 | else |
1038 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
1039 | oh->name); | |
1040 | ||
5d95dde7 | 1041 | return (found) ? (i - 1) : -EINVAL; |
63c85238 PW |
1042 | } |
1043 | ||
2d6141ba PW |
1044 | /** |
1045 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1046 | * @oh: struct omap_hwmod * | |
1047 | * | |
1048 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1049 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1050 | * communicate with the IP block. This interface need not be directly | |
1051 | * connected to the MPU (and almost certainly is not), but is directly | |
1052 | * connected to the IP block represented by @oh. Returns a pointer | |
1053 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1054 | * error or if there does not appear to be a path from the MPU to this | |
1055 | * IP block. | |
1056 | */ | |
1057 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1058 | { | |
1059 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1060 | return NULL; | |
1061 | ||
1062 | return oh->slaves[oh->_mpu_port_index]; | |
1063 | }; | |
1064 | ||
63c85238 | 1065 | /** |
c9aafd23 | 1066 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1067 | * @oh: struct omap_hwmod * |
1068 | * | |
c9aafd23 PW |
1069 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1070 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1071 | */ |
c9aafd23 | 1072 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1073 | { |
1074 | struct omap_hwmod_ocp_if *os; | |
1075 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1076 | int found = 0, i = 0; |
63c85238 | 1077 | |
2d6141ba | 1078 | os = _find_mpu_rt_port(oh); |
78183f3f PW |
1079 | if (!os->addr) |
1080 | return NULL; | |
1081 | ||
1082 | do { | |
1083 | mem = &os->addr[i++]; | |
1084 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1085 | found = 1; |
78183f3f | 1086 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1087 | |
c9aafd23 | 1088 | return (found) ? mem : NULL; |
63c85238 PW |
1089 | } |
1090 | ||
1091 | /** | |
74ff3a68 | 1092 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1093 | * @oh: struct omap_hwmod * |
1094 | * | |
1095 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
1096 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1097 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
1098 | * otherwise, configure it for smart-standby. No return value. | |
1099 | */ | |
74ff3a68 | 1100 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1101 | { |
43b40992 | 1102 | u8 idlemode, sf; |
63c85238 PW |
1103 | u32 v; |
1104 | ||
43b40992 | 1105 | if (!oh->class->sysc) |
63c85238 PW |
1106 | return; |
1107 | ||
1108 | v = oh->_sysc_cache; | |
43b40992 | 1109 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1110 | |
43b40992 | 1111 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
1112 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
1113 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
1114 | _set_slave_idlemode(oh, idlemode, &v); | |
1115 | } | |
1116 | ||
43b40992 | 1117 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1118 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1119 | idlemode = HWMOD_IDLEMODE_NO; | |
1120 | } else { | |
1121 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1122 | _enable_wakeup(oh, &v); | |
1123 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1124 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1125 | else | |
1126 | idlemode = HWMOD_IDLEMODE_SMART; | |
1127 | } | |
63c85238 PW |
1128 | _set_master_standbymode(oh, idlemode, &v); |
1129 | } | |
1130 | ||
a16b1f7f PW |
1131 | /* |
1132 | * XXX The clock framework should handle this, by | |
1133 | * calling into this code. But this must wait until the | |
1134 | * clock structures are tagged with omap_hwmod entries | |
1135 | */ | |
43b40992 PW |
1136 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1137 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1138 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1139 | |
9980ce53 RN |
1140 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1141 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1142 | _enable_wakeup(oh, &v); |
1143 | ||
1144 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1145 | |
1146 | /* | |
1147 | * Set the autoidle bit only after setting the smartidle bit | |
1148 | * Setting this will not have any impact on the other modules. | |
1149 | */ | |
1150 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1151 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1152 | 0 : 1; | |
1153 | _set_module_autoidle(oh, idlemode, &v); | |
1154 | _write_sysconfig(v, oh); | |
1155 | } | |
63c85238 PW |
1156 | } |
1157 | ||
1158 | /** | |
74ff3a68 | 1159 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1160 | * @oh: struct omap_hwmod * |
1161 | * | |
1162 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1163 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1164 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1165 | * configure it for smart-standby. No return value. | |
1166 | */ | |
74ff3a68 | 1167 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1168 | { |
43b40992 | 1169 | u8 idlemode, sf; |
63c85238 PW |
1170 | u32 v; |
1171 | ||
43b40992 | 1172 | if (!oh->class->sysc) |
63c85238 PW |
1173 | return; |
1174 | ||
1175 | v = oh->_sysc_cache; | |
43b40992 | 1176 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1177 | |
43b40992 | 1178 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
1179 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
1180 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
1181 | _set_slave_idlemode(oh, idlemode, &v); | |
1182 | } | |
1183 | ||
43b40992 | 1184 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1185 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1186 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1187 | } else { | |
1188 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1189 | _enable_wakeup(oh, &v); | |
1190 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1191 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1192 | else | |
1193 | idlemode = HWMOD_IDLEMODE_SMART; | |
1194 | } | |
63c85238 PW |
1195 | _set_master_standbymode(oh, idlemode, &v); |
1196 | } | |
1197 | ||
86009eb3 BC |
1198 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1199 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1200 | _enable_wakeup(oh, &v); | |
1201 | ||
63c85238 PW |
1202 | _write_sysconfig(v, oh); |
1203 | } | |
1204 | ||
1205 | /** | |
74ff3a68 | 1206 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1207 | * @oh: struct omap_hwmod * |
1208 | * | |
1209 | * Force the module into slave idle and master suspend. No return | |
1210 | * value. | |
1211 | */ | |
74ff3a68 | 1212 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1213 | { |
1214 | u32 v; | |
43b40992 | 1215 | u8 sf; |
63c85238 | 1216 | |
43b40992 | 1217 | if (!oh->class->sysc) |
63c85238 PW |
1218 | return; |
1219 | ||
1220 | v = oh->_sysc_cache; | |
43b40992 | 1221 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1222 | |
43b40992 | 1223 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1224 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1225 | ||
43b40992 | 1226 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1227 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1228 | ||
43b40992 | 1229 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1230 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1231 | |
1232 | _write_sysconfig(v, oh); | |
1233 | } | |
1234 | ||
1235 | /** | |
1236 | * _lookup - find an omap_hwmod by name | |
1237 | * @name: find an omap_hwmod by name | |
1238 | * | |
1239 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1240 | */ |
1241 | static struct omap_hwmod *_lookup(const char *name) | |
1242 | { | |
1243 | struct omap_hwmod *oh, *temp_oh; | |
1244 | ||
1245 | oh = NULL; | |
1246 | ||
1247 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1248 | if (!strcmp(name, temp_oh->name)) { | |
1249 | oh = temp_oh; | |
1250 | break; | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | return oh; | |
1255 | } | |
6ae76997 BC |
1256 | /** |
1257 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1258 | * @oh: struct omap_hwmod * | |
1259 | * | |
1260 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1261 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
1262 | * return -EINVAL if clkdm_name does not exist or if the lookup failed. | |
1263 | */ | |
1264 | static int _init_clkdm(struct omap_hwmod *oh) | |
1265 | { | |
1266 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1267 | return 0; | |
1268 | ||
1269 | if (!oh->clkdm_name) { | |
1270 | pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name); | |
1271 | return -EINVAL; | |
1272 | } | |
1273 | ||
1274 | oh->clkdm = clkdm_lookup(oh->clkdm_name); | |
1275 | if (!oh->clkdm) { | |
1276 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1277 | oh->name, oh->clkdm_name); | |
1278 | return -EINVAL; | |
1279 | } | |
1280 | ||
1281 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1282 | oh->name, oh->clkdm_name); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
63c85238 PW |
1286 | |
1287 | /** | |
6ae76997 BC |
1288 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1289 | * well the clockdomain. | |
63c85238 | 1290 | * @oh: struct omap_hwmod * |
97d60162 | 1291 | * @data: not used; pass NULL |
63c85238 | 1292 | * |
a2debdbd | 1293 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1294 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1295 | * success, or a negative error code on failure. | |
63c85238 | 1296 | */ |
97d60162 | 1297 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1298 | { |
1299 | int ret = 0; | |
1300 | ||
48d54f3f PW |
1301 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1302 | return 0; | |
63c85238 PW |
1303 | |
1304 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1305 | ||
1306 | ret |= _init_main_clk(oh); | |
1307 | ret |= _init_interface_clks(oh); | |
1308 | ret |= _init_opt_clks(oh); | |
6ae76997 | 1309 | ret |= _init_clkdm(oh); |
63c85238 | 1310 | |
f5c1f84b BC |
1311 | if (!ret) |
1312 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1313 | else |
1314 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1315 | |
09c35f2f | 1316 | return ret; |
63c85238 PW |
1317 | } |
1318 | ||
1319 | /** | |
1320 | * _wait_target_ready - wait for a module to leave slave idle | |
1321 | * @oh: struct omap_hwmod * | |
1322 | * | |
1323 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
1324 | * does not have an IDLEST bit or if the module successfully leaves | |
1325 | * slave idle; otherwise, pass along the return value of the | |
d0f0631d | 1326 | * appropriate *_cm*_wait_module_ready() function. |
63c85238 PW |
1327 | */ |
1328 | static int _wait_target_ready(struct omap_hwmod *oh) | |
1329 | { | |
1330 | struct omap_hwmod_ocp_if *os; | |
1331 | int ret; | |
1332 | ||
1333 | if (!oh) | |
1334 | return -EINVAL; | |
1335 | ||
2d6141ba | 1336 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
1337 | return 0; |
1338 | ||
2d6141ba PW |
1339 | os = _find_mpu_rt_port(oh); |
1340 | if (!os) | |
63c85238 PW |
1341 | return 0; |
1342 | ||
1343 | /* XXX check module SIDLEMODE */ | |
1344 | ||
1345 | /* XXX check clock enable states */ | |
1346 | ||
1347 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1348 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
1349 | oh->prcm.omap2.idlest_reg_id, | |
1350 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 1351 | } else if (cpu_is_omap44xx()) { |
d0f0631d BC |
1352 | if (!oh->clkdm) |
1353 | return -EINVAL; | |
1354 | ||
1355 | ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
1356 | oh->clkdm->cm_inst, | |
1357 | oh->clkdm->clkdm_offs, | |
1358 | oh->prcm.omap4.clkctrl_offs); | |
63c85238 PW |
1359 | } else { |
1360 | BUG(); | |
1361 | }; | |
1362 | ||
1363 | return ret; | |
1364 | } | |
1365 | ||
5365efbe | 1366 | /** |
cc1226e7 | 1367 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1368 | * @oh: struct omap_hwmod * |
1369 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1370 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1371 | * |
1372 | * Return the bit position of the reset line that match the | |
1373 | * input name. Return -ENOENT if not found. | |
1374 | */ | |
cc1226e7 | 1375 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1376 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1377 | { |
1378 | int i; | |
1379 | ||
1380 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1381 | const char *rst_line = oh->rst_lines[i].name; | |
1382 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1383 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1384 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1385 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1386 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1387 | ohri->st_shift); | |
5365efbe | 1388 | |
cc1226e7 | 1389 | return 0; |
5365efbe BC |
1390 | } |
1391 | } | |
1392 | ||
1393 | return -ENOENT; | |
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * _assert_hardreset - assert the HW reset line of submodules | |
1398 | * contained in the hwmod module. | |
1399 | * @oh: struct omap_hwmod * | |
1400 | * @name: name of the reset line to lookup and assert | |
1401 | * | |
1402 | * Some IP like dsp, ipu or iva contain processor that require | |
1403 | * an HW reset line to be assert / deassert in order to enable fully | |
1404 | * the IP. | |
1405 | */ | |
1406 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1407 | { | |
cc1226e7 | 1408 | struct omap_hwmod_rst_info ohri; |
1409 | u8 ret; | |
5365efbe BC |
1410 | |
1411 | if (!oh) | |
1412 | return -EINVAL; | |
1413 | ||
cc1226e7 | 1414 | ret = _lookup_hardreset(oh, name, &ohri); |
1415 | if (IS_ERR_VALUE(ret)) | |
1416 | return ret; | |
5365efbe BC |
1417 | |
1418 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1419 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1420 | ohri.rst_shift); |
5365efbe | 1421 | else if (cpu_is_omap44xx()) |
eaac329d BC |
1422 | return omap4_prminst_assert_hardreset(ohri.rst_shift, |
1423 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1424 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1425 | oh->prcm.omap4.rstctrl_offs); | |
5365efbe BC |
1426 | else |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ||
1430 | /** | |
1431 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1432 | * in the hwmod module. | |
1433 | * @oh: struct omap_hwmod * | |
1434 | * @name: name of the reset line to look up and deassert | |
1435 | * | |
1436 | * Some IP like dsp, ipu or iva contain processor that require | |
1437 | * an HW reset line to be assert / deassert in order to enable fully | |
1438 | * the IP. | |
1439 | */ | |
1440 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1441 | { | |
cc1226e7 | 1442 | struct omap_hwmod_rst_info ohri; |
1443 | int ret; | |
5365efbe BC |
1444 | |
1445 | if (!oh) | |
1446 | return -EINVAL; | |
1447 | ||
cc1226e7 | 1448 | ret = _lookup_hardreset(oh, name, &ohri); |
1449 | if (IS_ERR_VALUE(ret)) | |
1450 | return ret; | |
5365efbe | 1451 | |
cc1226e7 | 1452 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1453 | ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
1454 | ohri.rst_shift, | |
1455 | ohri.st_shift); | |
1456 | } else if (cpu_is_omap44xx()) { | |
1457 | if (ohri.st_shift) | |
1458 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
1459 | oh->name, name); | |
eaac329d BC |
1460 | ret = omap4_prminst_deassert_hardreset(ohri.rst_shift, |
1461 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1462 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1463 | oh->prcm.omap4.rstctrl_offs); | |
cc1226e7 | 1464 | } else { |
5365efbe | 1465 | return -EINVAL; |
cc1226e7 | 1466 | } |
5365efbe | 1467 | |
cc1226e7 | 1468 | if (ret == -EBUSY) |
5365efbe BC |
1469 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1470 | ||
cc1226e7 | 1471 | return ret; |
5365efbe BC |
1472 | } |
1473 | ||
1474 | /** | |
1475 | * _read_hardreset - read the HW reset line state of submodules | |
1476 | * contained in the hwmod module | |
1477 | * @oh: struct omap_hwmod * | |
1478 | * @name: name of the reset line to look up and read | |
1479 | * | |
1480 | * Return the state of the reset line. | |
1481 | */ | |
1482 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1483 | { | |
cc1226e7 | 1484 | struct omap_hwmod_rst_info ohri; |
1485 | u8 ret; | |
5365efbe BC |
1486 | |
1487 | if (!oh) | |
1488 | return -EINVAL; | |
1489 | ||
cc1226e7 | 1490 | ret = _lookup_hardreset(oh, name, &ohri); |
1491 | if (IS_ERR_VALUE(ret)) | |
1492 | return ret; | |
5365efbe BC |
1493 | |
1494 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1495 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1496 | ohri.st_shift); |
5365efbe | 1497 | } else if (cpu_is_omap44xx()) { |
eaac329d BC |
1498 | return omap4_prminst_is_hardreset_asserted(ohri.rst_shift, |
1499 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1500 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1501 | oh->prcm.omap4.rstctrl_offs); | |
5365efbe BC |
1502 | } else { |
1503 | return -EINVAL; | |
1504 | } | |
1505 | } | |
1506 | ||
747834ab PW |
1507 | /** |
1508 | * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset | |
1509 | * @oh: struct omap_hwmod * | |
1510 | * | |
1511 | * If any hardreset line associated with @oh is asserted, then return true. | |
1512 | * Otherwise, if @oh has no hardreset lines associated with it, or if | |
1513 | * no hardreset lines associated with @oh are asserted, then return false. | |
1514 | * This function is used to avoid executing some parts of the IP block | |
1515 | * enable/disable sequence if a hardreset line is set. | |
1516 | */ | |
1517 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1518 | { | |
1519 | int i; | |
1520 | ||
1521 | if (oh->rst_lines_cnt == 0) | |
1522 | return false; | |
1523 | ||
1524 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1525 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1526 | return true; | |
1527 | ||
1528 | return false; | |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1533 | * @oh: struct omap_hwmod * | |
1534 | * | |
1535 | * Disable the PRCM module mode related to the hwmod @oh. | |
1536 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1537 | */ | |
1538 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1539 | { | |
1540 | int v; | |
1541 | ||
1542 | /* The module mode does not exist prior OMAP4 */ | |
1543 | if (!cpu_is_omap44xx()) | |
1544 | return -EINVAL; | |
1545 | ||
1546 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1547 | return -EINVAL; | |
1548 | ||
1549 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1550 | ||
1551 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1552 | oh->clkdm->cm_inst, | |
1553 | oh->clkdm->clkdm_offs, | |
1554 | oh->prcm.omap4.clkctrl_offs); | |
1555 | ||
1556 | if (_are_any_hardreset_lines_asserted(oh)) | |
1557 | return 0; | |
1558 | ||
1559 | v = _omap4_wait_target_disable(oh); | |
1560 | if (v) | |
1561 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1562 | oh->name); | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
63c85238 | 1567 | /** |
bd36179e | 1568 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1569 | * @oh: struct omap_hwmod * |
1570 | * | |
1571 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1572 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1573 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1574 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1575 | * |
1576 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1577 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1578 | * use the SYSCONFIG softreset bit to provide the status. |
1579 | * | |
bd36179e PW |
1580 | * Note that some IP like McBSP do have reset control but don't have |
1581 | * reset status. | |
63c85238 | 1582 | */ |
bd36179e | 1583 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1584 | { |
387ca5bf | 1585 | u32 v, softrst_mask; |
6f8b7ff5 | 1586 | int c = 0; |
96835af9 | 1587 | int ret = 0; |
63c85238 | 1588 | |
43b40992 | 1589 | if (!oh->class->sysc || |
2cb06814 | 1590 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1591 | return -ENOENT; |
63c85238 PW |
1592 | |
1593 | /* clocks must be on for this operation */ | |
1594 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1595 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1596 | "enabled state\n", oh->name); | |
63c85238 PW |
1597 | return -EINVAL; |
1598 | } | |
1599 | ||
96835af9 BC |
1600 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1601 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1602 | _enable_optional_clocks(oh); | |
1603 | ||
bd36179e | 1604 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1605 | |
1606 | v = oh->_sysc_cache; | |
96835af9 BC |
1607 | ret = _set_softreset(oh, &v); |
1608 | if (ret) | |
1609 | goto dis_opt_clks; | |
63c85238 PW |
1610 | _write_sysconfig(v, oh); |
1611 | ||
d99de7f5 FGL |
1612 | if (oh->class->sysc->srst_udelay) |
1613 | udelay(oh->class->sysc->srst_udelay); | |
1614 | ||
2cb06814 | 1615 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1616 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1617 | oh->class->sysc->syss_offs) |
1618 | & SYSS_RESETDONE_MASK), | |
1619 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1620 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1621 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1622 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1623 | oh->class->sysc->sysc_offs) |
387ca5bf | 1624 | & softrst_mask), |
2cb06814 | 1625 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1626 | } |
63c85238 | 1627 | |
5365efbe | 1628 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1629 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1630 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1631 | else |
5365efbe | 1632 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1633 | |
1634 | /* | |
1635 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1636 | * _wait_target_ready() or _reset() | |
1637 | */ | |
1638 | ||
96835af9 BC |
1639 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1640 | ||
1641 | dis_opt_clks: | |
1642 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1643 | _disable_optional_clocks(oh); | |
1644 | ||
1645 | return ret; | |
63c85238 PW |
1646 | } |
1647 | ||
bd36179e PW |
1648 | /** |
1649 | * _reset - reset an omap_hwmod | |
1650 | * @oh: struct omap_hwmod * | |
1651 | * | |
30e105c0 PW |
1652 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1653 | * function pointer defined, then call it to reset the IP block, and | |
1654 | * pass along its return value to the caller. Otherwise, if the IP | |
1655 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1656 | * associated with it, call a function to reset the IP block via that | |
1657 | * method, and pass along the return value to the caller. Finally, if | |
1658 | * the IP block has some hardreset lines associated with it, assert | |
1659 | * all of those, but do _not_ deassert them. (This is because driver | |
1660 | * authors have expressed an apparent requirement to control the | |
1661 | * deassertion of the hardreset lines themselves.) | |
1662 | * | |
1663 | * The default software reset mechanism for most OMAP IP blocks is | |
1664 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1665 | * hwmods cannot be reset via this method. Some are not targets and | |
1666 | * therefore have no OCP header registers to access. Others (like the | |
1667 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1668 | * rare cases, custom reset code can be supplied in the struct | |
1669 | * omap_hwmod_class .reset function pointer. Passes along the return | |
1670 | * value from either _ocp_softreset() or the custom reset function - | |
1671 | * these must return -EINVAL if the hwmod cannot be reset this way or | |
1672 | * if the hwmod is in the wrong state, -ETIMEDOUT if the module did | |
1673 | * not reset in time, or 0 upon success. | |
bd36179e PW |
1674 | */ |
1675 | static int _reset(struct omap_hwmod *oh) | |
1676 | { | |
30e105c0 | 1677 | int i, r; |
bd36179e PW |
1678 | |
1679 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1680 | ||
30e105c0 PW |
1681 | if (oh->class->reset) { |
1682 | r = oh->class->reset(oh); | |
1683 | } else { | |
1684 | if (oh->rst_lines_cnt > 0) { | |
1685 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1686 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1687 | return 0; | |
1688 | } else { | |
1689 | r = _ocp_softreset(oh); | |
1690 | if (r == -ENOENT) | |
1691 | r = 0; | |
1692 | } | |
1693 | } | |
1694 | ||
9c8b0ec7 | 1695 | /* |
30e105c0 PW |
1696 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1697 | * softreset. The _enable() function should be split to avoid | |
1698 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1699 | */ |
2800852a RN |
1700 | if (oh->class->sysc) { |
1701 | _update_sysc_cache(oh); | |
1702 | _enable_sysc(oh); | |
1703 | } | |
1704 | ||
30e105c0 | 1705 | return r; |
bd36179e PW |
1706 | } |
1707 | ||
63c85238 | 1708 | /** |
dc6d1cda | 1709 | * _enable - enable an omap_hwmod |
63c85238 PW |
1710 | * @oh: struct omap_hwmod * |
1711 | * | |
1712 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1713 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1714 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1715 | */ |
dc6d1cda | 1716 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1717 | { |
747834ab | 1718 | int r; |
665d0013 | 1719 | int hwsup = 0; |
63c85238 | 1720 | |
34617e2a BC |
1721 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1722 | ||
aacf0941 | 1723 | /* |
64813c3f PW |
1724 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
1725 | * state at init. Now that someone is really trying to enable | |
1726 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
1727 | */ |
1728 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
1729 | /* | |
1730 | * If the caller has mux data populated, do the mux'ing | |
1731 | * which wouldn't have been done as part of the _enable() | |
1732 | * done during setup. | |
1733 | */ | |
1734 | if (oh->mux) | |
1735 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1736 | ||
1737 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
1738 | return 0; | |
1739 | } | |
1740 | ||
63c85238 PW |
1741 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1742 | oh->_state != _HWMOD_STATE_IDLE && | |
1743 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1744 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1745 | oh->name); | |
63c85238 PW |
1746 | return -EINVAL; |
1747 | } | |
1748 | ||
31f62866 | 1749 | /* |
747834ab PW |
1750 | * If an IP block contains HW reset lines and any of them are |
1751 | * asserted, we let integration code associated with that | |
1752 | * block handle the enable. We've received very little | |
1753 | * information on what those driver authors need, and until | |
1754 | * detailed information is provided and the driver code is | |
1755 | * posted to the public lists, this is probably the best we | |
1756 | * can do. | |
31f62866 | 1757 | */ |
747834ab PW |
1758 | if (_are_any_hardreset_lines_asserted(oh)) |
1759 | return 0; | |
63c85238 | 1760 | |
665d0013 RN |
1761 | /* Mux pins for device runtime if populated */ |
1762 | if (oh->mux && (!oh->mux->enabled || | |
1763 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
1764 | oh->mux->pads_dynamic))) | |
1765 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1766 | ||
1767 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 1768 | |
665d0013 RN |
1769 | if (oh->clkdm) { |
1770 | /* | |
1771 | * A clockdomain must be in SW_SUP before enabling | |
1772 | * completely the module. The clockdomain can be set | |
1773 | * in HW_AUTO only when the module become ready. | |
1774 | */ | |
1775 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1776 | r = clkdm_hwmod_enable(oh->clkdm, oh); | |
1777 | if (r) { | |
1778 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1779 | oh->name, oh->clkdm->name, r); | |
1780 | return r; | |
1781 | } | |
34617e2a | 1782 | } |
665d0013 RN |
1783 | |
1784 | _enable_clocks(oh); | |
45c38252 | 1785 | _enable_module(oh); |
34617e2a | 1786 | |
665d0013 RN |
1787 | r = _wait_target_ready(oh); |
1788 | if (!r) { | |
1789 | /* | |
1790 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
1791 | * assuming that the previous state was HW_AUTO | |
1792 | */ | |
1793 | if (oh->clkdm && hwsup) | |
1794 | clkdm_allow_idle(oh->clkdm); | |
1795 | ||
1796 | oh->_state = _HWMOD_STATE_ENABLED; | |
1797 | ||
1798 | /* Access the sysconfig only if the target is ready */ | |
1799 | if (oh->class->sysc) { | |
1800 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1801 | _update_sysc_cache(oh); | |
1802 | _enable_sysc(oh); | |
1803 | } | |
1804 | } else { | |
1805 | _disable_clocks(oh); | |
1806 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1807 | oh->name, r); | |
34617e2a | 1808 | |
665d0013 RN |
1809 | if (oh->clkdm) |
1810 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1811 | } |
1812 | ||
63c85238 PW |
1813 | return r; |
1814 | } | |
1815 | ||
1816 | /** | |
dc6d1cda | 1817 | * _idle - idle an omap_hwmod |
63c85238 PW |
1818 | * @oh: struct omap_hwmod * |
1819 | * | |
1820 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1821 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1822 | * state or returns 0. | |
63c85238 | 1823 | */ |
dc6d1cda | 1824 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1825 | { |
34617e2a BC |
1826 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1827 | ||
63c85238 | 1828 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
1829 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
1830 | oh->name); | |
63c85238 PW |
1831 | return -EINVAL; |
1832 | } | |
1833 | ||
747834ab PW |
1834 | if (_are_any_hardreset_lines_asserted(oh)) |
1835 | return 0; | |
1836 | ||
43b40992 | 1837 | if (oh->class->sysc) |
74ff3a68 | 1838 | _idle_sysc(oh); |
63c85238 | 1839 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 BC |
1840 | |
1841 | _omap4_disable_module(oh); | |
1842 | ||
45c38252 BC |
1843 | /* |
1844 | * The module must be in idle mode before disabling any parents | |
1845 | * clocks. Otherwise, the parent clock might be disabled before | |
1846 | * the module transition is done, and thus will prevent the | |
1847 | * transition to complete properly. | |
1848 | */ | |
1849 | _disable_clocks(oh); | |
665d0013 RN |
1850 | if (oh->clkdm) |
1851 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 1852 | |
8d9af88f | 1853 | /* Mux pins for device idle if populated */ |
029268e4 | 1854 | if (oh->mux && oh->mux->pads_dynamic) |
8d9af88f TL |
1855 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
1856 | ||
63c85238 PW |
1857 | oh->_state = _HWMOD_STATE_IDLE; |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
9599217a KVA |
1862 | /** |
1863 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
1864 | * @oh: struct omap_hwmod * | |
1865 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
1866 | * | |
1867 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
1868 | * local copy. Intended to be used by drivers that require | |
1869 | * direct manipulation of the AUTOIDLE bits. | |
1870 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
1871 | * along the return value from _set_module_autoidle(). | |
1872 | * | |
1873 | * Any users of this function should be scrutinized carefully. | |
1874 | */ | |
1875 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
1876 | { | |
1877 | u32 v; | |
1878 | int retval = 0; | |
1879 | unsigned long flags; | |
1880 | ||
1881 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
1882 | return -EINVAL; | |
1883 | ||
1884 | spin_lock_irqsave(&oh->_lock, flags); | |
1885 | ||
1886 | v = oh->_sysc_cache; | |
1887 | ||
1888 | retval = _set_module_autoidle(oh, autoidle, &v); | |
1889 | ||
1890 | if (!retval) | |
1891 | _write_sysconfig(v, oh); | |
1892 | ||
1893 | spin_unlock_irqrestore(&oh->_lock, flags); | |
1894 | ||
1895 | return retval; | |
1896 | } | |
1897 | ||
63c85238 PW |
1898 | /** |
1899 | * _shutdown - shutdown an omap_hwmod | |
1900 | * @oh: struct omap_hwmod * | |
1901 | * | |
1902 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1903 | * used for the hwmod is removed or unloaded or if the driver is not | |
1904 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1905 | * state or returns 0. | |
1906 | */ | |
1907 | static int _shutdown(struct omap_hwmod *oh) | |
1908 | { | |
9c8b0ec7 | 1909 | int ret, i; |
e4dc8f50 PW |
1910 | u8 prev_state; |
1911 | ||
63c85238 PW |
1912 | if (oh->_state != _HWMOD_STATE_IDLE && |
1913 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
1914 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
1915 | oh->name); | |
63c85238 PW |
1916 | return -EINVAL; |
1917 | } | |
1918 | ||
747834ab PW |
1919 | if (_are_any_hardreset_lines_asserted(oh)) |
1920 | return 0; | |
1921 | ||
63c85238 PW |
1922 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
1923 | ||
e4dc8f50 PW |
1924 | if (oh->class->pre_shutdown) { |
1925 | prev_state = oh->_state; | |
1926 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1927 | _enable(oh); |
e4dc8f50 PW |
1928 | ret = oh->class->pre_shutdown(oh); |
1929 | if (ret) { | |
1930 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1931 | _idle(oh); |
e4dc8f50 PW |
1932 | return ret; |
1933 | } | |
1934 | } | |
1935 | ||
6481c73c MV |
1936 | if (oh->class->sysc) { |
1937 | if (oh->_state == _HWMOD_STATE_IDLE) | |
1938 | _enable(oh); | |
74ff3a68 | 1939 | _shutdown_sysc(oh); |
6481c73c | 1940 | } |
5365efbe | 1941 | |
3827f949 BC |
1942 | /* clocks and deps are already disabled in idle */ |
1943 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1944 | _del_initiator_dep(oh, mpu_oh); | |
1945 | /* XXX what about the other system initiators here? dma, dsp */ | |
bfc141e3 | 1946 | _omap4_disable_module(oh); |
45c38252 | 1947 | _disable_clocks(oh); |
665d0013 RN |
1948 | if (oh->clkdm) |
1949 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 1950 | } |
63c85238 PW |
1951 | /* XXX Should this code also force-disable the optional clocks? */ |
1952 | ||
9c8b0ec7 PW |
1953 | for (i = 0; i < oh->rst_lines_cnt; i++) |
1954 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 1955 | |
8d9af88f TL |
1956 | /* Mux pins to safe mode or use populated off mode values */ |
1957 | if (oh->mux) | |
1958 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
1959 | |
1960 | oh->_state = _HWMOD_STATE_DISABLED; | |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
381d033a PW |
1965 | /** |
1966 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
1967 | * @oh: struct omap_hwmod * to locate the virtual address | |
1968 | * | |
1969 | * Cache the virtual address used by the MPU to access this IP block's | |
1970 | * registers. This address is needed early so the OCP registers that | |
1971 | * are part of the device's address space can be ioremapped properly. | |
1972 | * No return value. | |
1973 | */ | |
1974 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
1975 | { | |
c9aafd23 PW |
1976 | struct omap_hwmod_addr_space *mem; |
1977 | void __iomem *va_start; | |
1978 | ||
1979 | if (!oh) | |
1980 | return; | |
1981 | ||
381d033a PW |
1982 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
1983 | return; | |
1984 | ||
c9aafd23 PW |
1985 | mem = _find_mpu_rt_addr_space(oh); |
1986 | if (!mem) { | |
1987 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
1988 | oh->name); | |
1989 | return; | |
1990 | } | |
1991 | ||
1992 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
1993 | if (!va_start) { | |
1994 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
1995 | return; | |
1996 | } | |
1997 | ||
1998 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
1999 | oh->name, va_start); | |
2000 | ||
2001 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2002 | } |
2003 | ||
2004 | /** | |
2005 | * _init - initialize internal data for the hwmod @oh | |
2006 | * @oh: struct omap_hwmod * | |
2007 | * @n: (unused) | |
2008 | * | |
2009 | * Look up the clocks and the address space used by the MPU to access | |
2010 | * registers belonging to the hwmod @oh. @oh must already be | |
2011 | * registered at this point. This is the first of two phases for | |
2012 | * hwmod initialization. Code called here does not touch any hardware | |
2013 | * registers, it simply prepares internal data structures. Returns 0 | |
2014 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2015 | * failure. | |
2016 | */ | |
2017 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2018 | { | |
2019 | int r; | |
2020 | ||
2021 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2022 | return 0; | |
2023 | ||
2024 | _init_mpu_rt_base(oh, NULL); | |
2025 | ||
2026 | r = _init_clocks(oh, NULL); | |
2027 | if (IS_ERR_VALUE(r)) { | |
2028 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2029 | return -EINVAL; | |
2030 | } | |
2031 | ||
2032 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2033 | ||
2034 | return 0; | |
2035 | } | |
2036 | ||
63c85238 | 2037 | /** |
64813c3f | 2038 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2039 | * @oh: struct omap_hwmod * |
2040 | * | |
64813c3f PW |
2041 | * Set up the module's interface clocks. XXX This function is still mostly |
2042 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2043 | * the clock code. No return value. | |
63c85238 | 2044 | */ |
64813c3f | 2045 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2046 | { |
5d95dde7 PW |
2047 | struct omap_hwmod_ocp_if *os; |
2048 | int i = 0; | |
381d033a | 2049 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2050 | return; |
48d54f3f | 2051 | |
63c85238 | 2052 | |
5d95dde7 PW |
2053 | while (i < oh->slaves_cnt) { |
2054 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
2055 | if (!os->_clk) | |
64813c3f | 2056 | continue; |
63c85238 | 2057 | |
64813c3f PW |
2058 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2059 | /* XXX omap_iclk_deny_idle(c); */ | |
2060 | } else { | |
2061 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2062 | clk_enable(os->_clk); |
63c85238 PW |
2063 | } |
2064 | } | |
2065 | ||
64813c3f PW |
2066 | return; |
2067 | } | |
2068 | ||
2069 | /** | |
2070 | * _setup_reset - reset an IP block during the setup process | |
2071 | * @oh: struct omap_hwmod * | |
2072 | * | |
2073 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2074 | * process. The IP block is first enabled so it can be successfully | |
2075 | * reset. Returns 0 upon success or a negative error code upon | |
2076 | * failure. | |
2077 | */ | |
2078 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2079 | { | |
2080 | int r; | |
2081 | ||
2082 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2083 | return -EINVAL; | |
63c85238 | 2084 | |
747834ab PW |
2085 | if (oh->rst_lines_cnt == 0) { |
2086 | r = _enable(oh); | |
2087 | if (r) { | |
2088 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2089 | oh->name, oh->_state); | |
2090 | return -EINVAL; | |
2091 | } | |
9a23dfe1 | 2092 | } |
63c85238 | 2093 | |
2800852a | 2094 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2095 | r = _reset(oh); |
2096 | ||
2097 | return r; | |
2098 | } | |
2099 | ||
2100 | /** | |
2101 | * _setup_postsetup - transition to the appropriate state after _setup | |
2102 | * @oh: struct omap_hwmod * | |
2103 | * | |
2104 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2105 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2106 | * this function is called at the end of _setup().) The postsetup | |
2107 | * state for an IP block can be changed by calling | |
2108 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2109 | * before one of the omap_hwmod_setup*() functions are called for the | |
2110 | * IP block. | |
2111 | * | |
2112 | * The IP block stays in this state until a PM runtime-based driver is | |
2113 | * loaded for that IP block. A post-setup state of IDLE is | |
2114 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2115 | * drivers, since those drivers are able to enable the IP block. A | |
2116 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2117 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2118 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2119 | * included, since the WDTIMER starts running on reset and will reset | |
2120 | * the MPU if left active. | |
2121 | * | |
2122 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2123 | * drivers have been converted to use PM runtime, and all of the IP | |
2124 | * block data and interconnect data is available to the hwmod code, it | |
2125 | * should be possible to replace this mechanism with a "lazy reset" | |
2126 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2127 | * when the driver first probes, then all remaining IP blocks without | |
2128 | * drivers are either shut down or enabled after the drivers have | |
2129 | * loaded. However, this cannot take place until the above | |
2130 | * preconditions have been met, since otherwise the late reset code | |
2131 | * has no way of knowing which IP blocks are in use by drivers, and | |
2132 | * which ones are unused. | |
2133 | * | |
2134 | * No return value. | |
2135 | */ | |
2136 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2137 | { | |
2138 | u8 postsetup_state; | |
2139 | ||
2140 | if (oh->rst_lines_cnt > 0) | |
2141 | return; | |
76e5589e | 2142 | |
2092e5cc PW |
2143 | postsetup_state = oh->_postsetup_state; |
2144 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2145 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2146 | ||
2147 | /* | |
2148 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2149 | * it should be set by the core code as a runtime flag during startup | |
2150 | */ | |
2151 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2152 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2153 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2154 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2155 | } |
2092e5cc PW |
2156 | |
2157 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2158 | _idle(oh); |
2092e5cc PW |
2159 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2160 | _shutdown(oh); | |
2161 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2162 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2163 | oh->name, postsetup_state); | |
63c85238 | 2164 | |
64813c3f PW |
2165 | return; |
2166 | } | |
2167 | ||
2168 | /** | |
2169 | * _setup - prepare IP block hardware for use | |
2170 | * @oh: struct omap_hwmod * | |
2171 | * @n: (unused, pass NULL) | |
2172 | * | |
2173 | * Configure the IP block represented by @oh. This may include | |
2174 | * enabling the IP block, resetting it, and placing it into a | |
2175 | * post-setup state, depending on the type of IP block and applicable | |
2176 | * flags. IP blocks are reset to prevent any previous configuration | |
2177 | * by the bootloader or previous operating system from interfering | |
2178 | * with power management or other parts of the system. The reset can | |
2179 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2180 | * two phases for hwmod initialization. Code called here generally | |
2181 | * affects the IP block hardware, or system integration hardware | |
2182 | * associated with the IP block. Returns 0. | |
2183 | */ | |
2184 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2185 | { | |
2186 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2187 | return 0; | |
2188 | ||
2189 | _setup_iclk_autoidle(oh); | |
2190 | ||
2191 | if (!_setup_reset(oh)) | |
2192 | _setup_postsetup(oh); | |
2193 | ||
63c85238 PW |
2194 | return 0; |
2195 | } | |
2196 | ||
63c85238 | 2197 | /** |
0102b627 | 2198 | * _register - register a struct omap_hwmod |
63c85238 PW |
2199 | * @oh: struct omap_hwmod * |
2200 | * | |
43b40992 PW |
2201 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2202 | * already has been registered by the same name; -EINVAL if the | |
2203 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2204 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2205 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2206 | * success. | |
63c85238 PW |
2207 | * |
2208 | * XXX The data should be copied into bootmem, so the original data | |
2209 | * should be marked __initdata and freed after init. This would allow | |
2210 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2211 | * that the copy process would be relatively complex due to the large number | |
2212 | * of substructures. | |
2213 | */ | |
01592df9 | 2214 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2215 | { |
569edd70 | 2216 | int ms_id; |
63c85238 | 2217 | |
43b40992 PW |
2218 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2219 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2220 | return -EINVAL; |
2221 | ||
63c85238 PW |
2222 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2223 | ||
ce35b244 BC |
2224 | if (_lookup(oh->name)) |
2225 | return -EEXIST; | |
63c85238 PW |
2226 | |
2227 | ms_id = _find_mpu_port_index(oh); | |
e7c7d760 | 2228 | if (!IS_ERR_VALUE(ms_id)) |
63c85238 | 2229 | oh->_mpu_port_index = ms_id; |
e7c7d760 | 2230 | else |
63c85238 | 2231 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; |
63c85238 PW |
2232 | |
2233 | list_add_tail(&oh->node, &omap_hwmod_list); | |
2234 | ||
dc6d1cda | 2235 | spin_lock_init(&oh->_lock); |
2092e5cc | 2236 | |
63c85238 PW |
2237 | oh->_state = _HWMOD_STATE_REGISTERED; |
2238 | ||
569edd70 PW |
2239 | /* |
2240 | * XXX Rather than doing a strcmp(), this should test a flag | |
2241 | * set in the hwmod data, inserted by the autogenerator code. | |
2242 | */ | |
2243 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2244 | mpu_oh = oh; | |
63c85238 | 2245 | |
569edd70 | 2246 | return 0; |
63c85238 PW |
2247 | } |
2248 | ||
0102b627 BC |
2249 | |
2250 | /* Public functions */ | |
2251 | ||
2252 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2253 | { | |
2254 | if (oh->flags & HWMOD_16BIT_REG) | |
2255 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
2256 | else | |
2257 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
2258 | } | |
2259 | ||
2260 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2261 | { | |
2262 | if (oh->flags & HWMOD_16BIT_REG) | |
2263 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
2264 | else | |
2265 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
2266 | } | |
2267 | ||
6d3c55fd A |
2268 | /** |
2269 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2270 | * @oh: struct omap_hwmod * | |
2271 | * | |
2272 | * This is a public function exposed to drivers. Some drivers may need to do | |
2273 | * some settings before and after resetting the device. Those drivers after | |
2274 | * doing the necessary settings could use this function to start a reset by | |
2275 | * setting the SYSCONFIG.SOFTRESET bit. | |
2276 | */ | |
2277 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
2278 | { | |
3c55c1ba PW |
2279 | u32 v; |
2280 | int ret; | |
2281 | ||
2282 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
2283 | return -EINVAL; |
2284 | ||
3c55c1ba PW |
2285 | v = oh->_sysc_cache; |
2286 | ret = _set_softreset(oh, &v); | |
2287 | if (ret) | |
2288 | goto error; | |
2289 | _write_sysconfig(v, oh); | |
2290 | ||
2291 | error: | |
2292 | return ret; | |
6d3c55fd A |
2293 | } |
2294 | ||
0102b627 BC |
2295 | /** |
2296 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
2297 | * @oh: struct omap_hwmod * | |
2298 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
2299 | * | |
2300 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
2301 | * local copy. Intended to be used by drivers that have some erratum | |
2302 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
2303 | * -EINVAL if @oh is null, or passes along the return value from | |
2304 | * _set_slave_idlemode(). | |
2305 | * | |
2306 | * XXX Does this function have any current users? If not, we should | |
2307 | * remove it; it is better to let the rest of the hwmod code handle this. | |
2308 | * Any users of this function should be scrutinized carefully. | |
2309 | */ | |
2310 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
2311 | { | |
2312 | u32 v; | |
2313 | int retval = 0; | |
2314 | ||
2315 | if (!oh) | |
2316 | return -EINVAL; | |
2317 | ||
2318 | v = oh->_sysc_cache; | |
2319 | ||
2320 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
2321 | if (!retval) | |
2322 | _write_sysconfig(v, oh); | |
2323 | ||
2324 | return retval; | |
2325 | } | |
2326 | ||
63c85238 PW |
2327 | /** |
2328 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
2329 | * @name: name of the omap_hwmod to look up | |
2330 | * | |
2331 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
2332 | * struct omap_hwmod *, or NULL upon error. | |
2333 | */ | |
2334 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
2335 | { | |
2336 | struct omap_hwmod *oh; | |
2337 | ||
2338 | if (!name) | |
2339 | return NULL; | |
2340 | ||
63c85238 | 2341 | oh = _lookup(name); |
63c85238 PW |
2342 | |
2343 | return oh; | |
2344 | } | |
2345 | ||
2346 | /** | |
2347 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
2348 | * @fn: pointer to a callback function | |
97d60162 | 2349 | * @data: void * data to pass to callback function |
63c85238 PW |
2350 | * |
2351 | * Call @fn for each registered omap_hwmod, passing @data to each | |
2352 | * function. @fn must return 0 for success or any other value for | |
2353 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
2354 | * will stop and the non-zero return value will be passed to the | |
2355 | * caller of omap_hwmod_for_each(). @fn is called with | |
2356 | * omap_hwmod_for_each() held. | |
2357 | */ | |
97d60162 PW |
2358 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
2359 | void *data) | |
63c85238 PW |
2360 | { |
2361 | struct omap_hwmod *temp_oh; | |
30ebad9d | 2362 | int ret = 0; |
63c85238 PW |
2363 | |
2364 | if (!fn) | |
2365 | return -EINVAL; | |
2366 | ||
63c85238 | 2367 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 2368 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
2369 | if (ret) |
2370 | break; | |
2371 | } | |
63c85238 PW |
2372 | |
2373 | return ret; | |
2374 | } | |
2375 | ||
63c85238 | 2376 | /** |
550c8092 | 2377 | * omap_hwmod_register - register an array of hwmods |
63c85238 PW |
2378 | * @ohs: pointer to an array of omap_hwmods to register |
2379 | * | |
2380 | * Intended to be called early in boot before the clock framework is | |
2381 | * initialized. If @ohs is not null, will register all omap_hwmods | |
550c8092 | 2382 | * listed in @ohs that are valid for this chip. Returns 0. |
63c85238 | 2383 | */ |
550c8092 | 2384 | int __init omap_hwmod_register(struct omap_hwmod **ohs) |
63c85238 | 2385 | { |
bac1a0f0 | 2386 | int r, i; |
63c85238 PW |
2387 | |
2388 | if (!ohs) | |
2389 | return 0; | |
2390 | ||
bac1a0f0 PW |
2391 | i = 0; |
2392 | do { | |
bac1a0f0 PW |
2393 | r = _register(ohs[i]); |
2394 | WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, | |
2395 | r); | |
2396 | } while (ohs[++i]); | |
63c85238 PW |
2397 | |
2398 | return 0; | |
2399 | } | |
2400 | ||
381d033a PW |
2401 | /** |
2402 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
2403 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
2404 | * | |
2405 | * If the hwmod data corresponding to the MPU subsystem IP block | |
2406 | * hasn't been initialized and set up yet, do so now. This must be | |
2407 | * done first since sleep dependencies may be added from other hwmods | |
2408 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
2409 | * return value. | |
63c85238 | 2410 | */ |
381d033a | 2411 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 2412 | { |
381d033a PW |
2413 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
2414 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
2415 | __func__, MPU_INITIATOR_NAME); | |
2416 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
2417 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
2418 | } |
2419 | ||
63c85238 | 2420 | /** |
a2debdbd PW |
2421 | * omap_hwmod_setup_one - set up a single hwmod |
2422 | * @oh_name: const char * name of the already-registered hwmod to set up | |
2423 | * | |
381d033a PW |
2424 | * Initialize and set up a single hwmod. Intended to be used for a |
2425 | * small number of early devices, such as the timer IP blocks used for | |
2426 | * the scheduler clock. Must be called after omap2_clk_init(). | |
2427 | * Resolves the struct clk names to struct clk pointers for each | |
2428 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
2429 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
2430 | */ |
2431 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
2432 | { |
2433 | struct omap_hwmod *oh; | |
63c85238 | 2434 | |
a2debdbd PW |
2435 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
2436 | ||
a2debdbd PW |
2437 | oh = _lookup(oh_name); |
2438 | if (!oh) { | |
2439 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
2440 | return -EINVAL; | |
2441 | } | |
63c85238 | 2442 | |
381d033a | 2443 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 2444 | |
381d033a | 2445 | _init(oh, NULL); |
a2debdbd PW |
2446 | _setup(oh, NULL); |
2447 | ||
63c85238 PW |
2448 | return 0; |
2449 | } | |
2450 | ||
2451 | /** | |
381d033a | 2452 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 2453 | * |
381d033a PW |
2454 | * Initialize and set up all IP blocks registered with the hwmod code. |
2455 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
2456 | * names to struct clk pointers for each registered omap_hwmod. Also | |
2457 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 2458 | */ |
550c8092 | 2459 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 2460 | { |
381d033a | 2461 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 2462 | |
381d033a | 2463 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 2464 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
2465 | |
2466 | return 0; | |
2467 | } | |
550c8092 | 2468 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 2469 | |
63c85238 PW |
2470 | /** |
2471 | * omap_hwmod_enable - enable an omap_hwmod | |
2472 | * @oh: struct omap_hwmod * | |
2473 | * | |
74ff3a68 | 2474 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
2475 | * Returns -EINVAL on error or passes along the return value from _enable(). |
2476 | */ | |
2477 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
2478 | { | |
2479 | int r; | |
dc6d1cda | 2480 | unsigned long flags; |
63c85238 PW |
2481 | |
2482 | if (!oh) | |
2483 | return -EINVAL; | |
2484 | ||
dc6d1cda PW |
2485 | spin_lock_irqsave(&oh->_lock, flags); |
2486 | r = _enable(oh); | |
2487 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2488 | |
2489 | return r; | |
2490 | } | |
2491 | ||
2492 | /** | |
2493 | * omap_hwmod_idle - idle an omap_hwmod | |
2494 | * @oh: struct omap_hwmod * | |
2495 | * | |
74ff3a68 | 2496 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
2497 | * Returns -EINVAL on error or passes along the return value from _idle(). |
2498 | */ | |
2499 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
2500 | { | |
dc6d1cda PW |
2501 | unsigned long flags; |
2502 | ||
63c85238 PW |
2503 | if (!oh) |
2504 | return -EINVAL; | |
2505 | ||
dc6d1cda PW |
2506 | spin_lock_irqsave(&oh->_lock, flags); |
2507 | _idle(oh); | |
2508 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2509 | |
2510 | return 0; | |
2511 | } | |
2512 | ||
2513 | /** | |
2514 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
2515 | * @oh: struct omap_hwmod * | |
2516 | * | |
74ff3a68 | 2517 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
2518 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
2519 | * the return value from _shutdown(). | |
2520 | */ | |
2521 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
2522 | { | |
dc6d1cda PW |
2523 | unsigned long flags; |
2524 | ||
63c85238 PW |
2525 | if (!oh) |
2526 | return -EINVAL; | |
2527 | ||
dc6d1cda | 2528 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2529 | _shutdown(oh); |
dc6d1cda | 2530 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2531 | |
2532 | return 0; | |
2533 | } | |
2534 | ||
2535 | /** | |
2536 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
2537 | * @oh: struct omap_hwmod *oh | |
2538 | * | |
2539 | * Intended to be called by the omap_device code. | |
2540 | */ | |
2541 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
2542 | { | |
dc6d1cda PW |
2543 | unsigned long flags; |
2544 | ||
2545 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2546 | _enable_clocks(oh); |
dc6d1cda | 2547 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2548 | |
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | /** | |
2553 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
2554 | * @oh: struct omap_hwmod *oh | |
2555 | * | |
2556 | * Intended to be called by the omap_device code. | |
2557 | */ | |
2558 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
2559 | { | |
dc6d1cda PW |
2560 | unsigned long flags; |
2561 | ||
2562 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2563 | _disable_clocks(oh); |
dc6d1cda | 2564 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2565 | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | /** | |
2570 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
2571 | * @oh: struct omap_hwmod *oh | |
2572 | * | |
2573 | * Intended to be called by drivers and core code when all posted | |
2574 | * writes to a device must complete before continuing further | |
2575 | * execution (for example, after clearing some device IRQSTATUS | |
2576 | * register bits) | |
2577 | * | |
2578 | * XXX what about targets with multiple OCP threads? | |
2579 | */ | |
2580 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
2581 | { | |
2582 | BUG_ON(!oh); | |
2583 | ||
43b40992 | 2584 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
2585 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
2586 | oh->name); | |
63c85238 PW |
2587 | return; |
2588 | } | |
2589 | ||
2590 | /* | |
2591 | * Forces posted writes to complete on the OCP thread handling | |
2592 | * register writes | |
2593 | */ | |
cc7a1d2a | 2594 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
2595 | } |
2596 | ||
2597 | /** | |
2598 | * omap_hwmod_reset - reset the hwmod | |
2599 | * @oh: struct omap_hwmod * | |
2600 | * | |
2601 | * Under some conditions, a driver may wish to reset the entire device. | |
2602 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 2603 | * the return value from _reset(). |
63c85238 PW |
2604 | */ |
2605 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
2606 | { | |
2607 | int r; | |
dc6d1cda | 2608 | unsigned long flags; |
63c85238 | 2609 | |
9b579114 | 2610 | if (!oh) |
63c85238 PW |
2611 | return -EINVAL; |
2612 | ||
dc6d1cda | 2613 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2614 | r = _reset(oh); |
dc6d1cda | 2615 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2616 | |
2617 | return r; | |
2618 | } | |
2619 | ||
5e8370f1 PW |
2620 | /* |
2621 | * IP block data retrieval functions | |
2622 | */ | |
2623 | ||
63c85238 PW |
2624 | /** |
2625 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
2626 | * @oh: struct omap_hwmod * | |
2627 | * @res: pointer to the first element of an array of struct resource to fill | |
2628 | * | |
2629 | * Count the number of struct resource array elements necessary to | |
2630 | * contain omap_hwmod @oh resources. Intended to be called by code | |
2631 | * that registers omap_devices. Intended to be used to determine the | |
2632 | * size of a dynamically-allocated struct resource array, before | |
2633 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
2634 | * resource array elements needed. | |
2635 | * | |
2636 | * XXX This code is not optimized. It could attempt to merge adjacent | |
2637 | * resource IDs. | |
2638 | * | |
2639 | */ | |
2640 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
2641 | { | |
5d95dde7 PW |
2642 | struct omap_hwmod_ocp_if *os; |
2643 | int ret; | |
2644 | int i = 0; | |
63c85238 | 2645 | |
bc614958 | 2646 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 2647 | |
5d95dde7 PW |
2648 | while (i < oh->slaves_cnt) { |
2649 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
2650 | ret += _count_ocp_if_addr_spaces(os); | |
2651 | } | |
63c85238 PW |
2652 | |
2653 | return ret; | |
2654 | } | |
2655 | ||
2656 | /** | |
2657 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
2658 | * @oh: struct omap_hwmod * | |
2659 | * @res: pointer to the first element of an array of struct resource to fill | |
2660 | * | |
2661 | * Fill the struct resource array @res with resource data from the | |
2662 | * omap_hwmod @oh. Intended to be called by code that registers | |
2663 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
2664 | * number of array elements filled. | |
2665 | */ | |
2666 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
2667 | { | |
5d95dde7 PW |
2668 | struct omap_hwmod_ocp_if *os; |
2669 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; | |
63c85238 PW |
2670 | int r = 0; |
2671 | ||
2672 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
2673 | ||
212738a4 PW |
2674 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
2675 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
2676 | (res + r)->name = (oh->mpu_irqs + i)->name; |
2677 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
2678 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
2679 | (res + r)->flags = IORESOURCE_IRQ; |
2680 | r++; | |
2681 | } | |
2682 | ||
bc614958 PW |
2683 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
2684 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
2685 | (res + r)->name = (oh->sdma_reqs + i)->name; |
2686 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
2687 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
2688 | (res + r)->flags = IORESOURCE_DMA; |
2689 | r++; | |
2690 | } | |
2691 | ||
5d95dde7 PW |
2692 | i = 0; |
2693 | while (i < oh->slaves_cnt) { | |
2694 | os = _fetch_next_ocp_if(NULL, oh->slaves, &i); | |
78183f3f | 2695 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 2696 | |
78183f3f | 2697 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 2698 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
2699 | (res + r)->start = (os->addr + j)->pa_start; |
2700 | (res + r)->end = (os->addr + j)->pa_end; | |
2701 | (res + r)->flags = IORESOURCE_MEM; | |
2702 | r++; | |
2703 | } | |
2704 | } | |
2705 | ||
2706 | return r; | |
2707 | } | |
2708 | ||
5e8370f1 PW |
2709 | /** |
2710 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
2711 | * @oh: struct omap_hwmod * to operate on | |
2712 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
2713 | * @name: pointer to the name of the data to fetch (optional) | |
2714 | * @rsrc: pointer to a struct resource, allocated by the caller | |
2715 | * | |
2716 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
2717 | * data for the IP block pointed to by @oh. The data will be filled | |
2718 | * into a struct resource record pointed to by @rsrc. The struct | |
2719 | * resource must be allocated by the caller. When @name is non-null, | |
2720 | * the data associated with the matching entry in the IRQ/SDMA/address | |
2721 | * space hwmod data arrays will be returned. If @name is null, the | |
2722 | * first array entry will be returned. Data order is not meaningful | |
2723 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
2724 | * @name whenever possible to avoid unpredictable effects if hwmod | |
2725 | * data is later added that causes data ordering to change. This | |
2726 | * function is only intended for use by OMAP core code. Device | |
2727 | * drivers should not call this function - the appropriate bus-related | |
2728 | * data accessor functions should be used instead. Returns 0 upon | |
2729 | * success or a negative error code upon error. | |
2730 | */ | |
2731 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
2732 | const char *name, struct resource *rsrc) | |
2733 | { | |
2734 | int r; | |
2735 | unsigned int irq, dma; | |
2736 | u32 pa_start, pa_end; | |
2737 | ||
2738 | if (!oh || !rsrc) | |
2739 | return -EINVAL; | |
2740 | ||
2741 | if (type == IORESOURCE_IRQ) { | |
2742 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
2743 | if (r) | |
2744 | return r; | |
2745 | ||
2746 | rsrc->start = irq; | |
2747 | rsrc->end = irq; | |
2748 | } else if (type == IORESOURCE_DMA) { | |
2749 | r = _get_sdma_req_by_name(oh, name, &dma); | |
2750 | if (r) | |
2751 | return r; | |
2752 | ||
2753 | rsrc->start = dma; | |
2754 | rsrc->end = dma; | |
2755 | } else if (type == IORESOURCE_MEM) { | |
2756 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
2757 | if (r) | |
2758 | return r; | |
2759 | ||
2760 | rsrc->start = pa_start; | |
2761 | rsrc->end = pa_end; | |
2762 | } else { | |
2763 | return -EINVAL; | |
2764 | } | |
2765 | ||
2766 | rsrc->flags = type; | |
2767 | rsrc->name = name; | |
2768 | ||
2769 | return 0; | |
2770 | } | |
2771 | ||
63c85238 PW |
2772 | /** |
2773 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
2774 | * @oh: struct omap_hwmod * | |
2775 | * | |
2776 | * Return the powerdomain pointer associated with the OMAP module | |
2777 | * @oh's main clock. If @oh does not have a main clk, return the | |
2778 | * powerdomain associated with the interface clock associated with the | |
2779 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
2780 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
2781 | * success. | |
2782 | */ | |
2783 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
2784 | { | |
2785 | struct clk *c; | |
2d6141ba | 2786 | struct omap_hwmod_ocp_if *oi; |
63c85238 PW |
2787 | |
2788 | if (!oh) | |
2789 | return NULL; | |
2790 | ||
2791 | if (oh->_clk) { | |
2792 | c = oh->_clk; | |
2793 | } else { | |
2d6141ba PW |
2794 | oi = _find_mpu_rt_port(oh); |
2795 | if (!oi) | |
63c85238 | 2796 | return NULL; |
2d6141ba | 2797 | c = oi->_clk; |
63c85238 PW |
2798 | } |
2799 | ||
d5647c18 TG |
2800 | if (!c->clkdm) |
2801 | return NULL; | |
2802 | ||
63c85238 PW |
2803 | return c->clkdm->pwrdm.ptr; |
2804 | ||
2805 | } | |
2806 | ||
db2a60bf PW |
2807 | /** |
2808 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
2809 | * @oh: struct omap_hwmod * | |
2810 | * | |
2811 | * Returns the virtual address corresponding to the beginning of the | |
2812 | * module's register target, in the address range that is intended to | |
2813 | * be used by the MPU. Returns the virtual address upon success or NULL | |
2814 | * upon error. | |
2815 | */ | |
2816 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
2817 | { | |
2818 | if (!oh) | |
2819 | return NULL; | |
2820 | ||
2821 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
2822 | return NULL; | |
2823 | ||
2824 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
2825 | return NULL; | |
2826 | ||
2827 | return oh->_mpu_rt_va; | |
2828 | } | |
2829 | ||
63c85238 PW |
2830 | /** |
2831 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
2832 | * @oh: struct omap_hwmod * | |
2833 | * @init_oh: struct omap_hwmod * (initiator) | |
2834 | * | |
2835 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
2836 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2837 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2838 | * code needs to add/del initiator dependencies dynamically | |
2839 | * before/after accessing a device. Returns the return value from | |
2840 | * _add_initiator_dep(). | |
2841 | * | |
2842 | * XXX Keep a usecount in the clockdomain code | |
2843 | */ | |
2844 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
2845 | struct omap_hwmod *init_oh) | |
2846 | { | |
2847 | return _add_initiator_dep(oh, init_oh); | |
2848 | } | |
2849 | ||
2850 | /* | |
2851 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
2852 | * for context save/restore operations? | |
2853 | */ | |
2854 | ||
2855 | /** | |
2856 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
2857 | * @oh: struct omap_hwmod * | |
2858 | * @init_oh: struct omap_hwmod * (initiator) | |
2859 | * | |
2860 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
2861 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2862 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2863 | * code needs to add/del initiator dependencies dynamically | |
2864 | * before/after accessing a device. Returns the return value from | |
2865 | * _del_initiator_dep(). | |
2866 | * | |
2867 | * XXX Keep a usecount in the clockdomain code | |
2868 | */ | |
2869 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
2870 | struct omap_hwmod *init_oh) | |
2871 | { | |
2872 | return _del_initiator_dep(oh, init_oh); | |
2873 | } | |
2874 | ||
63c85238 PW |
2875 | /** |
2876 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
2877 | * @oh: struct omap_hwmod * | |
2878 | * | |
2879 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
2880 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
2881 | * this IP block if it has dynamic mux entries. Eventually this | |
2882 | * should set PRCM wakeup registers to cause the PRCM to receive | |
2883 | * wakeup events from the module. Does not set any wakeup routing | |
2884 | * registers beyond this point - if the module is to wake up any other | |
2885 | * module or subsystem, that must be set separately. Called by | |
2886 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
2887 | */ |
2888 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
2889 | { | |
dc6d1cda | 2890 | unsigned long flags; |
5a7ddcbd | 2891 | u32 v; |
dc6d1cda | 2892 | |
dc6d1cda | 2893 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
2894 | |
2895 | if (oh->class->sysc && | |
2896 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
2897 | v = oh->_sysc_cache; | |
2898 | _enable_wakeup(oh, &v); | |
2899 | _write_sysconfig(v, oh); | |
2900 | } | |
2901 | ||
eceec009 | 2902 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 2903 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2904 | |
2905 | return 0; | |
2906 | } | |
2907 | ||
2908 | /** | |
2909 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
2910 | * @oh: struct omap_hwmod * | |
2911 | * | |
2912 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
2913 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
2914 | * events for this IP block if it has dynamic mux entries. Eventually | |
2915 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
2916 | * wakeup events from the module. Does not set any wakeup routing | |
2917 | * registers beyond this point - if the module is to wake up any other | |
2918 | * module or subsystem, that must be set separately. Called by | |
2919 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
2920 | */ |
2921 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
2922 | { | |
dc6d1cda | 2923 | unsigned long flags; |
5a7ddcbd | 2924 | u32 v; |
dc6d1cda | 2925 | |
dc6d1cda | 2926 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
2927 | |
2928 | if (oh->class->sysc && | |
2929 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
2930 | v = oh->_sysc_cache; | |
2931 | _disable_wakeup(oh, &v); | |
2932 | _write_sysconfig(v, oh); | |
2933 | } | |
2934 | ||
eceec009 | 2935 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 2936 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2937 | |
2938 | return 0; | |
2939 | } | |
43b40992 | 2940 | |
aee48e3c PW |
2941 | /** |
2942 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
2943 | * contained in the hwmod module. | |
2944 | * @oh: struct omap_hwmod * | |
2945 | * @name: name of the reset line to lookup and assert | |
2946 | * | |
2947 | * Some IP like dsp, ipu or iva contain processor that require | |
2948 | * an HW reset line to be assert / deassert in order to enable fully | |
2949 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2950 | * yet supported on this OMAP; otherwise, passes along the return value | |
2951 | * from _assert_hardreset(). | |
2952 | */ | |
2953 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
2954 | { | |
2955 | int ret; | |
dc6d1cda | 2956 | unsigned long flags; |
aee48e3c PW |
2957 | |
2958 | if (!oh) | |
2959 | return -EINVAL; | |
2960 | ||
dc6d1cda | 2961 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2962 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 2963 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2964 | |
2965 | return ret; | |
2966 | } | |
2967 | ||
2968 | /** | |
2969 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
2970 | * contained in the hwmod module. | |
2971 | * @oh: struct omap_hwmod * | |
2972 | * @name: name of the reset line to look up and deassert | |
2973 | * | |
2974 | * Some IP like dsp, ipu or iva contain processor that require | |
2975 | * an HW reset line to be assert / deassert in order to enable fully | |
2976 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2977 | * yet supported on this OMAP; otherwise, passes along the return value | |
2978 | * from _deassert_hardreset(). | |
2979 | */ | |
2980 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
2981 | { | |
2982 | int ret; | |
dc6d1cda | 2983 | unsigned long flags; |
aee48e3c PW |
2984 | |
2985 | if (!oh) | |
2986 | return -EINVAL; | |
2987 | ||
dc6d1cda | 2988 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2989 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 2990 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2991 | |
2992 | return ret; | |
2993 | } | |
2994 | ||
2995 | /** | |
2996 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
2997 | * contained in the hwmod module | |
2998 | * @oh: struct omap_hwmod * | |
2999 | * @name: name of the reset line to look up and read | |
3000 | * | |
3001 | * Return the current state of the hwmod @oh's reset line named @name: | |
3002 | * returns -EINVAL upon parameter error or if this operation | |
3003 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3004 | * value from _read_hardreset(). | |
3005 | */ | |
3006 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3007 | { | |
3008 | int ret; | |
dc6d1cda | 3009 | unsigned long flags; |
aee48e3c PW |
3010 | |
3011 | if (!oh) | |
3012 | return -EINVAL; | |
3013 | ||
dc6d1cda | 3014 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3015 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3016 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3017 | |
3018 | return ret; | |
3019 | } | |
3020 | ||
3021 | ||
43b40992 PW |
3022 | /** |
3023 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3024 | * @classname: struct omap_hwmod_class name to search for | |
3025 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3026 | * @user: arbitrary context data to pass to the callback function | |
3027 | * | |
ce35b244 BC |
3028 | * For each omap_hwmod of class @classname, call @fn. |
3029 | * If the callback function returns something other than | |
43b40992 PW |
3030 | * zero, the iterator is terminated, and the callback function's return |
3031 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3032 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3033 | */ | |
3034 | int omap_hwmod_for_each_by_class(const char *classname, | |
3035 | int (*fn)(struct omap_hwmod *oh, | |
3036 | void *user), | |
3037 | void *user) | |
3038 | { | |
3039 | struct omap_hwmod *temp_oh; | |
3040 | int ret = 0; | |
3041 | ||
3042 | if (!classname || !fn) | |
3043 | return -EINVAL; | |
3044 | ||
3045 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3046 | __func__, classname); | |
3047 | ||
43b40992 PW |
3048 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3049 | if (!strcmp(temp_oh->class->name, classname)) { | |
3050 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3051 | __func__, temp_oh->name); | |
3052 | ret = (*fn)(temp_oh, user); | |
3053 | if (ret) | |
3054 | break; | |
3055 | } | |
3056 | } | |
3057 | ||
43b40992 PW |
3058 | if (ret) |
3059 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3060 | __func__, ret); | |
3061 | ||
3062 | return ret; | |
3063 | } | |
3064 | ||
2092e5cc PW |
3065 | /** |
3066 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3067 | * @oh: struct omap_hwmod * | |
3068 | * @state: state that _setup() should leave the hwmod in | |
3069 | * | |
550c8092 | 3070 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3071 | * (called by omap_hwmod_setup_*()). See also the documentation |
3072 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3073 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3074 | * in the wrong state. | |
2092e5cc PW |
3075 | */ |
3076 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3077 | { | |
3078 | int ret; | |
dc6d1cda | 3079 | unsigned long flags; |
2092e5cc PW |
3080 | |
3081 | if (!oh) | |
3082 | return -EINVAL; | |
3083 | ||
3084 | if (state != _HWMOD_STATE_DISABLED && | |
3085 | state != _HWMOD_STATE_ENABLED && | |
3086 | state != _HWMOD_STATE_IDLE) | |
3087 | return -EINVAL; | |
3088 | ||
dc6d1cda | 3089 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3090 | |
3091 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3092 | ret = -EINVAL; | |
3093 | goto ohsps_unlock; | |
3094 | } | |
3095 | ||
3096 | oh->_postsetup_state = state; | |
3097 | ret = 0; | |
3098 | ||
3099 | ohsps_unlock: | |
dc6d1cda | 3100 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3101 | |
3102 | return ret; | |
3103 | } | |
c80705aa KH |
3104 | |
3105 | /** | |
3106 | * omap_hwmod_get_context_loss_count - get lost context count | |
3107 | * @oh: struct omap_hwmod * | |
3108 | * | |
3109 | * Query the powerdomain of of @oh to get the context loss | |
3110 | * count for this device. | |
3111 | * | |
3112 | * Returns the context loss count of the powerdomain assocated with @oh | |
3113 | * upon success, or zero if no powerdomain exists for @oh. | |
3114 | */ | |
fc013873 | 3115 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3116 | { |
3117 | struct powerdomain *pwrdm; | |
3118 | int ret = 0; | |
3119 | ||
3120 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3121 | if (pwrdm) | |
3122 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3123 | ||
3124 | return ret; | |
3125 | } | |
43b01643 PW |
3126 | |
3127 | /** | |
3128 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3129 | * @oh: struct omap_hwmod * | |
3130 | * | |
3131 | * Prevent the hwmod @oh from being reset during the setup process. | |
3132 | * Intended for use by board-*.c files on boards with devices that | |
3133 | * cannot tolerate being reset. Must be called before the hwmod has | |
3134 | * been set up. Returns 0 upon success or negative error code upon | |
3135 | * failure. | |
3136 | */ | |
3137 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3138 | { | |
3139 | if (!oh) | |
3140 | return -EINVAL; | |
3141 | ||
3142 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3143 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3144 | oh->name); | |
3145 | return -EINVAL; | |
3146 | } | |
3147 | ||
3148 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3149 | ||
3150 | return 0; | |
3151 | } | |
abc2d545 TK |
3152 | |
3153 | /** | |
3154 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3155 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3156 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3157 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3158 | * | |
3159 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3160 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3161 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3162 | * this function is not called for a given pad_idx, then the ISR | |
3163 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3164 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3165 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3166 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3167 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3168 | * must be called separately for each pad that requires its interrupt | |
3169 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3170 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3171 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3172 | * | |
3173 | * XXX This function interface is fragile. Rather than using array | |
3174 | * indexes, which are subject to unpredictable change, it should be | |
3175 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3176 | * pad records. | |
3177 | */ | |
3178 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3179 | { | |
3180 | int nr_irqs; | |
3181 | ||
3182 | might_sleep(); | |
3183 | ||
3184 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3185 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3186 | return -EINVAL; | |
3187 | ||
3188 | /* Check the number of available mpu_irqs */ | |
3189 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3190 | ; | |
3191 | ||
3192 | if (irq_idx >= nr_irqs) | |
3193 | return -EINVAL; | |
3194 | ||
3195 | if (!oh->mux->irqs) { | |
3196 | /* XXX What frees this? */ | |
3197 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3198 | GFP_KERNEL); | |
3199 | if (!oh->mux->irqs) | |
3200 | return -ENOMEM; | |
3201 | } | |
3202 | oh->mux->irqs[pad_idx] = irq_idx; | |
3203 | ||
3204 | return 0; | |
3205 | } |