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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
63c85238 | 141 | |
4e65331c | 142 | #include "common.h" |
ce491cf8 | 143 | #include <plat/cpu.h> |
1540f214 | 144 | #include "clockdomain.h" |
72e06d08 | 145 | #include "powerdomain.h" |
ce491cf8 TL |
146 | #include <plat/clock.h> |
147 | #include <plat/omap_hwmod.h> | |
5365efbe | 148 | #include <plat/prcm.h> |
63c85238 | 149 | |
59fb659b | 150 | #include "cm2xxx_3xxx.h" |
d0f0631d | 151 | #include "cminst44xx.h" |
59fb659b | 152 | #include "prm2xxx_3xxx.h" |
d198b514 | 153 | #include "prm44xx.h" |
eaac329d | 154 | #include "prminst44xx.h" |
8d9af88f | 155 | #include "mux.h" |
63c85238 | 156 | |
5365efbe BC |
157 | /* Maximum microseconds to wait for OMAP module to softreset */ |
158 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
159 | |
160 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 161 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 162 | |
2221b5cd PW |
163 | /* |
164 | * Number of struct omap_hwmod_link records per struct | |
165 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
166 | */ | |
167 | #define LINKS_PER_OCP_IF 2 | |
168 | ||
9ebfd285 KH |
169 | /** |
170 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
171 | * @enable_module: function to enable a module (via MODULEMODE) | |
172 | * @disable_module: function to disable a module (via MODULEMODE) | |
173 | * | |
174 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
175 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
176 | * conditionals in this code. | |
177 | */ | |
178 | struct omap_hwmod_soc_ops { | |
179 | void (*enable_module)(struct omap_hwmod *oh); | |
180 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 181 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
182 | int (*assert_hardreset)(struct omap_hwmod *oh, |
183 | struct omap_hwmod_rst_info *ohri); | |
184 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
185 | struct omap_hwmod_rst_info *ohri); | |
186 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
187 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 188 | int (*init_clkdm)(struct omap_hwmod *oh); |
9ebfd285 KH |
189 | }; |
190 | ||
191 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
192 | static struct omap_hwmod_soc_ops soc_ops; | |
193 | ||
63c85238 PW |
194 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
195 | static LIST_HEAD(omap_hwmod_list); | |
196 | ||
63c85238 PW |
197 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
198 | static struct omap_hwmod *mpu_oh; | |
199 | ||
2221b5cd PW |
200 | /* |
201 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
202 | * allocated from - used to reduce the number of small memory | |
203 | * allocations, which has a significant impact on performance | |
204 | */ | |
205 | static struct omap_hwmod_link *linkspace; | |
206 | ||
207 | /* | |
208 | * free_ls, max_ls: array indexes into linkspace; representing the | |
209 | * next free struct omap_hwmod_link index, and the maximum number of | |
210 | * struct omap_hwmod_link records allocated (respectively) | |
211 | */ | |
212 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 213 | |
9ebfd285 KH |
214 | /* inited: set to true once the hwmod code is initialized */ |
215 | static bool inited; | |
216 | ||
63c85238 PW |
217 | /* Private functions */ |
218 | ||
5d95dde7 | 219 | /** |
11cd4b94 | 220 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 221 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
222 | * @i: pointer to the index of the element pointed to by @p in the list |
223 | * | |
224 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
225 | * containing the struct list_head pointed to by @p, and increment | |
226 | * @p such that a future call to this routine will return the next | |
227 | * record. | |
5d95dde7 PW |
228 | */ |
229 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
230 | int *i) |
231 | { | |
232 | struct omap_hwmod_ocp_if *oi; | |
233 | ||
11cd4b94 PW |
234 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
235 | *p = (*p)->next; | |
2221b5cd | 236 | |
5d95dde7 PW |
237 | *i = *i + 1; |
238 | ||
239 | return oi; | |
240 | } | |
241 | ||
63c85238 PW |
242 | /** |
243 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
244 | * @oh: struct omap_hwmod * | |
245 | * | |
246 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
247 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
248 | * OCP_SYSCONFIG register or 0 upon success. | |
249 | */ | |
250 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
251 | { | |
43b40992 PW |
252 | if (!oh->class->sysc) { |
253 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
254 | return -EINVAL; |
255 | } | |
256 | ||
257 | /* XXX ensure module interface clock is up */ | |
258 | ||
cc7a1d2a | 259 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 260 | |
43b40992 | 261 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 262 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
263 | |
264 | return 0; | |
265 | } | |
266 | ||
267 | /** | |
268 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
269 | * @v: OCP_SYSCONFIG value to write | |
270 | * @oh: struct omap_hwmod * | |
271 | * | |
43b40992 PW |
272 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
273 | * one. No return value. | |
63c85238 PW |
274 | */ |
275 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
276 | { | |
43b40992 PW |
277 | if (!oh->class->sysc) { |
278 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
279 | return; |
280 | } | |
281 | ||
282 | /* XXX ensure module interface clock is up */ | |
283 | ||
233cbe5b RN |
284 | /* Module might have lost context, always update cache and register */ |
285 | oh->_sysc_cache = v; | |
286 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
287 | } |
288 | ||
289 | /** | |
290 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
291 | * @oh: struct omap_hwmod * | |
292 | * @standbymode: MIDLEMODE field bits | |
293 | * @v: pointer to register contents to modify | |
294 | * | |
295 | * Update the master standby mode bits in @v to be @standbymode for | |
296 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
297 | * upon error or 0 upon success. | |
298 | */ | |
299 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
300 | u32 *v) | |
301 | { | |
358f0e63 TG |
302 | u32 mstandby_mask; |
303 | u8 mstandby_shift; | |
304 | ||
43b40992 PW |
305 | if (!oh->class->sysc || |
306 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
307 | return -EINVAL; |
308 | ||
43b40992 PW |
309 | if (!oh->class->sysc->sysc_fields) { |
310 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
311 | return -EINVAL; |
312 | } | |
313 | ||
43b40992 | 314 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
315 | mstandby_mask = (0x3 << mstandby_shift); |
316 | ||
317 | *v &= ~mstandby_mask; | |
318 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
319 | |
320 | return 0; | |
321 | } | |
322 | ||
323 | /** | |
324 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
325 | * @oh: struct omap_hwmod * | |
326 | * @idlemode: SIDLEMODE field bits | |
327 | * @v: pointer to register contents to modify | |
328 | * | |
329 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
330 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
331 | * or 0 upon success. | |
332 | */ | |
333 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
334 | { | |
358f0e63 TG |
335 | u32 sidle_mask; |
336 | u8 sidle_shift; | |
337 | ||
43b40992 PW |
338 | if (!oh->class->sysc || |
339 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
340 | return -EINVAL; |
341 | ||
43b40992 PW |
342 | if (!oh->class->sysc->sysc_fields) { |
343 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
344 | return -EINVAL; |
345 | } | |
346 | ||
43b40992 | 347 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
348 | sidle_mask = (0x3 << sidle_shift); |
349 | ||
350 | *v &= ~sidle_mask; | |
351 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
356 | /** | |
357 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
358 | * @oh: struct omap_hwmod * | |
359 | * @clockact: CLOCKACTIVITY field bits | |
360 | * @v: pointer to register contents to modify | |
361 | * | |
362 | * Update the clockactivity mode bits in @v to be @clockact for the | |
363 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
364 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
365 | * success. | |
366 | */ | |
367 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
368 | { | |
358f0e63 TG |
369 | u32 clkact_mask; |
370 | u8 clkact_shift; | |
371 | ||
43b40992 PW |
372 | if (!oh->class->sysc || |
373 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
374 | return -EINVAL; |
375 | ||
43b40992 PW |
376 | if (!oh->class->sysc->sysc_fields) { |
377 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
378 | return -EINVAL; |
379 | } | |
380 | ||
43b40992 | 381 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
382 | clkact_mask = (0x3 << clkact_shift); |
383 | ||
384 | *v &= ~clkact_mask; | |
385 | *v |= clockact << clkact_shift; | |
63c85238 PW |
386 | |
387 | return 0; | |
388 | } | |
389 | ||
390 | /** | |
391 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
392 | * @oh: struct omap_hwmod * | |
393 | * @v: pointer to register contents to modify | |
394 | * | |
395 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
396 | * error or 0 upon success. | |
397 | */ | |
398 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
399 | { | |
358f0e63 TG |
400 | u32 softrst_mask; |
401 | ||
43b40992 PW |
402 | if (!oh->class->sysc || |
403 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
404 | return -EINVAL; |
405 | ||
43b40992 PW |
406 | if (!oh->class->sysc->sysc_fields) { |
407 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
408 | return -EINVAL; |
409 | } | |
410 | ||
43b40992 | 411 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
412 | |
413 | *v |= softrst_mask; | |
63c85238 PW |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
6668546f KVA |
418 | /** |
419 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
420 | * @oh: struct omap_hwmod * | |
421 | * | |
422 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
423 | * of some modules. When the DMA must perform read/write accesses, the | |
424 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
425 | * for power management, software must set the DMADISABLE bit back to 1. | |
426 | * | |
427 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
428 | * error or 0 upon success. | |
429 | */ | |
430 | static int _set_dmadisable(struct omap_hwmod *oh) | |
431 | { | |
432 | u32 v; | |
433 | u32 dmadisable_mask; | |
434 | ||
435 | if (!oh->class->sysc || | |
436 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
437 | return -EINVAL; | |
438 | ||
439 | if (!oh->class->sysc->sysc_fields) { | |
440 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
441 | return -EINVAL; | |
442 | } | |
443 | ||
444 | /* clocks must be on for this operation */ | |
445 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
446 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
447 | return -EINVAL; | |
448 | } | |
449 | ||
450 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
451 | ||
452 | v = oh->_sysc_cache; | |
453 | dmadisable_mask = | |
454 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
455 | v |= dmadisable_mask; | |
456 | _write_sysconfig(v, oh); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
726072e5 PW |
461 | /** |
462 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
463 | * @oh: struct omap_hwmod * | |
464 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
465 | * @v: pointer to register contents to modify | |
466 | * | |
467 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
468 | * hwmod. The autoidle bit controls whether the module can gate | |
469 | * internal clocks automatically when it isn't doing anything; the | |
470 | * exact function of this bit varies on a per-module basis. This | |
471 | * function does not write to the hardware. Returns -EINVAL upon | |
472 | * error or 0 upon success. | |
473 | */ | |
474 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
475 | u32 *v) | |
476 | { | |
358f0e63 TG |
477 | u32 autoidle_mask; |
478 | u8 autoidle_shift; | |
479 | ||
43b40992 PW |
480 | if (!oh->class->sysc || |
481 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
482 | return -EINVAL; |
483 | ||
43b40992 PW |
484 | if (!oh->class->sysc->sysc_fields) { |
485 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
486 | return -EINVAL; |
487 | } | |
488 | ||
43b40992 | 489 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 490 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
491 | |
492 | *v &= ~autoidle_mask; | |
493 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
494 | |
495 | return 0; | |
496 | } | |
497 | ||
eceec009 G |
498 | /** |
499 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
500 | * @oh: struct omap_hwmod * | |
501 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
502 | * | |
503 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
504 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
505 | * in memory. If the hwmod is currently idled, and the new idle | |
506 | * values don't match the previous ones, this function will also | |
507 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
508 | * currently idled, this function won't touch the hardware: the new | |
509 | * mux settings are written to the SCM PADCTRL registers when the | |
510 | * hwmod is idled. No return value. | |
511 | */ | |
512 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
513 | { | |
514 | struct omap_device_pad *pad; | |
515 | bool change = false; | |
516 | u16 prev_idle; | |
517 | int j; | |
518 | ||
519 | if (!oh->mux || !oh->mux->enabled) | |
520 | return; | |
521 | ||
522 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
523 | pad = oh->mux->pads_dynamic[j]; | |
524 | ||
525 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
526 | continue; | |
527 | ||
528 | prev_idle = pad->idle; | |
529 | ||
530 | if (set_wake) | |
531 | pad->idle |= OMAP_WAKEUP_EN; | |
532 | else | |
533 | pad->idle &= ~OMAP_WAKEUP_EN; | |
534 | ||
535 | if (prev_idle != pad->idle) | |
536 | change = true; | |
537 | } | |
538 | ||
539 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
540 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
541 | } | |
542 | ||
63c85238 PW |
543 | /** |
544 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
545 | * @oh: struct omap_hwmod * | |
546 | * | |
547 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
548 | * upon error or 0 upon success. | |
549 | */ | |
5a7ddcbd | 550 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 551 | { |
43b40992 | 552 | if (!oh->class->sysc || |
86009eb3 | 553 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
554 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
555 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
556 | return -EINVAL; |
557 | ||
43b40992 PW |
558 | if (!oh->class->sysc->sysc_fields) { |
559 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
560 | return -EINVAL; |
561 | } | |
562 | ||
1fe74113 BC |
563 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
564 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 565 | |
86009eb3 BC |
566 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
567 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
568 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
569 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 570 | |
63c85238 PW |
571 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
572 | ||
573 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | /** | |
579 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
580 | * @oh: struct omap_hwmod * | |
581 | * | |
582 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
583 | * upon error or 0 upon success. | |
584 | */ | |
5a7ddcbd | 585 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 586 | { |
43b40992 | 587 | if (!oh->class->sysc || |
86009eb3 | 588 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
589 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
590 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
591 | return -EINVAL; |
592 | ||
43b40992 PW |
593 | if (!oh->class->sysc->sysc_fields) { |
594 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
595 | return -EINVAL; |
596 | } | |
597 | ||
1fe74113 BC |
598 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
599 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 600 | |
86009eb3 BC |
601 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
602 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 603 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 604 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 605 | |
63c85238 PW |
606 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
607 | ||
608 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | /** | |
614 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
615 | * @oh: struct omap_hwmod * | |
616 | * | |
617 | * Prevent the hardware module @oh from entering idle while the | |
618 | * hardare module initiator @init_oh is active. Useful when a module | |
619 | * will be accessed by a particular initiator (e.g., if a module will | |
620 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
621 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
622 | * mode. If the clockdomain is marked as not needing autodeps, return |
623 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
624 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
625 | */ |
626 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
627 | { | |
628 | if (!oh->_clk) | |
629 | return -EINVAL; | |
630 | ||
570b54c7 PW |
631 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
632 | return 0; | |
633 | ||
55ed9694 | 634 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
635 | } |
636 | ||
637 | /** | |
638 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
639 | * @oh: struct omap_hwmod * | |
640 | * | |
641 | * Allow the hardware module @oh to enter idle while the hardare | |
642 | * module initiator @init_oh is active. Useful when a module will not | |
643 | * be accessed by a particular initiator (e.g., if a module will not | |
644 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
645 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
646 | * mode. If the clockdomain is marked as not needing autodeps, return |
647 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
648 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
649 | */ |
650 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
651 | { | |
652 | if (!oh->_clk) | |
653 | return -EINVAL; | |
654 | ||
570b54c7 PW |
655 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
656 | return 0; | |
657 | ||
55ed9694 | 658 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
659 | } |
660 | ||
661 | /** | |
662 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
663 | * @oh: struct omap_hwmod * | |
664 | * | |
665 | * Called from _init_clocks(). Populates the @oh _clk (main | |
666 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
667 | * success or -EINVAL on error. | |
668 | */ | |
669 | static int _init_main_clk(struct omap_hwmod *oh) | |
670 | { | |
63c85238 PW |
671 | int ret = 0; |
672 | ||
50ebdac2 | 673 | if (!oh->main_clk) |
63c85238 PW |
674 | return 0; |
675 | ||
63403384 | 676 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 677 | if (!oh->_clk) { |
20383d82 BC |
678 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
679 | oh->name, oh->main_clk); | |
63403384 | 680 | return -EINVAL; |
dc75925d | 681 | } |
63c85238 | 682 | |
63403384 BC |
683 | if (!oh->_clk->clkdm) |
684 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
685 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 686 | |
63c85238 PW |
687 | return ret; |
688 | } | |
689 | ||
690 | /** | |
887adeac | 691 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
692 | * @oh: struct omap_hwmod * |
693 | * | |
694 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
695 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
696 | */ | |
697 | static int _init_interface_clks(struct omap_hwmod *oh) | |
698 | { | |
5d95dde7 | 699 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 700 | struct list_head *p; |
63c85238 | 701 | struct clk *c; |
5d95dde7 | 702 | int i = 0; |
63c85238 PW |
703 | int ret = 0; |
704 | ||
11cd4b94 | 705 | p = oh->slave_ports.next; |
2221b5cd | 706 | |
5d95dde7 | 707 | while (i < oh->slaves_cnt) { |
11cd4b94 | 708 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 709 | if (!os->clk) |
63c85238 PW |
710 | continue; |
711 | ||
50ebdac2 | 712 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 713 | if (!c) { |
20383d82 BC |
714 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
715 | oh->name, os->clk); | |
63c85238 | 716 | ret = -EINVAL; |
dc75925d | 717 | } |
63c85238 PW |
718 | os->_clk = c; |
719 | } | |
720 | ||
721 | return ret; | |
722 | } | |
723 | ||
724 | /** | |
725 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
726 | * @oh: struct omap_hwmod * | |
727 | * | |
728 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
729 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
730 | */ | |
731 | static int _init_opt_clks(struct omap_hwmod *oh) | |
732 | { | |
733 | struct omap_hwmod_opt_clk *oc; | |
734 | struct clk *c; | |
735 | int i; | |
736 | int ret = 0; | |
737 | ||
738 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 739 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 740 | if (!c) { |
20383d82 BC |
741 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
742 | oh->name, oc->clk); | |
63c85238 | 743 | ret = -EINVAL; |
dc75925d | 744 | } |
63c85238 PW |
745 | oc->_clk = c; |
746 | } | |
747 | ||
748 | return ret; | |
749 | } | |
750 | ||
751 | /** | |
752 | * _enable_clocks - enable hwmod main clock and interface clocks | |
753 | * @oh: struct omap_hwmod * | |
754 | * | |
755 | * Enables all clocks necessary for register reads and writes to succeed | |
756 | * on the hwmod @oh. Returns 0. | |
757 | */ | |
758 | static int _enable_clocks(struct omap_hwmod *oh) | |
759 | { | |
5d95dde7 | 760 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 761 | struct list_head *p; |
5d95dde7 | 762 | int i = 0; |
63c85238 PW |
763 | |
764 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
765 | ||
4d3ae5a9 | 766 | if (oh->_clk) |
63c85238 PW |
767 | clk_enable(oh->_clk); |
768 | ||
11cd4b94 | 769 | p = oh->slave_ports.next; |
2221b5cd | 770 | |
5d95dde7 | 771 | while (i < oh->slaves_cnt) { |
11cd4b94 | 772 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 773 | |
5d95dde7 PW |
774 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
775 | clk_enable(os->_clk); | |
63c85238 PW |
776 | } |
777 | ||
778 | /* The opt clocks are controlled by the device driver. */ | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | /** | |
784 | * _disable_clocks - disable hwmod main clock and interface clocks | |
785 | * @oh: struct omap_hwmod * | |
786 | * | |
787 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
788 | */ | |
789 | static int _disable_clocks(struct omap_hwmod *oh) | |
790 | { | |
5d95dde7 | 791 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 792 | struct list_head *p; |
5d95dde7 | 793 | int i = 0; |
63c85238 PW |
794 | |
795 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
796 | ||
4d3ae5a9 | 797 | if (oh->_clk) |
63c85238 PW |
798 | clk_disable(oh->_clk); |
799 | ||
11cd4b94 | 800 | p = oh->slave_ports.next; |
2221b5cd | 801 | |
5d95dde7 | 802 | while (i < oh->slaves_cnt) { |
11cd4b94 | 803 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 804 | |
5d95dde7 PW |
805 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
806 | clk_disable(os->_clk); | |
63c85238 PW |
807 | } |
808 | ||
809 | /* The opt clocks are controlled by the device driver. */ | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
96835af9 BC |
814 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
815 | { | |
816 | struct omap_hwmod_opt_clk *oc; | |
817 | int i; | |
818 | ||
819 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
820 | ||
821 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
822 | if (oc->_clk) { | |
823 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
824 | oc->_clk->name); | |
825 | clk_enable(oc->_clk); | |
826 | } | |
827 | } | |
828 | ||
829 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
830 | { | |
831 | struct omap_hwmod_opt_clk *oc; | |
832 | int i; | |
833 | ||
834 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
835 | ||
836 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
837 | if (oc->_clk) { | |
838 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
839 | oc->_clk->name); | |
840 | clk_disable(oc->_clk); | |
841 | } | |
842 | } | |
843 | ||
45c38252 | 844 | /** |
3d9f0327 | 845 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
846 | * @oh: struct omap_hwmod * |
847 | * | |
848 | * Enables the PRCM module mode related to the hwmod @oh. | |
849 | * No return value. | |
850 | */ | |
3d9f0327 | 851 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 852 | { |
45c38252 BC |
853 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
854 | return; | |
855 | ||
3d9f0327 KH |
856 | pr_debug("omap_hwmod: %s: %s: %d\n", |
857 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
858 | |
859 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
860 | oh->clkdm->prcm_partition, | |
861 | oh->clkdm->cm_inst, | |
862 | oh->clkdm->clkdm_offs, | |
863 | oh->prcm.omap4.clkctrl_offs); | |
864 | } | |
865 | ||
866 | /** | |
bfc141e3 BC |
867 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
868 | * @oh: struct omap_hwmod * | |
869 | * | |
870 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
871 | * does not have an IDLEST bit or if the module successfully enters | |
872 | * slave idle; otherwise, pass along the return value of the | |
873 | * appropriate *_cm*_wait_module_idle() function. | |
874 | */ | |
875 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
876 | { | |
868c157d | 877 | if (!oh || !oh->clkdm) |
bfc141e3 BC |
878 | return -EINVAL; |
879 | ||
880 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
881 | return 0; | |
882 | ||
883 | if (oh->flags & HWMOD_NO_IDLEST) | |
884 | return 0; | |
885 | ||
886 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
887 | oh->clkdm->cm_inst, | |
888 | oh->clkdm->clkdm_offs, | |
889 | oh->prcm.omap4.clkctrl_offs); | |
890 | } | |
891 | ||
212738a4 PW |
892 | /** |
893 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
894 | * @oh: struct omap_hwmod *oh | |
895 | * | |
896 | * Count and return the number of MPU IRQs associated with the hwmod | |
897 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
898 | * NULL. | |
899 | */ | |
900 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
901 | { | |
902 | struct omap_hwmod_irq_info *ohii; | |
903 | int i = 0; | |
904 | ||
905 | if (!oh || !oh->mpu_irqs) | |
906 | return 0; | |
907 | ||
908 | do { | |
909 | ohii = &oh->mpu_irqs[i++]; | |
910 | } while (ohii->irq != -1); | |
911 | ||
cc1b0765 | 912 | return i-1; |
212738a4 PW |
913 | } |
914 | ||
bc614958 PW |
915 | /** |
916 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
917 | * @oh: struct omap_hwmod *oh | |
918 | * | |
919 | * Count and return the number of SDMA request lines associated with | |
920 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
921 | * if @oh is NULL. | |
922 | */ | |
923 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
924 | { | |
925 | struct omap_hwmod_dma_info *ohdi; | |
926 | int i = 0; | |
927 | ||
928 | if (!oh || !oh->sdma_reqs) | |
929 | return 0; | |
930 | ||
931 | do { | |
932 | ohdi = &oh->sdma_reqs[i++]; | |
933 | } while (ohdi->dma_req != -1); | |
934 | ||
cc1b0765 | 935 | return i-1; |
bc614958 PW |
936 | } |
937 | ||
78183f3f PW |
938 | /** |
939 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
940 | * @oh: struct omap_hwmod *oh | |
941 | * | |
942 | * Count and return the number of address space ranges associated with | |
943 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
944 | * if @oh is NULL. | |
945 | */ | |
946 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
947 | { | |
948 | struct omap_hwmod_addr_space *mem; | |
949 | int i = 0; | |
950 | ||
951 | if (!os || !os->addr) | |
952 | return 0; | |
953 | ||
954 | do { | |
955 | mem = &os->addr[i++]; | |
956 | } while (mem->pa_start != mem->pa_end); | |
957 | ||
cc1b0765 | 958 | return i-1; |
78183f3f PW |
959 | } |
960 | ||
5e8370f1 PW |
961 | /** |
962 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
963 | * @oh: struct omap_hwmod * to operate on | |
964 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
965 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
966 | * | |
967 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
968 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
969 | * into the address pointed to by @dma. When @name is non-null, the | |
970 | * IRQ line number associated with the named entry will be returned. | |
971 | * If @name is null, the first matching entry will be returned. Data | |
972 | * order is not meaningful in hwmod data, so callers are strongly | |
973 | * encouraged to use a non-null @name whenever possible to avoid | |
974 | * unpredictable effects if hwmod data is later added that causes data | |
975 | * ordering to change. Returns 0 upon success or a negative error | |
976 | * code upon error. | |
977 | */ | |
978 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
979 | unsigned int *irq) | |
980 | { | |
981 | int i; | |
982 | bool found = false; | |
983 | ||
984 | if (!oh->mpu_irqs) | |
985 | return -ENOENT; | |
986 | ||
987 | i = 0; | |
988 | while (oh->mpu_irqs[i].irq != -1) { | |
989 | if (name == oh->mpu_irqs[i].name || | |
990 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
991 | found = true; | |
992 | break; | |
993 | } | |
994 | i++; | |
995 | } | |
996 | ||
997 | if (!found) | |
998 | return -ENOENT; | |
999 | ||
1000 | *irq = oh->mpu_irqs[i].irq; | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | /** | |
1006 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1007 | * @oh: struct omap_hwmod * to operate on | |
1008 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1009 | * @dma: pointer to an unsigned int to store the request line ID to | |
1010 | * | |
1011 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1012 | * pointed to by @oh. The ID will be filled into the address pointed | |
1013 | * to by @dma. When @name is non-null, the request line ID associated | |
1014 | * with the named entry will be returned. If @name is null, the first | |
1015 | * matching entry will be returned. Data order is not meaningful in | |
1016 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1017 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1018 | * data is later added that causes data ordering to change. Returns 0 | |
1019 | * upon success or a negative error code upon error. | |
1020 | */ | |
1021 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1022 | unsigned int *dma) | |
1023 | { | |
1024 | int i; | |
1025 | bool found = false; | |
1026 | ||
1027 | if (!oh->sdma_reqs) | |
1028 | return -ENOENT; | |
1029 | ||
1030 | i = 0; | |
1031 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1032 | if (name == oh->sdma_reqs[i].name || | |
1033 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1034 | found = true; | |
1035 | break; | |
1036 | } | |
1037 | i++; | |
1038 | } | |
1039 | ||
1040 | if (!found) | |
1041 | return -ENOENT; | |
1042 | ||
1043 | *dma = oh->sdma_reqs[i].dma_req; | |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | /** | |
1049 | * _get_addr_space_by_name - fetch address space start & end by name | |
1050 | * @oh: struct omap_hwmod * to operate on | |
1051 | * @name: pointer to the name of the address space to fetch (optional) | |
1052 | * @pa_start: pointer to a u32 to store the starting address to | |
1053 | * @pa_end: pointer to a u32 to store the ending address to | |
1054 | * | |
1055 | * Retrieve address space start and end addresses for the IP block | |
1056 | * pointed to by @oh. The data will be filled into the addresses | |
1057 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1058 | * address space data associated with the named entry will be | |
1059 | * returned. If @name is null, the first matching entry will be | |
1060 | * returned. Data order is not meaningful in hwmod data, so callers | |
1061 | * are strongly encouraged to use a non-null @name whenever possible | |
1062 | * to avoid unpredictable effects if hwmod data is later added that | |
1063 | * causes data ordering to change. Returns 0 upon success or a | |
1064 | * negative error code upon error. | |
1065 | */ | |
1066 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1067 | u32 *pa_start, u32 *pa_end) | |
1068 | { | |
1069 | int i, j; | |
1070 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1071 | struct list_head *p = NULL; |
5e8370f1 PW |
1072 | bool found = false; |
1073 | ||
11cd4b94 | 1074 | p = oh->slave_ports.next; |
2221b5cd | 1075 | |
5d95dde7 PW |
1076 | i = 0; |
1077 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1078 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1079 | |
1080 | if (!os->addr) | |
1081 | return -ENOENT; | |
1082 | ||
1083 | j = 0; | |
1084 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1085 | if (name == os->addr[j].name || | |
1086 | !strcmp(name, os->addr[j].name)) { | |
1087 | found = true; | |
1088 | break; | |
1089 | } | |
1090 | j++; | |
1091 | } | |
1092 | ||
1093 | if (found) | |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | if (!found) | |
1098 | return -ENOENT; | |
1099 | ||
1100 | *pa_start = os->addr[j].pa_start; | |
1101 | *pa_end = os->addr[j].pa_end; | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
63c85238 | 1106 | /** |
24dbc213 | 1107 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1108 | * @oh: struct omap_hwmod * |
1109 | * | |
24dbc213 PW |
1110 | * Determines the array index of the OCP slave port that the MPU uses |
1111 | * to address the device, and saves it into the struct omap_hwmod. | |
1112 | * Intended to be called during hwmod registration only. No return | |
1113 | * value. | |
63c85238 | 1114 | */ |
24dbc213 | 1115 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1116 | { |
24dbc213 | 1117 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1118 | struct list_head *p; |
5d95dde7 | 1119 | int i = 0; |
63c85238 | 1120 | |
5d95dde7 | 1121 | if (!oh) |
24dbc213 PW |
1122 | return; |
1123 | ||
1124 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1125 | |
11cd4b94 | 1126 | p = oh->slave_ports.next; |
2221b5cd | 1127 | |
5d95dde7 | 1128 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1129 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1130 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1131 | oh->_mpu_port = os; |
24dbc213 | 1132 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1133 | break; |
1134 | } | |
1135 | } | |
1136 | ||
24dbc213 | 1137 | return; |
63c85238 PW |
1138 | } |
1139 | ||
2d6141ba PW |
1140 | /** |
1141 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1142 | * @oh: struct omap_hwmod * | |
1143 | * | |
1144 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1145 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1146 | * communicate with the IP block. This interface need not be directly | |
1147 | * connected to the MPU (and almost certainly is not), but is directly | |
1148 | * connected to the IP block represented by @oh. Returns a pointer | |
1149 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1150 | * error or if there does not appear to be a path from the MPU to this | |
1151 | * IP block. | |
1152 | */ | |
1153 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1154 | { | |
1155 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1156 | return NULL; | |
1157 | ||
11cd4b94 | 1158 | return oh->_mpu_port; |
2d6141ba PW |
1159 | }; |
1160 | ||
63c85238 | 1161 | /** |
c9aafd23 | 1162 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1163 | * @oh: struct omap_hwmod * |
1164 | * | |
c9aafd23 PW |
1165 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1166 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1167 | */ |
c9aafd23 | 1168 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1169 | { |
1170 | struct omap_hwmod_ocp_if *os; | |
1171 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1172 | int found = 0, i = 0; |
63c85238 | 1173 | |
2d6141ba | 1174 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1175 | if (!os || !os->addr) |
78183f3f PW |
1176 | return NULL; |
1177 | ||
1178 | do { | |
1179 | mem = &os->addr[i++]; | |
1180 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1181 | found = 1; |
78183f3f | 1182 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1183 | |
c9aafd23 | 1184 | return (found) ? mem : NULL; |
63c85238 PW |
1185 | } |
1186 | ||
1187 | /** | |
74ff3a68 | 1188 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1189 | * @oh: struct omap_hwmod * |
1190 | * | |
1191 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
1192 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1193 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
1194 | * otherwise, configure it for smart-standby. No return value. | |
1195 | */ | |
74ff3a68 | 1196 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1197 | { |
43b40992 | 1198 | u8 idlemode, sf; |
63c85238 PW |
1199 | u32 v; |
1200 | ||
43b40992 | 1201 | if (!oh->class->sysc) |
63c85238 PW |
1202 | return; |
1203 | ||
1204 | v = oh->_sysc_cache; | |
43b40992 | 1205 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1206 | |
43b40992 | 1207 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
1208 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
1209 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
1210 | _set_slave_idlemode(oh, idlemode, &v); | |
1211 | } | |
1212 | ||
43b40992 | 1213 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1214 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1215 | idlemode = HWMOD_IDLEMODE_NO; | |
1216 | } else { | |
1217 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1218 | _enable_wakeup(oh, &v); | |
1219 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1220 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1221 | else | |
1222 | idlemode = HWMOD_IDLEMODE_SMART; | |
1223 | } | |
63c85238 PW |
1224 | _set_master_standbymode(oh, idlemode, &v); |
1225 | } | |
1226 | ||
a16b1f7f PW |
1227 | /* |
1228 | * XXX The clock framework should handle this, by | |
1229 | * calling into this code. But this must wait until the | |
1230 | * clock structures are tagged with omap_hwmod entries | |
1231 | */ | |
43b40992 PW |
1232 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1233 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1234 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1235 | |
9980ce53 RN |
1236 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1237 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1238 | _enable_wakeup(oh, &v); |
1239 | ||
1240 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1241 | |
1242 | /* | |
1243 | * Set the autoidle bit only after setting the smartidle bit | |
1244 | * Setting this will not have any impact on the other modules. | |
1245 | */ | |
1246 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1247 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1248 | 0 : 1; | |
1249 | _set_module_autoidle(oh, idlemode, &v); | |
1250 | _write_sysconfig(v, oh); | |
1251 | } | |
63c85238 PW |
1252 | } |
1253 | ||
1254 | /** | |
74ff3a68 | 1255 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1256 | * @oh: struct omap_hwmod * |
1257 | * | |
1258 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1259 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1260 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1261 | * configure it for smart-standby. No return value. | |
1262 | */ | |
74ff3a68 | 1263 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1264 | { |
43b40992 | 1265 | u8 idlemode, sf; |
63c85238 PW |
1266 | u32 v; |
1267 | ||
43b40992 | 1268 | if (!oh->class->sysc) |
63c85238 PW |
1269 | return; |
1270 | ||
1271 | v = oh->_sysc_cache; | |
43b40992 | 1272 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1273 | |
43b40992 | 1274 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
1275 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
1276 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
1277 | _set_slave_idlemode(oh, idlemode, &v); | |
1278 | } | |
1279 | ||
43b40992 | 1280 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1281 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1282 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1283 | } else { | |
1284 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1285 | _enable_wakeup(oh, &v); | |
1286 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1287 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1288 | else | |
1289 | idlemode = HWMOD_IDLEMODE_SMART; | |
1290 | } | |
63c85238 PW |
1291 | _set_master_standbymode(oh, idlemode, &v); |
1292 | } | |
1293 | ||
86009eb3 BC |
1294 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1295 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1296 | _enable_wakeup(oh, &v); | |
1297 | ||
63c85238 PW |
1298 | _write_sysconfig(v, oh); |
1299 | } | |
1300 | ||
1301 | /** | |
74ff3a68 | 1302 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1303 | * @oh: struct omap_hwmod * |
1304 | * | |
1305 | * Force the module into slave idle and master suspend. No return | |
1306 | * value. | |
1307 | */ | |
74ff3a68 | 1308 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1309 | { |
1310 | u32 v; | |
43b40992 | 1311 | u8 sf; |
63c85238 | 1312 | |
43b40992 | 1313 | if (!oh->class->sysc) |
63c85238 PW |
1314 | return; |
1315 | ||
1316 | v = oh->_sysc_cache; | |
43b40992 | 1317 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1318 | |
43b40992 | 1319 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1320 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1321 | ||
43b40992 | 1322 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1323 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1324 | ||
43b40992 | 1325 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1326 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1327 | |
1328 | _write_sysconfig(v, oh); | |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * _lookup - find an omap_hwmod by name | |
1333 | * @name: find an omap_hwmod by name | |
1334 | * | |
1335 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1336 | */ |
1337 | static struct omap_hwmod *_lookup(const char *name) | |
1338 | { | |
1339 | struct omap_hwmod *oh, *temp_oh; | |
1340 | ||
1341 | oh = NULL; | |
1342 | ||
1343 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1344 | if (!strcmp(name, temp_oh->name)) { | |
1345 | oh = temp_oh; | |
1346 | break; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | return oh; | |
1351 | } | |
868c157d | 1352 | |
6ae76997 BC |
1353 | /** |
1354 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1355 | * @oh: struct omap_hwmod * | |
1356 | * | |
1357 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1358 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1359 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1360 | */ |
1361 | static int _init_clkdm(struct omap_hwmod *oh) | |
1362 | { | |
868c157d | 1363 | if (!oh->clkdm_name) |
6ae76997 BC |
1364 | return 0; |
1365 | ||
6ae76997 BC |
1366 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1367 | if (!oh->clkdm) { | |
1368 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1369 | oh->name, oh->clkdm_name); | |
1370 | return -EINVAL; | |
1371 | } | |
1372 | ||
1373 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1374 | oh->name, oh->clkdm_name); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
63c85238 PW |
1378 | |
1379 | /** | |
6ae76997 BC |
1380 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1381 | * well the clockdomain. | |
63c85238 | 1382 | * @oh: struct omap_hwmod * |
97d60162 | 1383 | * @data: not used; pass NULL |
63c85238 | 1384 | * |
a2debdbd | 1385 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1386 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1387 | * success, or a negative error code on failure. | |
63c85238 | 1388 | */ |
97d60162 | 1389 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1390 | { |
1391 | int ret = 0; | |
1392 | ||
48d54f3f PW |
1393 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1394 | return 0; | |
63c85238 PW |
1395 | |
1396 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1397 | ||
1398 | ret |= _init_main_clk(oh); | |
1399 | ret |= _init_interface_clks(oh); | |
1400 | ret |= _init_opt_clks(oh); | |
0a179eaa KH |
1401 | if (soc_ops.init_clkdm) |
1402 | ret |= soc_ops.init_clkdm(oh); | |
63c85238 | 1403 | |
f5c1f84b BC |
1404 | if (!ret) |
1405 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1406 | else |
1407 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1408 | |
09c35f2f | 1409 | return ret; |
63c85238 PW |
1410 | } |
1411 | ||
5365efbe | 1412 | /** |
cc1226e7 | 1413 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1414 | * @oh: struct omap_hwmod * |
1415 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1416 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1417 | * |
1418 | * Return the bit position of the reset line that match the | |
1419 | * input name. Return -ENOENT if not found. | |
1420 | */ | |
cc1226e7 | 1421 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1422 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1423 | { |
1424 | int i; | |
1425 | ||
1426 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1427 | const char *rst_line = oh->rst_lines[i].name; | |
1428 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1429 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1430 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1431 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1432 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1433 | ohri->st_shift); | |
5365efbe | 1434 | |
cc1226e7 | 1435 | return 0; |
5365efbe BC |
1436 | } |
1437 | } | |
1438 | ||
1439 | return -ENOENT; | |
1440 | } | |
1441 | ||
1442 | /** | |
1443 | * _assert_hardreset - assert the HW reset line of submodules | |
1444 | * contained in the hwmod module. | |
1445 | * @oh: struct omap_hwmod * | |
1446 | * @name: name of the reset line to lookup and assert | |
1447 | * | |
b8249cf2 KH |
1448 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1449 | * reset line to be assert / deassert in order to enable fully the IP. | |
1450 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1451 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1452 | * along the return value from _lookup_hardreset() or the SoC's | |
1453 | * assert_hardreset code. | |
5365efbe BC |
1454 | */ |
1455 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1456 | { | |
cc1226e7 | 1457 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1458 | u8 ret = -EINVAL; |
5365efbe BC |
1459 | |
1460 | if (!oh) | |
1461 | return -EINVAL; | |
1462 | ||
b8249cf2 KH |
1463 | if (!soc_ops.assert_hardreset) |
1464 | return -ENOSYS; | |
1465 | ||
cc1226e7 | 1466 | ret = _lookup_hardreset(oh, name, &ohri); |
1467 | if (IS_ERR_VALUE(ret)) | |
1468 | return ret; | |
5365efbe | 1469 | |
b8249cf2 KH |
1470 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1471 | ||
1472 | return ret; | |
5365efbe BC |
1473 | } |
1474 | ||
1475 | /** | |
1476 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1477 | * in the hwmod module. | |
1478 | * @oh: struct omap_hwmod * | |
1479 | * @name: name of the reset line to look up and deassert | |
1480 | * | |
b8249cf2 KH |
1481 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1482 | * reset line to be assert / deassert in order to enable fully the IP. | |
1483 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1484 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1485 | * along the return value from _lookup_hardreset() or the SoC's | |
1486 | * deassert_hardreset code. | |
5365efbe BC |
1487 | */ |
1488 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1489 | { | |
cc1226e7 | 1490 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1491 | int ret = -EINVAL; |
5365efbe BC |
1492 | |
1493 | if (!oh) | |
1494 | return -EINVAL; | |
1495 | ||
b8249cf2 KH |
1496 | if (!soc_ops.deassert_hardreset) |
1497 | return -ENOSYS; | |
1498 | ||
cc1226e7 | 1499 | ret = _lookup_hardreset(oh, name, &ohri); |
1500 | if (IS_ERR_VALUE(ret)) | |
1501 | return ret; | |
5365efbe | 1502 | |
b8249cf2 | 1503 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
cc1226e7 | 1504 | if (ret == -EBUSY) |
5365efbe BC |
1505 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1506 | ||
cc1226e7 | 1507 | return ret; |
5365efbe BC |
1508 | } |
1509 | ||
1510 | /** | |
1511 | * _read_hardreset - read the HW reset line state of submodules | |
1512 | * contained in the hwmod module | |
1513 | * @oh: struct omap_hwmod * | |
1514 | * @name: name of the reset line to look up and read | |
1515 | * | |
b8249cf2 KH |
1516 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1517 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1518 | * status on the currently-booted SoC, or passes along the return | |
1519 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1520 | * code. | |
5365efbe BC |
1521 | */ |
1522 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1523 | { | |
cc1226e7 | 1524 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1525 | u8 ret = -EINVAL; |
5365efbe BC |
1526 | |
1527 | if (!oh) | |
1528 | return -EINVAL; | |
1529 | ||
b8249cf2 KH |
1530 | if (!soc_ops.is_hardreset_asserted) |
1531 | return -ENOSYS; | |
1532 | ||
cc1226e7 | 1533 | ret = _lookup_hardreset(oh, name, &ohri); |
1534 | if (IS_ERR_VALUE(ret)) | |
1535 | return ret; | |
5365efbe | 1536 | |
b8249cf2 | 1537 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1538 | } |
1539 | ||
747834ab PW |
1540 | /** |
1541 | * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset | |
1542 | * @oh: struct omap_hwmod * | |
1543 | * | |
1544 | * If any hardreset line associated with @oh is asserted, then return true. | |
1545 | * Otherwise, if @oh has no hardreset lines associated with it, or if | |
1546 | * no hardreset lines associated with @oh are asserted, then return false. | |
1547 | * This function is used to avoid executing some parts of the IP block | |
1548 | * enable/disable sequence if a hardreset line is set. | |
1549 | */ | |
1550 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1551 | { | |
1552 | int i; | |
1553 | ||
1554 | if (oh->rst_lines_cnt == 0) | |
1555 | return false; | |
1556 | ||
1557 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1558 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1559 | return true; | |
1560 | ||
1561 | return false; | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1566 | * @oh: struct omap_hwmod * | |
1567 | * | |
1568 | * Disable the PRCM module mode related to the hwmod @oh. | |
1569 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1570 | */ | |
1571 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1572 | { | |
1573 | int v; | |
1574 | ||
747834ab PW |
1575 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1576 | return -EINVAL; | |
1577 | ||
1578 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1579 | ||
1580 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1581 | oh->clkdm->cm_inst, | |
1582 | oh->clkdm->clkdm_offs, | |
1583 | oh->prcm.omap4.clkctrl_offs); | |
1584 | ||
1585 | if (_are_any_hardreset_lines_asserted(oh)) | |
1586 | return 0; | |
1587 | ||
1588 | v = _omap4_wait_target_disable(oh); | |
1589 | if (v) | |
1590 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1591 | oh->name); | |
1592 | ||
1593 | return 0; | |
1594 | } | |
1595 | ||
63c85238 | 1596 | /** |
bd36179e | 1597 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1598 | * @oh: struct omap_hwmod * |
1599 | * | |
1600 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1601 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1602 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1603 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1604 | * |
1605 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1606 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1607 | * use the SYSCONFIG softreset bit to provide the status. |
1608 | * | |
bd36179e PW |
1609 | * Note that some IP like McBSP do have reset control but don't have |
1610 | * reset status. | |
63c85238 | 1611 | */ |
bd36179e | 1612 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1613 | { |
387ca5bf | 1614 | u32 v, softrst_mask; |
6f8b7ff5 | 1615 | int c = 0; |
96835af9 | 1616 | int ret = 0; |
63c85238 | 1617 | |
43b40992 | 1618 | if (!oh->class->sysc || |
2cb06814 | 1619 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1620 | return -ENOENT; |
63c85238 PW |
1621 | |
1622 | /* clocks must be on for this operation */ | |
1623 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1624 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1625 | "enabled state\n", oh->name); | |
63c85238 PW |
1626 | return -EINVAL; |
1627 | } | |
1628 | ||
96835af9 BC |
1629 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1630 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1631 | _enable_optional_clocks(oh); | |
1632 | ||
bd36179e | 1633 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1634 | |
1635 | v = oh->_sysc_cache; | |
96835af9 BC |
1636 | ret = _set_softreset(oh, &v); |
1637 | if (ret) | |
1638 | goto dis_opt_clks; | |
63c85238 PW |
1639 | _write_sysconfig(v, oh); |
1640 | ||
d99de7f5 FGL |
1641 | if (oh->class->sysc->srst_udelay) |
1642 | udelay(oh->class->sysc->srst_udelay); | |
1643 | ||
2cb06814 | 1644 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1645 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1646 | oh->class->sysc->syss_offs) |
1647 | & SYSS_RESETDONE_MASK), | |
1648 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1649 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1650 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1651 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1652 | oh->class->sysc->sysc_offs) |
387ca5bf | 1653 | & softrst_mask), |
2cb06814 | 1654 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1655 | } |
63c85238 | 1656 | |
5365efbe | 1657 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1658 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1659 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1660 | else |
5365efbe | 1661 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1662 | |
1663 | /* | |
1664 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1665 | * _wait_target_ready() or _reset() | |
1666 | */ | |
1667 | ||
96835af9 BC |
1668 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1669 | ||
1670 | dis_opt_clks: | |
1671 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1672 | _disable_optional_clocks(oh); | |
1673 | ||
1674 | return ret; | |
63c85238 PW |
1675 | } |
1676 | ||
bd36179e PW |
1677 | /** |
1678 | * _reset - reset an omap_hwmod | |
1679 | * @oh: struct omap_hwmod * | |
1680 | * | |
30e105c0 PW |
1681 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1682 | * function pointer defined, then call it to reset the IP block, and | |
1683 | * pass along its return value to the caller. Otherwise, if the IP | |
1684 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1685 | * associated with it, call a function to reset the IP block via that | |
1686 | * method, and pass along the return value to the caller. Finally, if | |
1687 | * the IP block has some hardreset lines associated with it, assert | |
1688 | * all of those, but do _not_ deassert them. (This is because driver | |
1689 | * authors have expressed an apparent requirement to control the | |
1690 | * deassertion of the hardreset lines themselves.) | |
1691 | * | |
1692 | * The default software reset mechanism for most OMAP IP blocks is | |
1693 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1694 | * hwmods cannot be reset via this method. Some are not targets and | |
1695 | * therefore have no OCP header registers to access. Others (like the | |
1696 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1697 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1698 | * omap_hwmod_class .reset function pointer. |
1699 | * | |
1700 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1701 | * does not prevent idling of the system. This is necessary for cases | |
1702 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1703 | * kernel without disabling dma. | |
1704 | * | |
1705 | * Passes along the return value from either _ocp_softreset() or the | |
1706 | * custom reset function - these must return -EINVAL if the hwmod | |
1707 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1708 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1709 | */ |
1710 | static int _reset(struct omap_hwmod *oh) | |
1711 | { | |
30e105c0 | 1712 | int i, r; |
bd36179e PW |
1713 | |
1714 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1715 | ||
30e105c0 PW |
1716 | if (oh->class->reset) { |
1717 | r = oh->class->reset(oh); | |
1718 | } else { | |
1719 | if (oh->rst_lines_cnt > 0) { | |
1720 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1721 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1722 | return 0; | |
1723 | } else { | |
1724 | r = _ocp_softreset(oh); | |
1725 | if (r == -ENOENT) | |
1726 | r = 0; | |
1727 | } | |
1728 | } | |
1729 | ||
6668546f KVA |
1730 | _set_dmadisable(oh); |
1731 | ||
9c8b0ec7 | 1732 | /* |
30e105c0 PW |
1733 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1734 | * softreset. The _enable() function should be split to avoid | |
1735 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1736 | */ |
2800852a RN |
1737 | if (oh->class->sysc) { |
1738 | _update_sysc_cache(oh); | |
1739 | _enable_sysc(oh); | |
1740 | } | |
1741 | ||
30e105c0 | 1742 | return r; |
bd36179e PW |
1743 | } |
1744 | ||
63c85238 | 1745 | /** |
dc6d1cda | 1746 | * _enable - enable an omap_hwmod |
63c85238 PW |
1747 | * @oh: struct omap_hwmod * |
1748 | * | |
1749 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1750 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1751 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1752 | */ |
dc6d1cda | 1753 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1754 | { |
747834ab | 1755 | int r; |
665d0013 | 1756 | int hwsup = 0; |
63c85238 | 1757 | |
34617e2a BC |
1758 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1759 | ||
aacf0941 | 1760 | /* |
64813c3f PW |
1761 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
1762 | * state at init. Now that someone is really trying to enable | |
1763 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
1764 | */ |
1765 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
1766 | /* | |
1767 | * If the caller has mux data populated, do the mux'ing | |
1768 | * which wouldn't have been done as part of the _enable() | |
1769 | * done during setup. | |
1770 | */ | |
1771 | if (oh->mux) | |
1772 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1773 | ||
1774 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
1775 | return 0; | |
1776 | } | |
1777 | ||
63c85238 PW |
1778 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1779 | oh->_state != _HWMOD_STATE_IDLE && | |
1780 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1781 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1782 | oh->name); | |
63c85238 PW |
1783 | return -EINVAL; |
1784 | } | |
1785 | ||
31f62866 | 1786 | /* |
747834ab PW |
1787 | * If an IP block contains HW reset lines and any of them are |
1788 | * asserted, we let integration code associated with that | |
1789 | * block handle the enable. We've received very little | |
1790 | * information on what those driver authors need, and until | |
1791 | * detailed information is provided and the driver code is | |
1792 | * posted to the public lists, this is probably the best we | |
1793 | * can do. | |
31f62866 | 1794 | */ |
747834ab PW |
1795 | if (_are_any_hardreset_lines_asserted(oh)) |
1796 | return 0; | |
63c85238 | 1797 | |
665d0013 RN |
1798 | /* Mux pins for device runtime if populated */ |
1799 | if (oh->mux && (!oh->mux->enabled || | |
1800 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
1801 | oh->mux->pads_dynamic))) | |
1802 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1803 | ||
1804 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 1805 | |
665d0013 RN |
1806 | if (oh->clkdm) { |
1807 | /* | |
1808 | * A clockdomain must be in SW_SUP before enabling | |
1809 | * completely the module. The clockdomain can be set | |
1810 | * in HW_AUTO only when the module become ready. | |
1811 | */ | |
1812 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1813 | r = clkdm_hwmod_enable(oh->clkdm, oh); | |
1814 | if (r) { | |
1815 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1816 | oh->name, oh->clkdm->name, r); | |
1817 | return r; | |
1818 | } | |
34617e2a | 1819 | } |
665d0013 RN |
1820 | |
1821 | _enable_clocks(oh); | |
9ebfd285 KH |
1822 | if (soc_ops.enable_module) |
1823 | soc_ops.enable_module(oh); | |
34617e2a | 1824 | |
8f6aa8ee KH |
1825 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
1826 | -EINVAL; | |
665d0013 RN |
1827 | if (!r) { |
1828 | /* | |
1829 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
1830 | * assuming that the previous state was HW_AUTO | |
1831 | */ | |
1832 | if (oh->clkdm && hwsup) | |
1833 | clkdm_allow_idle(oh->clkdm); | |
1834 | ||
1835 | oh->_state = _HWMOD_STATE_ENABLED; | |
1836 | ||
1837 | /* Access the sysconfig only if the target is ready */ | |
1838 | if (oh->class->sysc) { | |
1839 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1840 | _update_sysc_cache(oh); | |
1841 | _enable_sysc(oh); | |
1842 | } | |
1843 | } else { | |
1844 | _disable_clocks(oh); | |
1845 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1846 | oh->name, r); | |
34617e2a | 1847 | |
665d0013 RN |
1848 | if (oh->clkdm) |
1849 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1850 | } |
1851 | ||
63c85238 PW |
1852 | return r; |
1853 | } | |
1854 | ||
1855 | /** | |
dc6d1cda | 1856 | * _idle - idle an omap_hwmod |
63c85238 PW |
1857 | * @oh: struct omap_hwmod * |
1858 | * | |
1859 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1860 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1861 | * state or returns 0. | |
63c85238 | 1862 | */ |
dc6d1cda | 1863 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1864 | { |
34617e2a BC |
1865 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1866 | ||
63c85238 | 1867 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
1868 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
1869 | oh->name); | |
63c85238 PW |
1870 | return -EINVAL; |
1871 | } | |
1872 | ||
747834ab PW |
1873 | if (_are_any_hardreset_lines_asserted(oh)) |
1874 | return 0; | |
1875 | ||
43b40992 | 1876 | if (oh->class->sysc) |
74ff3a68 | 1877 | _idle_sysc(oh); |
63c85238 | 1878 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 1879 | |
9ebfd285 KH |
1880 | if (soc_ops.disable_module) |
1881 | soc_ops.disable_module(oh); | |
bfc141e3 | 1882 | |
45c38252 BC |
1883 | /* |
1884 | * The module must be in idle mode before disabling any parents | |
1885 | * clocks. Otherwise, the parent clock might be disabled before | |
1886 | * the module transition is done, and thus will prevent the | |
1887 | * transition to complete properly. | |
1888 | */ | |
1889 | _disable_clocks(oh); | |
665d0013 RN |
1890 | if (oh->clkdm) |
1891 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 1892 | |
8d9af88f | 1893 | /* Mux pins for device idle if populated */ |
029268e4 | 1894 | if (oh->mux && oh->mux->pads_dynamic) |
8d9af88f TL |
1895 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
1896 | ||
63c85238 PW |
1897 | oh->_state = _HWMOD_STATE_IDLE; |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
9599217a KVA |
1902 | /** |
1903 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
1904 | * @oh: struct omap_hwmod * | |
1905 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
1906 | * | |
1907 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
1908 | * local copy. Intended to be used by drivers that require | |
1909 | * direct manipulation of the AUTOIDLE bits. | |
1910 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
1911 | * along the return value from _set_module_autoidle(). | |
1912 | * | |
1913 | * Any users of this function should be scrutinized carefully. | |
1914 | */ | |
1915 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
1916 | { | |
1917 | u32 v; | |
1918 | int retval = 0; | |
1919 | unsigned long flags; | |
1920 | ||
1921 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
1922 | return -EINVAL; | |
1923 | ||
1924 | spin_lock_irqsave(&oh->_lock, flags); | |
1925 | ||
1926 | v = oh->_sysc_cache; | |
1927 | ||
1928 | retval = _set_module_autoidle(oh, autoidle, &v); | |
1929 | ||
1930 | if (!retval) | |
1931 | _write_sysconfig(v, oh); | |
1932 | ||
1933 | spin_unlock_irqrestore(&oh->_lock, flags); | |
1934 | ||
1935 | return retval; | |
1936 | } | |
1937 | ||
63c85238 PW |
1938 | /** |
1939 | * _shutdown - shutdown an omap_hwmod | |
1940 | * @oh: struct omap_hwmod * | |
1941 | * | |
1942 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1943 | * used for the hwmod is removed or unloaded or if the driver is not | |
1944 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1945 | * state or returns 0. | |
1946 | */ | |
1947 | static int _shutdown(struct omap_hwmod *oh) | |
1948 | { | |
9c8b0ec7 | 1949 | int ret, i; |
e4dc8f50 PW |
1950 | u8 prev_state; |
1951 | ||
63c85238 PW |
1952 | if (oh->_state != _HWMOD_STATE_IDLE && |
1953 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
1954 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
1955 | oh->name); | |
63c85238 PW |
1956 | return -EINVAL; |
1957 | } | |
1958 | ||
747834ab PW |
1959 | if (_are_any_hardreset_lines_asserted(oh)) |
1960 | return 0; | |
1961 | ||
63c85238 PW |
1962 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
1963 | ||
e4dc8f50 PW |
1964 | if (oh->class->pre_shutdown) { |
1965 | prev_state = oh->_state; | |
1966 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1967 | _enable(oh); |
e4dc8f50 PW |
1968 | ret = oh->class->pre_shutdown(oh); |
1969 | if (ret) { | |
1970 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1971 | _idle(oh); |
e4dc8f50 PW |
1972 | return ret; |
1973 | } | |
1974 | } | |
1975 | ||
6481c73c MV |
1976 | if (oh->class->sysc) { |
1977 | if (oh->_state == _HWMOD_STATE_IDLE) | |
1978 | _enable(oh); | |
74ff3a68 | 1979 | _shutdown_sysc(oh); |
6481c73c | 1980 | } |
5365efbe | 1981 | |
3827f949 BC |
1982 | /* clocks and deps are already disabled in idle */ |
1983 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1984 | _del_initiator_dep(oh, mpu_oh); | |
1985 | /* XXX what about the other system initiators here? dma, dsp */ | |
9ebfd285 KH |
1986 | if (soc_ops.disable_module) |
1987 | soc_ops.disable_module(oh); | |
45c38252 | 1988 | _disable_clocks(oh); |
665d0013 RN |
1989 | if (oh->clkdm) |
1990 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 1991 | } |
63c85238 PW |
1992 | /* XXX Should this code also force-disable the optional clocks? */ |
1993 | ||
9c8b0ec7 PW |
1994 | for (i = 0; i < oh->rst_lines_cnt; i++) |
1995 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 1996 | |
8d9af88f TL |
1997 | /* Mux pins to safe mode or use populated off mode values */ |
1998 | if (oh->mux) | |
1999 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2000 | |
2001 | oh->_state = _HWMOD_STATE_DISABLED; | |
2002 | ||
2003 | return 0; | |
2004 | } | |
2005 | ||
381d033a PW |
2006 | /** |
2007 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2008 | * @oh: struct omap_hwmod * to locate the virtual address | |
2009 | * | |
2010 | * Cache the virtual address used by the MPU to access this IP block's | |
2011 | * registers. This address is needed early so the OCP registers that | |
2012 | * are part of the device's address space can be ioremapped properly. | |
2013 | * No return value. | |
2014 | */ | |
2015 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
2016 | { | |
c9aafd23 PW |
2017 | struct omap_hwmod_addr_space *mem; |
2018 | void __iomem *va_start; | |
2019 | ||
2020 | if (!oh) | |
2021 | return; | |
2022 | ||
2221b5cd PW |
2023 | _save_mpu_port_index(oh); |
2024 | ||
381d033a PW |
2025 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2026 | return; | |
2027 | ||
c9aafd23 PW |
2028 | mem = _find_mpu_rt_addr_space(oh); |
2029 | if (!mem) { | |
2030 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2031 | oh->name); | |
2032 | return; | |
2033 | } | |
2034 | ||
2035 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
2036 | if (!va_start) { | |
2037 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2038 | return; | |
2039 | } | |
2040 | ||
2041 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2042 | oh->name, va_start); | |
2043 | ||
2044 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2045 | } |
2046 | ||
2047 | /** | |
2048 | * _init - initialize internal data for the hwmod @oh | |
2049 | * @oh: struct omap_hwmod * | |
2050 | * @n: (unused) | |
2051 | * | |
2052 | * Look up the clocks and the address space used by the MPU to access | |
2053 | * registers belonging to the hwmod @oh. @oh must already be | |
2054 | * registered at this point. This is the first of two phases for | |
2055 | * hwmod initialization. Code called here does not touch any hardware | |
2056 | * registers, it simply prepares internal data structures. Returns 0 | |
2057 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2058 | * failure. | |
2059 | */ | |
2060 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2061 | { | |
2062 | int r; | |
2063 | ||
2064 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2065 | return 0; | |
2066 | ||
2067 | _init_mpu_rt_base(oh, NULL); | |
2068 | ||
2069 | r = _init_clocks(oh, NULL); | |
2070 | if (IS_ERR_VALUE(r)) { | |
2071 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
63c85238 | 2080 | /** |
64813c3f | 2081 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2082 | * @oh: struct omap_hwmod * |
2083 | * | |
64813c3f PW |
2084 | * Set up the module's interface clocks. XXX This function is still mostly |
2085 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2086 | * the clock code. No return value. | |
63c85238 | 2087 | */ |
64813c3f | 2088 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2089 | { |
5d95dde7 | 2090 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2091 | struct list_head *p; |
5d95dde7 | 2092 | int i = 0; |
381d033a | 2093 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2094 | return; |
48d54f3f | 2095 | |
11cd4b94 | 2096 | p = oh->slave_ports.next; |
63c85238 | 2097 | |
5d95dde7 | 2098 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2099 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2100 | if (!os->_clk) |
64813c3f | 2101 | continue; |
63c85238 | 2102 | |
64813c3f PW |
2103 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2104 | /* XXX omap_iclk_deny_idle(c); */ | |
2105 | } else { | |
2106 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2107 | clk_enable(os->_clk); |
63c85238 PW |
2108 | } |
2109 | } | |
2110 | ||
64813c3f PW |
2111 | return; |
2112 | } | |
2113 | ||
2114 | /** | |
2115 | * _setup_reset - reset an IP block during the setup process | |
2116 | * @oh: struct omap_hwmod * | |
2117 | * | |
2118 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2119 | * process. The IP block is first enabled so it can be successfully | |
2120 | * reset. Returns 0 upon success or a negative error code upon | |
2121 | * failure. | |
2122 | */ | |
2123 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2124 | { | |
2125 | int r; | |
2126 | ||
2127 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2128 | return -EINVAL; | |
63c85238 | 2129 | |
747834ab PW |
2130 | if (oh->rst_lines_cnt == 0) { |
2131 | r = _enable(oh); | |
2132 | if (r) { | |
2133 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2134 | oh->name, oh->_state); | |
2135 | return -EINVAL; | |
2136 | } | |
9a23dfe1 | 2137 | } |
63c85238 | 2138 | |
2800852a | 2139 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2140 | r = _reset(oh); |
2141 | ||
2142 | return r; | |
2143 | } | |
2144 | ||
2145 | /** | |
2146 | * _setup_postsetup - transition to the appropriate state after _setup | |
2147 | * @oh: struct omap_hwmod * | |
2148 | * | |
2149 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2150 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2151 | * this function is called at the end of _setup().) The postsetup | |
2152 | * state for an IP block can be changed by calling | |
2153 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2154 | * before one of the omap_hwmod_setup*() functions are called for the | |
2155 | * IP block. | |
2156 | * | |
2157 | * The IP block stays in this state until a PM runtime-based driver is | |
2158 | * loaded for that IP block. A post-setup state of IDLE is | |
2159 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2160 | * drivers, since those drivers are able to enable the IP block. A | |
2161 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2162 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2163 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2164 | * included, since the WDTIMER starts running on reset and will reset | |
2165 | * the MPU if left active. | |
2166 | * | |
2167 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2168 | * drivers have been converted to use PM runtime, and all of the IP | |
2169 | * block data and interconnect data is available to the hwmod code, it | |
2170 | * should be possible to replace this mechanism with a "lazy reset" | |
2171 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2172 | * when the driver first probes, then all remaining IP blocks without | |
2173 | * drivers are either shut down or enabled after the drivers have | |
2174 | * loaded. However, this cannot take place until the above | |
2175 | * preconditions have been met, since otherwise the late reset code | |
2176 | * has no way of knowing which IP blocks are in use by drivers, and | |
2177 | * which ones are unused. | |
2178 | * | |
2179 | * No return value. | |
2180 | */ | |
2181 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2182 | { | |
2183 | u8 postsetup_state; | |
2184 | ||
2185 | if (oh->rst_lines_cnt > 0) | |
2186 | return; | |
76e5589e | 2187 | |
2092e5cc PW |
2188 | postsetup_state = oh->_postsetup_state; |
2189 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2190 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2191 | ||
2192 | /* | |
2193 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2194 | * it should be set by the core code as a runtime flag during startup | |
2195 | */ | |
2196 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2197 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2198 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2199 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2200 | } |
2092e5cc PW |
2201 | |
2202 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2203 | _idle(oh); |
2092e5cc PW |
2204 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2205 | _shutdown(oh); | |
2206 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2207 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2208 | oh->name, postsetup_state); | |
63c85238 | 2209 | |
64813c3f PW |
2210 | return; |
2211 | } | |
2212 | ||
2213 | /** | |
2214 | * _setup - prepare IP block hardware for use | |
2215 | * @oh: struct omap_hwmod * | |
2216 | * @n: (unused, pass NULL) | |
2217 | * | |
2218 | * Configure the IP block represented by @oh. This may include | |
2219 | * enabling the IP block, resetting it, and placing it into a | |
2220 | * post-setup state, depending on the type of IP block and applicable | |
2221 | * flags. IP blocks are reset to prevent any previous configuration | |
2222 | * by the bootloader or previous operating system from interfering | |
2223 | * with power management or other parts of the system. The reset can | |
2224 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2225 | * two phases for hwmod initialization. Code called here generally | |
2226 | * affects the IP block hardware, or system integration hardware | |
2227 | * associated with the IP block. Returns 0. | |
2228 | */ | |
2229 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2230 | { | |
2231 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2232 | return 0; | |
2233 | ||
2234 | _setup_iclk_autoidle(oh); | |
2235 | ||
2236 | if (!_setup_reset(oh)) | |
2237 | _setup_postsetup(oh); | |
2238 | ||
63c85238 PW |
2239 | return 0; |
2240 | } | |
2241 | ||
63c85238 | 2242 | /** |
0102b627 | 2243 | * _register - register a struct omap_hwmod |
63c85238 PW |
2244 | * @oh: struct omap_hwmod * |
2245 | * | |
43b40992 PW |
2246 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2247 | * already has been registered by the same name; -EINVAL if the | |
2248 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2249 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2250 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2251 | * success. | |
63c85238 PW |
2252 | * |
2253 | * XXX The data should be copied into bootmem, so the original data | |
2254 | * should be marked __initdata and freed after init. This would allow | |
2255 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2256 | * that the copy process would be relatively complex due to the large number | |
2257 | * of substructures. | |
2258 | */ | |
01592df9 | 2259 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2260 | { |
43b40992 PW |
2261 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2262 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2263 | return -EINVAL; |
2264 | ||
63c85238 PW |
2265 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2266 | ||
ce35b244 BC |
2267 | if (_lookup(oh->name)) |
2268 | return -EEXIST; | |
63c85238 | 2269 | |
63c85238 PW |
2270 | list_add_tail(&oh->node, &omap_hwmod_list); |
2271 | ||
2221b5cd PW |
2272 | INIT_LIST_HEAD(&oh->master_ports); |
2273 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2274 | spin_lock_init(&oh->_lock); |
2092e5cc | 2275 | |
63c85238 PW |
2276 | oh->_state = _HWMOD_STATE_REGISTERED; |
2277 | ||
569edd70 PW |
2278 | /* |
2279 | * XXX Rather than doing a strcmp(), this should test a flag | |
2280 | * set in the hwmod data, inserted by the autogenerator code. | |
2281 | */ | |
2282 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2283 | mpu_oh = oh; | |
63c85238 | 2284 | |
569edd70 | 2285 | return 0; |
63c85238 PW |
2286 | } |
2287 | ||
2221b5cd PW |
2288 | /** |
2289 | * _alloc_links - return allocated memory for hwmod links | |
2290 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2291 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2292 | * | |
2293 | * Return pointers to two struct omap_hwmod_link records, via the | |
2294 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2295 | * memory allocated as part of a large initial block, but if that has | |
2296 | * been exhausted, will allocate memory itself. Since ideally this | |
2297 | * second allocation path will never occur, the number of these | |
2298 | * 'supplemental' allocations will be logged when debugging is | |
2299 | * enabled. Returns 0. | |
2300 | */ | |
2301 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2302 | struct omap_hwmod_link **sl) | |
2303 | { | |
2304 | unsigned int sz; | |
2305 | ||
2306 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2307 | *ml = &linkspace[free_ls++]; | |
2308 | *sl = &linkspace[free_ls++]; | |
2309 | return 0; | |
2310 | } | |
2311 | ||
2312 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2313 | ||
2314 | *sl = NULL; | |
2315 | *ml = alloc_bootmem(sz); | |
2316 | ||
2317 | memset(*ml, 0, sz); | |
2318 | ||
2319 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2320 | ||
2321 | ls_supp++; | |
2322 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2323 | ls_supp * LINKS_PER_OCP_IF); | |
2324 | ||
2325 | return 0; | |
2326 | }; | |
2327 | ||
2328 | /** | |
2329 | * _add_link - add an interconnect between two IP blocks | |
2330 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2331 | * | |
2332 | * Add struct omap_hwmod_link records connecting the master IP block | |
2333 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2334 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2335 | * preemption or SMP has been enabled, thus avoiding the need for | |
2336 | * locking in this code. Changes to this assumption will require | |
2337 | * additional locking. Returns 0. | |
2338 | */ | |
2339 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2340 | { | |
2341 | struct omap_hwmod_link *ml, *sl; | |
2342 | ||
2343 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2344 | oi->slave->name); | |
2345 | ||
2346 | _alloc_links(&ml, &sl); | |
2347 | ||
2348 | ml->ocp_if = oi; | |
2349 | INIT_LIST_HEAD(&ml->node); | |
2350 | list_add(&ml->node, &oi->master->master_ports); | |
2351 | oi->master->masters_cnt++; | |
2352 | ||
2353 | sl->ocp_if = oi; | |
2354 | INIT_LIST_HEAD(&sl->node); | |
2355 | list_add(&sl->node, &oi->slave->slave_ports); | |
2356 | oi->slave->slaves_cnt++; | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
2361 | /** | |
2362 | * _register_link - register a struct omap_hwmod_ocp_if | |
2363 | * @oi: struct omap_hwmod_ocp_if * | |
2364 | * | |
2365 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2366 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2367 | * record pointed to by @oi is missing required fields; or 0 upon | |
2368 | * success. | |
2369 | * | |
2370 | * XXX The data should be copied into bootmem, so the original data | |
2371 | * should be marked __initdata and freed after init. This would allow | |
2372 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2373 | */ | |
2374 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2375 | { | |
2376 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2377 | return -EINVAL; | |
2378 | ||
2379 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2380 | return -EEXIST; | |
2381 | ||
2382 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2383 | oi->master->name, oi->slave->name); | |
2384 | ||
2385 | /* | |
2386 | * Register the connected hwmods, if they haven't been | |
2387 | * registered already | |
2388 | */ | |
2389 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2390 | _register(oi->master); | |
2391 | ||
2392 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2393 | _register(oi->slave); | |
2394 | ||
2395 | _add_link(oi); | |
2396 | ||
2397 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2398 | ||
2399 | return 0; | |
2400 | } | |
2401 | ||
2402 | /** | |
2403 | * _alloc_linkspace - allocate large block of hwmod links | |
2404 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2405 | * | |
2406 | * Allocate a large block of struct omap_hwmod_link records. This | |
2407 | * improves boot time significantly by avoiding the need to allocate | |
2408 | * individual records one by one. If the number of records to | |
2409 | * allocate in the block hasn't been manually specified, this function | |
2410 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2411 | * and use that to determine the allocation size. For SoC families | |
2412 | * that require multiple list registrations, such as OMAP3xxx, this | |
2413 | * estimation process isn't optimal, so manual estimation is advised | |
2414 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2415 | * or 0 upon success. | |
2416 | */ | |
2417 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2418 | { | |
2419 | unsigned int i = 0; | |
2420 | unsigned int sz; | |
2421 | ||
2422 | if (linkspace) { | |
2423 | WARN(1, "linkspace already allocated\n"); | |
2424 | return -EEXIST; | |
2425 | } | |
2426 | ||
2427 | if (max_ls == 0) | |
2428 | while (ois[i++]) | |
2429 | max_ls += LINKS_PER_OCP_IF; | |
2430 | ||
2431 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2432 | ||
2433 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2434 | __func__, sz, max_ls); | |
2435 | ||
2436 | linkspace = alloc_bootmem(sz); | |
2437 | ||
2438 | memset(linkspace, 0, sz); | |
2439 | ||
2440 | return 0; | |
2441 | } | |
0102b627 | 2442 | |
8f6aa8ee KH |
2443 | /* Static functions intended only for use in soc_ops field function pointers */ |
2444 | ||
2445 | /** | |
2446 | * _omap2_wait_target_ready - wait for a module to leave slave idle | |
2447 | * @oh: struct omap_hwmod * | |
2448 | * | |
2449 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2450 | * does not have an IDLEST bit or if the module successfully leaves | |
2451 | * slave idle; otherwise, pass along the return value of the | |
2452 | * appropriate *_cm*_wait_module_ready() function. | |
2453 | */ | |
2454 | static int _omap2_wait_target_ready(struct omap_hwmod *oh) | |
2455 | { | |
2456 | if (!oh) | |
2457 | return -EINVAL; | |
2458 | ||
2459 | if (oh->flags & HWMOD_NO_IDLEST) | |
2460 | return 0; | |
2461 | ||
2462 | if (!_find_mpu_rt_port(oh)) | |
2463 | return 0; | |
2464 | ||
2465 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2466 | ||
2467 | return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2468 | oh->prcm.omap2.idlest_reg_id, | |
2469 | oh->prcm.omap2.idlest_idle_bit); | |
2470 | } | |
2471 | ||
2472 | /** | |
2473 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2474 | * @oh: struct omap_hwmod * | |
2475 | * | |
2476 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2477 | * does not have an IDLEST bit or if the module successfully leaves | |
2478 | * slave idle; otherwise, pass along the return value of the | |
2479 | * appropriate *_cm*_wait_module_ready() function. | |
2480 | */ | |
2481 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2482 | { | |
2483 | if (!oh || !oh->clkdm) | |
2484 | return -EINVAL; | |
2485 | ||
2486 | if (oh->flags & HWMOD_NO_IDLEST) | |
2487 | return 0; | |
2488 | ||
2489 | if (!_find_mpu_rt_port(oh)) | |
2490 | return 0; | |
2491 | ||
2492 | /* XXX check module SIDLEMODE, hardreset status */ | |
2493 | ||
2494 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
2495 | oh->clkdm->cm_inst, | |
2496 | oh->clkdm->clkdm_offs, | |
2497 | oh->prcm.omap4.clkctrl_offs); | |
2498 | } | |
2499 | ||
b8249cf2 KH |
2500 | /** |
2501 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2502 | * @oh: struct omap_hwmod * to assert hardreset | |
2503 | * @ohri: hardreset line data | |
2504 | * | |
2505 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2506 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2507 | * use as an soc_ops function pointer. Passes along the return value | |
2508 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2509 | * for removal when the PRM code is moved into drivers/. | |
2510 | */ | |
2511 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2512 | struct omap_hwmod_rst_info *ohri) | |
2513 | { | |
2514 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
2515 | ohri->rst_shift); | |
2516 | } | |
2517 | ||
2518 | /** | |
2519 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2520 | * @oh: struct omap_hwmod * to deassert hardreset | |
2521 | * @ohri: hardreset line data | |
2522 | * | |
2523 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2524 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2525 | * use as an soc_ops function pointer. Passes along the return value | |
2526 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2527 | * scheduled for removal when the PRM code is moved into drivers/. | |
2528 | */ | |
2529 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2530 | struct omap_hwmod_rst_info *ohri) | |
2531 | { | |
2532 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
2533 | ohri->rst_shift, | |
2534 | ohri->st_shift); | |
2535 | } | |
2536 | ||
2537 | /** | |
2538 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2539 | * @oh: struct omap_hwmod * to test hardreset | |
2540 | * @ohri: hardreset line data | |
2541 | * | |
2542 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2543 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2544 | * intended for use as an soc_ops function pointer. Passes along the | |
2545 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2546 | * function is scheduled for removal when the PRM code is moved into | |
2547 | * drivers/. | |
2548 | */ | |
2549 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2550 | struct omap_hwmod_rst_info *ohri) | |
2551 | { | |
2552 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
2553 | ohri->st_shift); | |
2554 | } | |
2555 | ||
2556 | /** | |
2557 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2558 | * @oh: struct omap_hwmod * to assert hardreset | |
2559 | * @ohri: hardreset line data | |
2560 | * | |
2561 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2562 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2563 | * intended for use as an soc_ops function pointer. Passes along the | |
2564 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2565 | * function is scheduled for removal when the PRM code is moved into | |
2566 | * drivers/. | |
2567 | */ | |
2568 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2569 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2570 | { |
07b3a139 PW |
2571 | if (!oh->clkdm) |
2572 | return -EINVAL; | |
2573 | ||
b8249cf2 KH |
2574 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
2575 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2576 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2577 | oh->prcm.omap4.rstctrl_offs); | |
2578 | } | |
2579 | ||
2580 | /** | |
2581 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2582 | * @oh: struct omap_hwmod * to deassert hardreset | |
2583 | * @ohri: hardreset line data | |
2584 | * | |
2585 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2586 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2587 | * intended for use as an soc_ops function pointer. Passes along the | |
2588 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2589 | * function is scheduled for removal when the PRM code is moved into | |
2590 | * drivers/. | |
2591 | */ | |
2592 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2593 | struct omap_hwmod_rst_info *ohri) | |
2594 | { | |
07b3a139 PW |
2595 | if (!oh->clkdm) |
2596 | return -EINVAL; | |
2597 | ||
b8249cf2 KH |
2598 | if (ohri->st_shift) |
2599 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2600 | oh->name, ohri->name); | |
2601 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
2602 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2603 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2604 | oh->prcm.omap4.rstctrl_offs); | |
2605 | } | |
2606 | ||
2607 | /** | |
2608 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2609 | * @oh: struct omap_hwmod * to test hardreset | |
2610 | * @ohri: hardreset line data | |
2611 | * | |
2612 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2613 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2614 | * Only intended for use as an soc_ops function pointer. Passes along | |
2615 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2616 | * This function is scheduled for removal when the PRM code is moved | |
2617 | * into drivers/. | |
2618 | */ | |
2619 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2620 | struct omap_hwmod_rst_info *ohri) | |
2621 | { | |
07b3a139 PW |
2622 | if (!oh->clkdm) |
2623 | return -EINVAL; | |
2624 | ||
b8249cf2 KH |
2625 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
2626 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2627 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2628 | oh->prcm.omap4.rstctrl_offs); | |
2629 | } | |
2630 | ||
0102b627 BC |
2631 | /* Public functions */ |
2632 | ||
2633 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2634 | { | |
2635 | if (oh->flags & HWMOD_16BIT_REG) | |
2636 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
2637 | else | |
2638 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
2639 | } | |
2640 | ||
2641 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2642 | { | |
2643 | if (oh->flags & HWMOD_16BIT_REG) | |
2644 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
2645 | else | |
2646 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
2647 | } | |
2648 | ||
6d3c55fd A |
2649 | /** |
2650 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2651 | * @oh: struct omap_hwmod * | |
2652 | * | |
2653 | * This is a public function exposed to drivers. Some drivers may need to do | |
2654 | * some settings before and after resetting the device. Those drivers after | |
2655 | * doing the necessary settings could use this function to start a reset by | |
2656 | * setting the SYSCONFIG.SOFTRESET bit. | |
2657 | */ | |
2658 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
2659 | { | |
3c55c1ba PW |
2660 | u32 v; |
2661 | int ret; | |
2662 | ||
2663 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
2664 | return -EINVAL; |
2665 | ||
3c55c1ba PW |
2666 | v = oh->_sysc_cache; |
2667 | ret = _set_softreset(oh, &v); | |
2668 | if (ret) | |
2669 | goto error; | |
2670 | _write_sysconfig(v, oh); | |
2671 | ||
2672 | error: | |
2673 | return ret; | |
6d3c55fd A |
2674 | } |
2675 | ||
0102b627 BC |
2676 | /** |
2677 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
2678 | * @oh: struct omap_hwmod * | |
2679 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
2680 | * | |
2681 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
2682 | * local copy. Intended to be used by drivers that have some erratum | |
2683 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
2684 | * -EINVAL if @oh is null, or passes along the return value from | |
2685 | * _set_slave_idlemode(). | |
2686 | * | |
2687 | * XXX Does this function have any current users? If not, we should | |
2688 | * remove it; it is better to let the rest of the hwmod code handle this. | |
2689 | * Any users of this function should be scrutinized carefully. | |
2690 | */ | |
2691 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
2692 | { | |
2693 | u32 v; | |
2694 | int retval = 0; | |
2695 | ||
2696 | if (!oh) | |
2697 | return -EINVAL; | |
2698 | ||
2699 | v = oh->_sysc_cache; | |
2700 | ||
2701 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
2702 | if (!retval) | |
2703 | _write_sysconfig(v, oh); | |
2704 | ||
2705 | return retval; | |
2706 | } | |
2707 | ||
63c85238 PW |
2708 | /** |
2709 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
2710 | * @name: name of the omap_hwmod to look up | |
2711 | * | |
2712 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
2713 | * struct omap_hwmod *, or NULL upon error. | |
2714 | */ | |
2715 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
2716 | { | |
2717 | struct omap_hwmod *oh; | |
2718 | ||
2719 | if (!name) | |
2720 | return NULL; | |
2721 | ||
63c85238 | 2722 | oh = _lookup(name); |
63c85238 PW |
2723 | |
2724 | return oh; | |
2725 | } | |
2726 | ||
2727 | /** | |
2728 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
2729 | * @fn: pointer to a callback function | |
97d60162 | 2730 | * @data: void * data to pass to callback function |
63c85238 PW |
2731 | * |
2732 | * Call @fn for each registered omap_hwmod, passing @data to each | |
2733 | * function. @fn must return 0 for success or any other value for | |
2734 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
2735 | * will stop and the non-zero return value will be passed to the | |
2736 | * caller of omap_hwmod_for_each(). @fn is called with | |
2737 | * omap_hwmod_for_each() held. | |
2738 | */ | |
97d60162 PW |
2739 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
2740 | void *data) | |
63c85238 PW |
2741 | { |
2742 | struct omap_hwmod *temp_oh; | |
30ebad9d | 2743 | int ret = 0; |
63c85238 PW |
2744 | |
2745 | if (!fn) | |
2746 | return -EINVAL; | |
2747 | ||
63c85238 | 2748 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 2749 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
2750 | if (ret) |
2751 | break; | |
2752 | } | |
63c85238 PW |
2753 | |
2754 | return ret; | |
2755 | } | |
2756 | ||
2221b5cd PW |
2757 | /** |
2758 | * omap_hwmod_register_links - register an array of hwmod links | |
2759 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
2760 | * | |
2761 | * Intended to be called early in boot before the clock framework is | |
2762 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
2763 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
2764 | * omap_hwmod_init() hasn't been called before calling this function, | |
2765 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
2766 | * success. | |
2221b5cd PW |
2767 | */ |
2768 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
2769 | { | |
2770 | int r, i; | |
2771 | ||
9ebfd285 KH |
2772 | if (!inited) |
2773 | return -EINVAL; | |
2774 | ||
2221b5cd PW |
2775 | if (!ois) |
2776 | return 0; | |
2777 | ||
2221b5cd PW |
2778 | if (!linkspace) { |
2779 | if (_alloc_linkspace(ois)) { | |
2780 | pr_err("omap_hwmod: could not allocate link space\n"); | |
2781 | return -ENOMEM; | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | i = 0; | |
2786 | do { | |
2787 | r = _register_link(ois[i]); | |
2788 | WARN(r && r != -EEXIST, | |
2789 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
2790 | ois[i]->master->name, ois[i]->slave->name, r); | |
2791 | } while (ois[++i]); | |
2792 | ||
2793 | return 0; | |
2794 | } | |
2795 | ||
381d033a PW |
2796 | /** |
2797 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
2798 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
2799 | * | |
2800 | * If the hwmod data corresponding to the MPU subsystem IP block | |
2801 | * hasn't been initialized and set up yet, do so now. This must be | |
2802 | * done first since sleep dependencies may be added from other hwmods | |
2803 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
2804 | * return value. | |
63c85238 | 2805 | */ |
381d033a | 2806 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 2807 | { |
381d033a PW |
2808 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
2809 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
2810 | __func__, MPU_INITIATOR_NAME); | |
2811 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
2812 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
2813 | } |
2814 | ||
63c85238 | 2815 | /** |
a2debdbd PW |
2816 | * omap_hwmod_setup_one - set up a single hwmod |
2817 | * @oh_name: const char * name of the already-registered hwmod to set up | |
2818 | * | |
381d033a PW |
2819 | * Initialize and set up a single hwmod. Intended to be used for a |
2820 | * small number of early devices, such as the timer IP blocks used for | |
2821 | * the scheduler clock. Must be called after omap2_clk_init(). | |
2822 | * Resolves the struct clk names to struct clk pointers for each | |
2823 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
2824 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
2825 | */ |
2826 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
2827 | { |
2828 | struct omap_hwmod *oh; | |
63c85238 | 2829 | |
a2debdbd PW |
2830 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
2831 | ||
a2debdbd PW |
2832 | oh = _lookup(oh_name); |
2833 | if (!oh) { | |
2834 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
2835 | return -EINVAL; | |
2836 | } | |
63c85238 | 2837 | |
381d033a | 2838 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 2839 | |
381d033a | 2840 | _init(oh, NULL); |
a2debdbd PW |
2841 | _setup(oh, NULL); |
2842 | ||
63c85238 PW |
2843 | return 0; |
2844 | } | |
2845 | ||
2846 | /** | |
381d033a | 2847 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 2848 | * |
381d033a PW |
2849 | * Initialize and set up all IP blocks registered with the hwmod code. |
2850 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
2851 | * names to struct clk pointers for each registered omap_hwmod. Also | |
2852 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 2853 | */ |
550c8092 | 2854 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 2855 | { |
381d033a | 2856 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 2857 | |
381d033a | 2858 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 2859 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
2860 | |
2861 | return 0; | |
2862 | } | |
550c8092 | 2863 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 2864 | |
63c85238 PW |
2865 | /** |
2866 | * omap_hwmod_enable - enable an omap_hwmod | |
2867 | * @oh: struct omap_hwmod * | |
2868 | * | |
74ff3a68 | 2869 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
2870 | * Returns -EINVAL on error or passes along the return value from _enable(). |
2871 | */ | |
2872 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
2873 | { | |
2874 | int r; | |
dc6d1cda | 2875 | unsigned long flags; |
63c85238 PW |
2876 | |
2877 | if (!oh) | |
2878 | return -EINVAL; | |
2879 | ||
dc6d1cda PW |
2880 | spin_lock_irqsave(&oh->_lock, flags); |
2881 | r = _enable(oh); | |
2882 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2883 | |
2884 | return r; | |
2885 | } | |
2886 | ||
2887 | /** | |
2888 | * omap_hwmod_idle - idle an omap_hwmod | |
2889 | * @oh: struct omap_hwmod * | |
2890 | * | |
74ff3a68 | 2891 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
2892 | * Returns -EINVAL on error or passes along the return value from _idle(). |
2893 | */ | |
2894 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
2895 | { | |
dc6d1cda PW |
2896 | unsigned long flags; |
2897 | ||
63c85238 PW |
2898 | if (!oh) |
2899 | return -EINVAL; | |
2900 | ||
dc6d1cda PW |
2901 | spin_lock_irqsave(&oh->_lock, flags); |
2902 | _idle(oh); | |
2903 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2904 | |
2905 | return 0; | |
2906 | } | |
2907 | ||
2908 | /** | |
2909 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
2910 | * @oh: struct omap_hwmod * | |
2911 | * | |
74ff3a68 | 2912 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
2913 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
2914 | * the return value from _shutdown(). | |
2915 | */ | |
2916 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
2917 | { | |
dc6d1cda PW |
2918 | unsigned long flags; |
2919 | ||
63c85238 PW |
2920 | if (!oh) |
2921 | return -EINVAL; | |
2922 | ||
dc6d1cda | 2923 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2924 | _shutdown(oh); |
dc6d1cda | 2925 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2926 | |
2927 | return 0; | |
2928 | } | |
2929 | ||
2930 | /** | |
2931 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
2932 | * @oh: struct omap_hwmod *oh | |
2933 | * | |
2934 | * Intended to be called by the omap_device code. | |
2935 | */ | |
2936 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
2937 | { | |
dc6d1cda PW |
2938 | unsigned long flags; |
2939 | ||
2940 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2941 | _enable_clocks(oh); |
dc6d1cda | 2942 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2943 | |
2944 | return 0; | |
2945 | } | |
2946 | ||
2947 | /** | |
2948 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
2949 | * @oh: struct omap_hwmod *oh | |
2950 | * | |
2951 | * Intended to be called by the omap_device code. | |
2952 | */ | |
2953 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
2954 | { | |
dc6d1cda PW |
2955 | unsigned long flags; |
2956 | ||
2957 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2958 | _disable_clocks(oh); |
dc6d1cda | 2959 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2960 | |
2961 | return 0; | |
2962 | } | |
2963 | ||
2964 | /** | |
2965 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
2966 | * @oh: struct omap_hwmod *oh | |
2967 | * | |
2968 | * Intended to be called by drivers and core code when all posted | |
2969 | * writes to a device must complete before continuing further | |
2970 | * execution (for example, after clearing some device IRQSTATUS | |
2971 | * register bits) | |
2972 | * | |
2973 | * XXX what about targets with multiple OCP threads? | |
2974 | */ | |
2975 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
2976 | { | |
2977 | BUG_ON(!oh); | |
2978 | ||
43b40992 | 2979 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
2980 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
2981 | oh->name); | |
63c85238 PW |
2982 | return; |
2983 | } | |
2984 | ||
2985 | /* | |
2986 | * Forces posted writes to complete on the OCP thread handling | |
2987 | * register writes | |
2988 | */ | |
cc7a1d2a | 2989 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
2990 | } |
2991 | ||
2992 | /** | |
2993 | * omap_hwmod_reset - reset the hwmod | |
2994 | * @oh: struct omap_hwmod * | |
2995 | * | |
2996 | * Under some conditions, a driver may wish to reset the entire device. | |
2997 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 2998 | * the return value from _reset(). |
63c85238 PW |
2999 | */ |
3000 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3001 | { | |
3002 | int r; | |
dc6d1cda | 3003 | unsigned long flags; |
63c85238 | 3004 | |
9b579114 | 3005 | if (!oh) |
63c85238 PW |
3006 | return -EINVAL; |
3007 | ||
dc6d1cda | 3008 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3009 | r = _reset(oh); |
dc6d1cda | 3010 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3011 | |
3012 | return r; | |
3013 | } | |
3014 | ||
5e8370f1 PW |
3015 | /* |
3016 | * IP block data retrieval functions | |
3017 | */ | |
3018 | ||
63c85238 PW |
3019 | /** |
3020 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3021 | * @oh: struct omap_hwmod * | |
3022 | * @res: pointer to the first element of an array of struct resource to fill | |
3023 | * | |
3024 | * Count the number of struct resource array elements necessary to | |
3025 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3026 | * that registers omap_devices. Intended to be used to determine the | |
3027 | * size of a dynamically-allocated struct resource array, before | |
3028 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3029 | * resource array elements needed. | |
3030 | * | |
3031 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3032 | * resource IDs. | |
3033 | * | |
3034 | */ | |
3035 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
3036 | { | |
5d95dde7 | 3037 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3038 | struct list_head *p; |
5d95dde7 PW |
3039 | int ret; |
3040 | int i = 0; | |
63c85238 | 3041 | |
bc614958 | 3042 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 3043 | |
11cd4b94 | 3044 | p = oh->slave_ports.next; |
2221b5cd | 3045 | |
5d95dde7 | 3046 | while (i < oh->slaves_cnt) { |
11cd4b94 | 3047 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 PW |
3048 | ret += _count_ocp_if_addr_spaces(os); |
3049 | } | |
63c85238 PW |
3050 | |
3051 | return ret; | |
3052 | } | |
3053 | ||
3054 | /** | |
3055 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3056 | * @oh: struct omap_hwmod * | |
3057 | * @res: pointer to the first element of an array of struct resource to fill | |
3058 | * | |
3059 | * Fill the struct resource array @res with resource data from the | |
3060 | * omap_hwmod @oh. Intended to be called by code that registers | |
3061 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3062 | * number of array elements filled. | |
3063 | */ | |
3064 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3065 | { | |
5d95dde7 | 3066 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3067 | struct list_head *p; |
5d95dde7 | 3068 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3069 | int r = 0; |
3070 | ||
3071 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3072 | ||
212738a4 PW |
3073 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3074 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3075 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3076 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3077 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3078 | (res + r)->flags = IORESOURCE_IRQ; |
3079 | r++; | |
3080 | } | |
3081 | ||
bc614958 PW |
3082 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3083 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3084 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3085 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3086 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3087 | (res + r)->flags = IORESOURCE_DMA; |
3088 | r++; | |
3089 | } | |
3090 | ||
11cd4b94 | 3091 | p = oh->slave_ports.next; |
2221b5cd | 3092 | |
5d95dde7 PW |
3093 | i = 0; |
3094 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3095 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3096 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3097 | |
78183f3f | 3098 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3099 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3100 | (res + r)->start = (os->addr + j)->pa_start; |
3101 | (res + r)->end = (os->addr + j)->pa_end; | |
3102 | (res + r)->flags = IORESOURCE_MEM; | |
3103 | r++; | |
3104 | } | |
3105 | } | |
3106 | ||
3107 | return r; | |
3108 | } | |
3109 | ||
5e8370f1 PW |
3110 | /** |
3111 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3112 | * @oh: struct omap_hwmod * to operate on | |
3113 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3114 | * @name: pointer to the name of the data to fetch (optional) | |
3115 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3116 | * | |
3117 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3118 | * data for the IP block pointed to by @oh. The data will be filled | |
3119 | * into a struct resource record pointed to by @rsrc. The struct | |
3120 | * resource must be allocated by the caller. When @name is non-null, | |
3121 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3122 | * space hwmod data arrays will be returned. If @name is null, the | |
3123 | * first array entry will be returned. Data order is not meaningful | |
3124 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3125 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3126 | * data is later added that causes data ordering to change. This | |
3127 | * function is only intended for use by OMAP core code. Device | |
3128 | * drivers should not call this function - the appropriate bus-related | |
3129 | * data accessor functions should be used instead. Returns 0 upon | |
3130 | * success or a negative error code upon error. | |
3131 | */ | |
3132 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3133 | const char *name, struct resource *rsrc) | |
3134 | { | |
3135 | int r; | |
3136 | unsigned int irq, dma; | |
3137 | u32 pa_start, pa_end; | |
3138 | ||
3139 | if (!oh || !rsrc) | |
3140 | return -EINVAL; | |
3141 | ||
3142 | if (type == IORESOURCE_IRQ) { | |
3143 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3144 | if (r) | |
3145 | return r; | |
3146 | ||
3147 | rsrc->start = irq; | |
3148 | rsrc->end = irq; | |
3149 | } else if (type == IORESOURCE_DMA) { | |
3150 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3151 | if (r) | |
3152 | return r; | |
3153 | ||
3154 | rsrc->start = dma; | |
3155 | rsrc->end = dma; | |
3156 | } else if (type == IORESOURCE_MEM) { | |
3157 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3158 | if (r) | |
3159 | return r; | |
3160 | ||
3161 | rsrc->start = pa_start; | |
3162 | rsrc->end = pa_end; | |
3163 | } else { | |
3164 | return -EINVAL; | |
3165 | } | |
3166 | ||
3167 | rsrc->flags = type; | |
3168 | rsrc->name = name; | |
3169 | ||
3170 | return 0; | |
3171 | } | |
3172 | ||
63c85238 PW |
3173 | /** |
3174 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3175 | * @oh: struct omap_hwmod * | |
3176 | * | |
3177 | * Return the powerdomain pointer associated with the OMAP module | |
3178 | * @oh's main clock. If @oh does not have a main clk, return the | |
3179 | * powerdomain associated with the interface clock associated with the | |
3180 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3181 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3182 | * success. | |
3183 | */ | |
3184 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3185 | { | |
3186 | struct clk *c; | |
2d6141ba | 3187 | struct omap_hwmod_ocp_if *oi; |
63c85238 PW |
3188 | |
3189 | if (!oh) | |
3190 | return NULL; | |
3191 | ||
3192 | if (oh->_clk) { | |
3193 | c = oh->_clk; | |
3194 | } else { | |
2d6141ba PW |
3195 | oi = _find_mpu_rt_port(oh); |
3196 | if (!oi) | |
63c85238 | 3197 | return NULL; |
2d6141ba | 3198 | c = oi->_clk; |
63c85238 PW |
3199 | } |
3200 | ||
d5647c18 TG |
3201 | if (!c->clkdm) |
3202 | return NULL; | |
3203 | ||
63c85238 PW |
3204 | return c->clkdm->pwrdm.ptr; |
3205 | ||
3206 | } | |
3207 | ||
db2a60bf PW |
3208 | /** |
3209 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3210 | * @oh: struct omap_hwmod * | |
3211 | * | |
3212 | * Returns the virtual address corresponding to the beginning of the | |
3213 | * module's register target, in the address range that is intended to | |
3214 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3215 | * upon error. | |
3216 | */ | |
3217 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3218 | { | |
3219 | if (!oh) | |
3220 | return NULL; | |
3221 | ||
3222 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3223 | return NULL; | |
3224 | ||
3225 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3226 | return NULL; | |
3227 | ||
3228 | return oh->_mpu_rt_va; | |
3229 | } | |
3230 | ||
63c85238 PW |
3231 | /** |
3232 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3233 | * @oh: struct omap_hwmod * | |
3234 | * @init_oh: struct omap_hwmod * (initiator) | |
3235 | * | |
3236 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3237 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3238 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3239 | * code needs to add/del initiator dependencies dynamically | |
3240 | * before/after accessing a device. Returns the return value from | |
3241 | * _add_initiator_dep(). | |
3242 | * | |
3243 | * XXX Keep a usecount in the clockdomain code | |
3244 | */ | |
3245 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3246 | struct omap_hwmod *init_oh) | |
3247 | { | |
3248 | return _add_initiator_dep(oh, init_oh); | |
3249 | } | |
3250 | ||
3251 | /* | |
3252 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3253 | * for context save/restore operations? | |
3254 | */ | |
3255 | ||
3256 | /** | |
3257 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3258 | * @oh: struct omap_hwmod * | |
3259 | * @init_oh: struct omap_hwmod * (initiator) | |
3260 | * | |
3261 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3262 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3263 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3264 | * code needs to add/del initiator dependencies dynamically | |
3265 | * before/after accessing a device. Returns the return value from | |
3266 | * _del_initiator_dep(). | |
3267 | * | |
3268 | * XXX Keep a usecount in the clockdomain code | |
3269 | */ | |
3270 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3271 | struct omap_hwmod *init_oh) | |
3272 | { | |
3273 | return _del_initiator_dep(oh, init_oh); | |
3274 | } | |
3275 | ||
63c85238 PW |
3276 | /** |
3277 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3278 | * @oh: struct omap_hwmod * | |
3279 | * | |
3280 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3281 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3282 | * this IP block if it has dynamic mux entries. Eventually this | |
3283 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3284 | * wakeup events from the module. Does not set any wakeup routing | |
3285 | * registers beyond this point - if the module is to wake up any other | |
3286 | * module or subsystem, that must be set separately. Called by | |
3287 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3288 | */ |
3289 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3290 | { | |
dc6d1cda | 3291 | unsigned long flags; |
5a7ddcbd | 3292 | u32 v; |
dc6d1cda | 3293 | |
dc6d1cda | 3294 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3295 | |
3296 | if (oh->class->sysc && | |
3297 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3298 | v = oh->_sysc_cache; | |
3299 | _enable_wakeup(oh, &v); | |
3300 | _write_sysconfig(v, oh); | |
3301 | } | |
3302 | ||
eceec009 | 3303 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3304 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3305 | |
3306 | return 0; | |
3307 | } | |
3308 | ||
3309 | /** | |
3310 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3311 | * @oh: struct omap_hwmod * | |
3312 | * | |
3313 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3314 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3315 | * events for this IP block if it has dynamic mux entries. Eventually | |
3316 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3317 | * wakeup events from the module. Does not set any wakeup routing | |
3318 | * registers beyond this point - if the module is to wake up any other | |
3319 | * module or subsystem, that must be set separately. Called by | |
3320 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3321 | */ |
3322 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3323 | { | |
dc6d1cda | 3324 | unsigned long flags; |
5a7ddcbd | 3325 | u32 v; |
dc6d1cda | 3326 | |
dc6d1cda | 3327 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3328 | |
3329 | if (oh->class->sysc && | |
3330 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3331 | v = oh->_sysc_cache; | |
3332 | _disable_wakeup(oh, &v); | |
3333 | _write_sysconfig(v, oh); | |
3334 | } | |
3335 | ||
eceec009 | 3336 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3337 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3338 | |
3339 | return 0; | |
3340 | } | |
43b40992 | 3341 | |
aee48e3c PW |
3342 | /** |
3343 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3344 | * contained in the hwmod module. | |
3345 | * @oh: struct omap_hwmod * | |
3346 | * @name: name of the reset line to lookup and assert | |
3347 | * | |
3348 | * Some IP like dsp, ipu or iva contain processor that require | |
3349 | * an HW reset line to be assert / deassert in order to enable fully | |
3350 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3351 | * yet supported on this OMAP; otherwise, passes along the return value | |
3352 | * from _assert_hardreset(). | |
3353 | */ | |
3354 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3355 | { | |
3356 | int ret; | |
dc6d1cda | 3357 | unsigned long flags; |
aee48e3c PW |
3358 | |
3359 | if (!oh) | |
3360 | return -EINVAL; | |
3361 | ||
dc6d1cda | 3362 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3363 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3364 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3365 | |
3366 | return ret; | |
3367 | } | |
3368 | ||
3369 | /** | |
3370 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3371 | * contained in the hwmod module. | |
3372 | * @oh: struct omap_hwmod * | |
3373 | * @name: name of the reset line to look up and deassert | |
3374 | * | |
3375 | * Some IP like dsp, ipu or iva contain processor that require | |
3376 | * an HW reset line to be assert / deassert in order to enable fully | |
3377 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3378 | * yet supported on this OMAP; otherwise, passes along the return value | |
3379 | * from _deassert_hardreset(). | |
3380 | */ | |
3381 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3382 | { | |
3383 | int ret; | |
dc6d1cda | 3384 | unsigned long flags; |
aee48e3c PW |
3385 | |
3386 | if (!oh) | |
3387 | return -EINVAL; | |
3388 | ||
dc6d1cda | 3389 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3390 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3391 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3392 | |
3393 | return ret; | |
3394 | } | |
3395 | ||
3396 | /** | |
3397 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3398 | * contained in the hwmod module | |
3399 | * @oh: struct omap_hwmod * | |
3400 | * @name: name of the reset line to look up and read | |
3401 | * | |
3402 | * Return the current state of the hwmod @oh's reset line named @name: | |
3403 | * returns -EINVAL upon parameter error or if this operation | |
3404 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3405 | * value from _read_hardreset(). | |
3406 | */ | |
3407 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3408 | { | |
3409 | int ret; | |
dc6d1cda | 3410 | unsigned long flags; |
aee48e3c PW |
3411 | |
3412 | if (!oh) | |
3413 | return -EINVAL; | |
3414 | ||
dc6d1cda | 3415 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3416 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3417 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3418 | |
3419 | return ret; | |
3420 | } | |
3421 | ||
3422 | ||
43b40992 PW |
3423 | /** |
3424 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3425 | * @classname: struct omap_hwmod_class name to search for | |
3426 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3427 | * @user: arbitrary context data to pass to the callback function | |
3428 | * | |
ce35b244 BC |
3429 | * For each omap_hwmod of class @classname, call @fn. |
3430 | * If the callback function returns something other than | |
43b40992 PW |
3431 | * zero, the iterator is terminated, and the callback function's return |
3432 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3433 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3434 | */ | |
3435 | int omap_hwmod_for_each_by_class(const char *classname, | |
3436 | int (*fn)(struct omap_hwmod *oh, | |
3437 | void *user), | |
3438 | void *user) | |
3439 | { | |
3440 | struct omap_hwmod *temp_oh; | |
3441 | int ret = 0; | |
3442 | ||
3443 | if (!classname || !fn) | |
3444 | return -EINVAL; | |
3445 | ||
3446 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3447 | __func__, classname); | |
3448 | ||
43b40992 PW |
3449 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3450 | if (!strcmp(temp_oh->class->name, classname)) { | |
3451 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3452 | __func__, temp_oh->name); | |
3453 | ret = (*fn)(temp_oh, user); | |
3454 | if (ret) | |
3455 | break; | |
3456 | } | |
3457 | } | |
3458 | ||
43b40992 PW |
3459 | if (ret) |
3460 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3461 | __func__, ret); | |
3462 | ||
3463 | return ret; | |
3464 | } | |
3465 | ||
2092e5cc PW |
3466 | /** |
3467 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3468 | * @oh: struct omap_hwmod * | |
3469 | * @state: state that _setup() should leave the hwmod in | |
3470 | * | |
550c8092 | 3471 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3472 | * (called by omap_hwmod_setup_*()). See also the documentation |
3473 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3474 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3475 | * in the wrong state. | |
2092e5cc PW |
3476 | */ |
3477 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3478 | { | |
3479 | int ret; | |
dc6d1cda | 3480 | unsigned long flags; |
2092e5cc PW |
3481 | |
3482 | if (!oh) | |
3483 | return -EINVAL; | |
3484 | ||
3485 | if (state != _HWMOD_STATE_DISABLED && | |
3486 | state != _HWMOD_STATE_ENABLED && | |
3487 | state != _HWMOD_STATE_IDLE) | |
3488 | return -EINVAL; | |
3489 | ||
dc6d1cda | 3490 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3491 | |
3492 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3493 | ret = -EINVAL; | |
3494 | goto ohsps_unlock; | |
3495 | } | |
3496 | ||
3497 | oh->_postsetup_state = state; | |
3498 | ret = 0; | |
3499 | ||
3500 | ohsps_unlock: | |
dc6d1cda | 3501 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3502 | |
3503 | return ret; | |
3504 | } | |
c80705aa KH |
3505 | |
3506 | /** | |
3507 | * omap_hwmod_get_context_loss_count - get lost context count | |
3508 | * @oh: struct omap_hwmod * | |
3509 | * | |
3510 | * Query the powerdomain of of @oh to get the context loss | |
3511 | * count for this device. | |
3512 | * | |
3513 | * Returns the context loss count of the powerdomain assocated with @oh | |
3514 | * upon success, or zero if no powerdomain exists for @oh. | |
3515 | */ | |
fc013873 | 3516 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3517 | { |
3518 | struct powerdomain *pwrdm; | |
3519 | int ret = 0; | |
3520 | ||
3521 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3522 | if (pwrdm) | |
3523 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3524 | ||
3525 | return ret; | |
3526 | } | |
43b01643 PW |
3527 | |
3528 | /** | |
3529 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3530 | * @oh: struct omap_hwmod * | |
3531 | * | |
3532 | * Prevent the hwmod @oh from being reset during the setup process. | |
3533 | * Intended for use by board-*.c files on boards with devices that | |
3534 | * cannot tolerate being reset. Must be called before the hwmod has | |
3535 | * been set up. Returns 0 upon success or negative error code upon | |
3536 | * failure. | |
3537 | */ | |
3538 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3539 | { | |
3540 | if (!oh) | |
3541 | return -EINVAL; | |
3542 | ||
3543 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3544 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3545 | oh->name); | |
3546 | return -EINVAL; | |
3547 | } | |
3548 | ||
3549 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3550 | ||
3551 | return 0; | |
3552 | } | |
abc2d545 TK |
3553 | |
3554 | /** | |
3555 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3556 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3557 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3558 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3559 | * | |
3560 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3561 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3562 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3563 | * this function is not called for a given pad_idx, then the ISR | |
3564 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3565 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3566 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3567 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3568 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3569 | * must be called separately for each pad that requires its interrupt | |
3570 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3571 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3572 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3573 | * | |
3574 | * XXX This function interface is fragile. Rather than using array | |
3575 | * indexes, which are subject to unpredictable change, it should be | |
3576 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3577 | * pad records. | |
3578 | */ | |
3579 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3580 | { | |
3581 | int nr_irqs; | |
3582 | ||
3583 | might_sleep(); | |
3584 | ||
3585 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3586 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3587 | return -EINVAL; | |
3588 | ||
3589 | /* Check the number of available mpu_irqs */ | |
3590 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3591 | ; | |
3592 | ||
3593 | if (irq_idx >= nr_irqs) | |
3594 | return -EINVAL; | |
3595 | ||
3596 | if (!oh->mux->irqs) { | |
3597 | /* XXX What frees this? */ | |
3598 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3599 | GFP_KERNEL); | |
3600 | if (!oh->mux->irqs) | |
3601 | return -ENOMEM; | |
3602 | } | |
3603 | oh->mux->irqs[pad_idx] = irq_idx; | |
3604 | ||
3605 | return 0; | |
3606 | } | |
9ebfd285 KH |
3607 | |
3608 | /** | |
3609 | * omap_hwmod_init - initialize the hwmod code | |
3610 | * | |
3611 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3612 | * currently-booted SoC. Intended to be called once during kernel init | |
3613 | * before any hwmods are registered. No return value. | |
3614 | */ | |
3615 | void __init omap_hwmod_init(void) | |
3616 | { | |
8f6aa8ee KH |
3617 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3618 | soc_ops.wait_target_ready = _omap2_wait_target_ready; | |
b8249cf2 KH |
3619 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3620 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3621 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
8f6aa8ee | 3622 | } else if (cpu_is_omap44xx()) { |
9ebfd285 KH |
3623 | soc_ops.enable_module = _omap4_enable_module; |
3624 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 3625 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
3626 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3627 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
3628 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 3629 | soc_ops.init_clkdm = _init_clkdm; |
8f6aa8ee KH |
3630 | } else { |
3631 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
3632 | } |
3633 | ||
3634 | inited = true; | |
3635 | } | |
68c9a95e TL |
3636 | |
3637 | /** | |
3638 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
3639 | * @oh: struct omap_hwmod * | |
3640 | * | |
3641 | * Returns the main clock name assocated with @oh upon success, | |
3642 | * or NULL if @oh is NULL. | |
3643 | */ | |
3644 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
3645 | { | |
3646 | if (!oh) | |
3647 | return NULL; | |
3648 | ||
3649 | return oh->main_clk; | |
3650 | } |