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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5dd3bb5 | 133 | #include <linux/clk-provider.h> |
63c85238 PW |
134 | #include <linux/delay.h> |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
f7b861b7 | 141 | #include <linux/cpu.h> |
079abade SS |
142 | #include <linux/of.h> |
143 | #include <linux/of_address.h> | |
63c85238 | 144 | |
fa200222 PW |
145 | #include <asm/system_misc.h> |
146 | ||
a135eaae | 147 | #include "clock.h" |
2a296c8f | 148 | #include "omap_hwmod.h" |
63c85238 | 149 | |
dbc04161 TL |
150 | #include "soc.h" |
151 | #include "common.h" | |
152 | #include "clockdomain.h" | |
153 | #include "powerdomain.h" | |
ff4ae5d9 PW |
154 | #include "cm2xxx.h" |
155 | #include "cm3xxx.h" | |
d0f0631d | 156 | #include "cminst44xx.h" |
1688bf19 | 157 | #include "cm33xx.h" |
b13159af | 158 | #include "prm.h" |
139563ad | 159 | #include "prm3xxx.h" |
d198b514 | 160 | #include "prm44xx.h" |
1688bf19 | 161 | #include "prm33xx.h" |
eaac329d | 162 | #include "prminst44xx.h" |
8d9af88f | 163 | #include "mux.h" |
5165882a | 164 | #include "pm.h" |
63c85238 | 165 | |
63c85238 | 166 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 167 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 168 | |
2221b5cd PW |
169 | /* |
170 | * Number of struct omap_hwmod_link records per struct | |
171 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
172 | */ | |
173 | #define LINKS_PER_OCP_IF 2 | |
174 | ||
9ebfd285 KH |
175 | /** |
176 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
177 | * @enable_module: function to enable a module (via MODULEMODE) | |
178 | * @disable_module: function to disable a module (via MODULEMODE) | |
179 | * | |
180 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
181 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
182 | * conditionals in this code. | |
183 | */ | |
184 | struct omap_hwmod_soc_ops { | |
185 | void (*enable_module)(struct omap_hwmod *oh); | |
186 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 187 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
188 | int (*assert_hardreset)(struct omap_hwmod *oh, |
189 | struct omap_hwmod_rst_info *ohri); | |
190 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
191 | struct omap_hwmod_rst_info *ohri); | |
192 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
193 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 194 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
195 | void (*update_context_lost)(struct omap_hwmod *oh); |
196 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9ebfd285 KH |
197 | }; |
198 | ||
199 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
200 | static struct omap_hwmod_soc_ops soc_ops; | |
201 | ||
63c85238 PW |
202 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
203 | static LIST_HEAD(omap_hwmod_list); | |
204 | ||
63c85238 PW |
205 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
206 | static struct omap_hwmod *mpu_oh; | |
207 | ||
5165882a VB |
208 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
209 | static DEFINE_SPINLOCK(io_chain_lock); | |
210 | ||
2221b5cd PW |
211 | /* |
212 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
213 | * allocated from - used to reduce the number of small memory | |
214 | * allocations, which has a significant impact on performance | |
215 | */ | |
216 | static struct omap_hwmod_link *linkspace; | |
217 | ||
218 | /* | |
219 | * free_ls, max_ls: array indexes into linkspace; representing the | |
220 | * next free struct omap_hwmod_link index, and the maximum number of | |
221 | * struct omap_hwmod_link records allocated (respectively) | |
222 | */ | |
223 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 224 | |
9ebfd285 KH |
225 | /* inited: set to true once the hwmod code is initialized */ |
226 | static bool inited; | |
227 | ||
63c85238 PW |
228 | /* Private functions */ |
229 | ||
5d95dde7 | 230 | /** |
11cd4b94 | 231 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 232 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
233 | * @i: pointer to the index of the element pointed to by @p in the list |
234 | * | |
235 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
236 | * containing the struct list_head pointed to by @p, and increment | |
237 | * @p such that a future call to this routine will return the next | |
238 | * record. | |
5d95dde7 PW |
239 | */ |
240 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
241 | int *i) |
242 | { | |
243 | struct omap_hwmod_ocp_if *oi; | |
244 | ||
11cd4b94 PW |
245 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
246 | *p = (*p)->next; | |
2221b5cd | 247 | |
5d95dde7 PW |
248 | *i = *i + 1; |
249 | ||
250 | return oi; | |
251 | } | |
252 | ||
63c85238 PW |
253 | /** |
254 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
255 | * @oh: struct omap_hwmod * | |
256 | * | |
257 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
258 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
259 | * OCP_SYSCONFIG register or 0 upon success. | |
260 | */ | |
261 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
262 | { | |
43b40992 PW |
263 | if (!oh->class->sysc) { |
264 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
265 | return -EINVAL; |
266 | } | |
267 | ||
268 | /* XXX ensure module interface clock is up */ | |
269 | ||
cc7a1d2a | 270 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 271 | |
43b40992 | 272 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 273 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
280 | * @v: OCP_SYSCONFIG value to write | |
281 | * @oh: struct omap_hwmod * | |
282 | * | |
43b40992 PW |
283 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
284 | * one. No return value. | |
63c85238 PW |
285 | */ |
286 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
287 | { | |
43b40992 PW |
288 | if (!oh->class->sysc) { |
289 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
290 | return; |
291 | } | |
292 | ||
293 | /* XXX ensure module interface clock is up */ | |
294 | ||
233cbe5b RN |
295 | /* Module might have lost context, always update cache and register */ |
296 | oh->_sysc_cache = v; | |
297 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
298 | } |
299 | ||
300 | /** | |
301 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
302 | * @oh: struct omap_hwmod * | |
303 | * @standbymode: MIDLEMODE field bits | |
304 | * @v: pointer to register contents to modify | |
305 | * | |
306 | * Update the master standby mode bits in @v to be @standbymode for | |
307 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
308 | * upon error or 0 upon success. | |
309 | */ | |
310 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
311 | u32 *v) | |
312 | { | |
358f0e63 TG |
313 | u32 mstandby_mask; |
314 | u8 mstandby_shift; | |
315 | ||
43b40992 PW |
316 | if (!oh->class->sysc || |
317 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
318 | return -EINVAL; |
319 | ||
43b40992 PW |
320 | if (!oh->class->sysc->sysc_fields) { |
321 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
322 | return -EINVAL; |
323 | } | |
324 | ||
43b40992 | 325 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
326 | mstandby_mask = (0x3 << mstandby_shift); |
327 | ||
328 | *v &= ~mstandby_mask; | |
329 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
330 | |
331 | return 0; | |
332 | } | |
333 | ||
334 | /** | |
335 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
336 | * @oh: struct omap_hwmod * | |
337 | * @idlemode: SIDLEMODE field bits | |
338 | * @v: pointer to register contents to modify | |
339 | * | |
340 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
341 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
342 | * or 0 upon success. | |
343 | */ | |
344 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
345 | { | |
358f0e63 TG |
346 | u32 sidle_mask; |
347 | u8 sidle_shift; | |
348 | ||
43b40992 PW |
349 | if (!oh->class->sysc || |
350 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
351 | return -EINVAL; |
352 | ||
43b40992 PW |
353 | if (!oh->class->sysc->sysc_fields) { |
354 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
355 | return -EINVAL; |
356 | } | |
357 | ||
43b40992 | 358 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
359 | sidle_mask = (0x3 << sidle_shift); |
360 | ||
361 | *v &= ~sidle_mask; | |
362 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
363 | |
364 | return 0; | |
365 | } | |
366 | ||
367 | /** | |
368 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
369 | * @oh: struct omap_hwmod * | |
370 | * @clockact: CLOCKACTIVITY field bits | |
371 | * @v: pointer to register contents to modify | |
372 | * | |
373 | * Update the clockactivity mode bits in @v to be @clockact for the | |
374 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
375 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
376 | * success. | |
377 | */ | |
378 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
379 | { | |
358f0e63 TG |
380 | u32 clkact_mask; |
381 | u8 clkact_shift; | |
382 | ||
43b40992 PW |
383 | if (!oh->class->sysc || |
384 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
385 | return -EINVAL; |
386 | ||
43b40992 PW |
387 | if (!oh->class->sysc->sysc_fields) { |
388 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
389 | return -EINVAL; |
390 | } | |
391 | ||
43b40992 | 392 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
393 | clkact_mask = (0x3 << clkact_shift); |
394 | ||
395 | *v &= ~clkact_mask; | |
396 | *v |= clockact << clkact_shift; | |
63c85238 PW |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
401 | /** | |
313a76ee | 402 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
403 | * @oh: struct omap_hwmod * |
404 | * @v: pointer to register contents to modify | |
405 | * | |
406 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
407 | * error or 0 upon success. | |
408 | */ | |
409 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
410 | { | |
358f0e63 TG |
411 | u32 softrst_mask; |
412 | ||
43b40992 PW |
413 | if (!oh->class->sysc || |
414 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
415 | return -EINVAL; |
416 | ||
43b40992 PW |
417 | if (!oh->class->sysc->sysc_fields) { |
418 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
419 | return -EINVAL; |
420 | } | |
421 | ||
43b40992 | 422 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
423 | |
424 | *v |= softrst_mask; | |
63c85238 PW |
425 | |
426 | return 0; | |
427 | } | |
428 | ||
313a76ee RQ |
429 | /** |
430 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
431 | * @oh: struct omap_hwmod * | |
432 | * @v: pointer to register contents to modify | |
433 | * | |
434 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
435 | * error or 0 upon success. | |
436 | */ | |
437 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
438 | { | |
439 | u32 softrst_mask; | |
440 | ||
441 | if (!oh->class->sysc || | |
442 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
443 | return -EINVAL; | |
444 | ||
445 | if (!oh->class->sysc->sysc_fields) { | |
446 | WARN(1, | |
447 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
448 | oh->name); | |
449 | return -EINVAL; | |
450 | } | |
451 | ||
452 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
453 | ||
454 | *v &= ~softrst_mask; | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
613ad0e9 TK |
459 | /** |
460 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
461 | * @oh: struct omap_hwmod * to wait on | |
462 | * | |
463 | * Wait until the IP block represented by @oh reports that its OCP | |
464 | * softreset is complete. This can be triggered by software (see | |
465 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
466 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
467 | * microseconds. Returns the number of microseconds waited. | |
468 | */ | |
469 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
470 | { | |
471 | struct omap_hwmod_class_sysconfig *sysc; | |
472 | u32 softrst_mask; | |
473 | int c = 0; | |
474 | ||
475 | sysc = oh->class->sysc; | |
476 | ||
477 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS) | |
478 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) | |
479 | & SYSS_RESETDONE_MASK), | |
480 | MAX_MODULE_SOFTRESET_WAIT, c); | |
481 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
482 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
483 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
484 | & softrst_mask), | |
485 | MAX_MODULE_SOFTRESET_WAIT, c); | |
486 | } | |
487 | ||
488 | return c; | |
489 | } | |
490 | ||
6668546f KVA |
491 | /** |
492 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
493 | * @oh: struct omap_hwmod * | |
494 | * | |
495 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
496 | * of some modules. When the DMA must perform read/write accesses, the | |
497 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
498 | * for power management, software must set the DMADISABLE bit back to 1. | |
499 | * | |
500 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
501 | * error or 0 upon success. | |
502 | */ | |
503 | static int _set_dmadisable(struct omap_hwmod *oh) | |
504 | { | |
505 | u32 v; | |
506 | u32 dmadisable_mask; | |
507 | ||
508 | if (!oh->class->sysc || | |
509 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
510 | return -EINVAL; | |
511 | ||
512 | if (!oh->class->sysc->sysc_fields) { | |
513 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | /* clocks must be on for this operation */ | |
518 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
519 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
520 | return -EINVAL; | |
521 | } | |
522 | ||
523 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
524 | ||
525 | v = oh->_sysc_cache; | |
526 | dmadisable_mask = | |
527 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
528 | v |= dmadisable_mask; | |
529 | _write_sysconfig(v, oh); | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
726072e5 PW |
534 | /** |
535 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
536 | * @oh: struct omap_hwmod * | |
537 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
538 | * @v: pointer to register contents to modify | |
539 | * | |
540 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
541 | * hwmod. The autoidle bit controls whether the module can gate | |
542 | * internal clocks automatically when it isn't doing anything; the | |
543 | * exact function of this bit varies on a per-module basis. This | |
544 | * function does not write to the hardware. Returns -EINVAL upon | |
545 | * error or 0 upon success. | |
546 | */ | |
547 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
548 | u32 *v) | |
549 | { | |
358f0e63 TG |
550 | u32 autoidle_mask; |
551 | u8 autoidle_shift; | |
552 | ||
43b40992 PW |
553 | if (!oh->class->sysc || |
554 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
555 | return -EINVAL; |
556 | ||
43b40992 PW |
557 | if (!oh->class->sysc->sysc_fields) { |
558 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
559 | return -EINVAL; |
560 | } | |
561 | ||
43b40992 | 562 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 563 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
564 | |
565 | *v &= ~autoidle_mask; | |
566 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
567 | |
568 | return 0; | |
569 | } | |
570 | ||
eceec009 G |
571 | /** |
572 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
573 | * @oh: struct omap_hwmod * | |
574 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
575 | * | |
576 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
577 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
578 | * in memory. If the hwmod is currently idled, and the new idle | |
579 | * values don't match the previous ones, this function will also | |
580 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
581 | * currently idled, this function won't touch the hardware: the new | |
582 | * mux settings are written to the SCM PADCTRL registers when the | |
583 | * hwmod is idled. No return value. | |
584 | */ | |
585 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
586 | { | |
587 | struct omap_device_pad *pad; | |
588 | bool change = false; | |
589 | u16 prev_idle; | |
590 | int j; | |
591 | ||
592 | if (!oh->mux || !oh->mux->enabled) | |
593 | return; | |
594 | ||
595 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
596 | pad = oh->mux->pads_dynamic[j]; | |
597 | ||
598 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
599 | continue; | |
600 | ||
601 | prev_idle = pad->idle; | |
602 | ||
603 | if (set_wake) | |
604 | pad->idle |= OMAP_WAKEUP_EN; | |
605 | else | |
606 | pad->idle &= ~OMAP_WAKEUP_EN; | |
607 | ||
608 | if (prev_idle != pad->idle) | |
609 | change = true; | |
610 | } | |
611 | ||
612 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
613 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
614 | } | |
615 | ||
63c85238 PW |
616 | /** |
617 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
618 | * @oh: struct omap_hwmod * | |
619 | * | |
620 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
621 | * upon error or 0 upon success. | |
622 | */ | |
5a7ddcbd | 623 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 624 | { |
43b40992 | 625 | if (!oh->class->sysc || |
86009eb3 | 626 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
627 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
628 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
629 | return -EINVAL; |
630 | ||
43b40992 PW |
631 | if (!oh->class->sysc->sysc_fields) { |
632 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
633 | return -EINVAL; |
634 | } | |
635 | ||
1fe74113 BC |
636 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
637 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 638 | |
86009eb3 BC |
639 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
640 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
641 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
642 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 643 | |
63c85238 PW |
644 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
645 | ||
63c85238 PW |
646 | return 0; |
647 | } | |
648 | ||
649 | /** | |
650 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
651 | * @oh: struct omap_hwmod * | |
652 | * | |
653 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
654 | * upon error or 0 upon success. | |
655 | */ | |
5a7ddcbd | 656 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 657 | { |
43b40992 | 658 | if (!oh->class->sysc || |
86009eb3 | 659 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
660 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
661 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
662 | return -EINVAL; |
663 | ||
43b40992 PW |
664 | if (!oh->class->sysc->sysc_fields) { |
665 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
666 | return -EINVAL; |
667 | } | |
668 | ||
1fe74113 BC |
669 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
670 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 671 | |
86009eb3 BC |
672 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
673 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 674 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 675 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 676 | |
63c85238 PW |
677 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
678 | ||
63c85238 PW |
679 | return 0; |
680 | } | |
681 | ||
f5dd3bb5 RN |
682 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
683 | { | |
c4a1ea2c RN |
684 | struct clk_hw_omap *clk; |
685 | ||
f5dd3bb5 RN |
686 | if (oh->clkdm) { |
687 | return oh->clkdm; | |
688 | } else if (oh->_clk) { | |
924f9498 TK |
689 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
690 | return NULL; | |
f5dd3bb5 RN |
691 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
692 | return clk->clkdm; | |
f5dd3bb5 RN |
693 | } |
694 | return NULL; | |
695 | } | |
696 | ||
63c85238 PW |
697 | /** |
698 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
699 | * @oh: struct omap_hwmod * | |
700 | * | |
701 | * Prevent the hardware module @oh from entering idle while the | |
702 | * hardare module initiator @init_oh is active. Useful when a module | |
703 | * will be accessed by a particular initiator (e.g., if a module will | |
704 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
705 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
706 | * mode. If the clockdomain is marked as not needing autodeps, return |
707 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
708 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
709 | */ |
710 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
711 | { | |
f5dd3bb5 RN |
712 | struct clockdomain *clkdm, *init_clkdm; |
713 | ||
714 | clkdm = _get_clkdm(oh); | |
715 | init_clkdm = _get_clkdm(init_oh); | |
716 | ||
717 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
718 | return -EINVAL; |
719 | ||
f5dd3bb5 | 720 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
721 | return 0; |
722 | ||
f5dd3bb5 | 723 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
724 | } |
725 | ||
726 | /** | |
727 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
728 | * @oh: struct omap_hwmod * | |
729 | * | |
730 | * Allow the hardware module @oh to enter idle while the hardare | |
731 | * module initiator @init_oh is active. Useful when a module will not | |
732 | * be accessed by a particular initiator (e.g., if a module will not | |
733 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
734 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
735 | * mode. If the clockdomain is marked as not needing autodeps, return |
736 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
737 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
738 | */ |
739 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
740 | { | |
f5dd3bb5 RN |
741 | struct clockdomain *clkdm, *init_clkdm; |
742 | ||
743 | clkdm = _get_clkdm(oh); | |
744 | init_clkdm = _get_clkdm(init_oh); | |
745 | ||
746 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
747 | return -EINVAL; |
748 | ||
f5dd3bb5 | 749 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
750 | return 0; |
751 | ||
f5dd3bb5 | 752 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
753 | } |
754 | ||
755 | /** | |
756 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
757 | * @oh: struct omap_hwmod * | |
758 | * | |
759 | * Called from _init_clocks(). Populates the @oh _clk (main | |
760 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
761 | * success or -EINVAL on error. | |
762 | */ | |
763 | static int _init_main_clk(struct omap_hwmod *oh) | |
764 | { | |
63c85238 PW |
765 | int ret = 0; |
766 | ||
50ebdac2 | 767 | if (!oh->main_clk) |
63c85238 PW |
768 | return 0; |
769 | ||
6ea74cb9 RN |
770 | oh->_clk = clk_get(NULL, oh->main_clk); |
771 | if (IS_ERR(oh->_clk)) { | |
20383d82 BC |
772 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
773 | oh->name, oh->main_clk); | |
63403384 | 774 | return -EINVAL; |
dc75925d | 775 | } |
4d7cb45e RN |
776 | /* |
777 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
778 | * to do something meaningful. Today its just a no-op. | |
779 | * If clk_prepare() is used at some point to do things like | |
780 | * voltage scaling etc, then this would have to be moved to | |
781 | * some point where subsystems like i2c and pmic become | |
782 | * available. | |
783 | */ | |
784 | clk_prepare(oh->_clk); | |
63c85238 | 785 | |
f5dd3bb5 | 786 | if (!_get_clkdm(oh)) |
3bb05dbf | 787 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 788 | oh->name, oh->main_clk); |
81d7c6ff | 789 | |
63c85238 PW |
790 | return ret; |
791 | } | |
792 | ||
793 | /** | |
887adeac | 794 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
795 | * @oh: struct omap_hwmod * |
796 | * | |
797 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
798 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
799 | */ | |
800 | static int _init_interface_clks(struct omap_hwmod *oh) | |
801 | { | |
5d95dde7 | 802 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 803 | struct list_head *p; |
63c85238 | 804 | struct clk *c; |
5d95dde7 | 805 | int i = 0; |
63c85238 PW |
806 | int ret = 0; |
807 | ||
11cd4b94 | 808 | p = oh->slave_ports.next; |
2221b5cd | 809 | |
5d95dde7 | 810 | while (i < oh->slaves_cnt) { |
11cd4b94 | 811 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 812 | if (!os->clk) |
63c85238 PW |
813 | continue; |
814 | ||
6ea74cb9 RN |
815 | c = clk_get(NULL, os->clk); |
816 | if (IS_ERR(c)) { | |
20383d82 BC |
817 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
818 | oh->name, os->clk); | |
63c85238 | 819 | ret = -EINVAL; |
0e7dc862 | 820 | continue; |
dc75925d | 821 | } |
63c85238 | 822 | os->_clk = c; |
4d7cb45e RN |
823 | /* |
824 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
825 | * to do something meaningful. Today its just a no-op. | |
826 | * If clk_prepare() is used at some point to do things like | |
827 | * voltage scaling etc, then this would have to be moved to | |
828 | * some point where subsystems like i2c and pmic become | |
829 | * available. | |
830 | */ | |
831 | clk_prepare(os->_clk); | |
63c85238 PW |
832 | } |
833 | ||
834 | return ret; | |
835 | } | |
836 | ||
837 | /** | |
838 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
839 | * @oh: struct omap_hwmod * | |
840 | * | |
841 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
842 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
843 | */ | |
844 | static int _init_opt_clks(struct omap_hwmod *oh) | |
845 | { | |
846 | struct omap_hwmod_opt_clk *oc; | |
847 | struct clk *c; | |
848 | int i; | |
849 | int ret = 0; | |
850 | ||
851 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
852 | c = clk_get(NULL, oc->clk); |
853 | if (IS_ERR(c)) { | |
20383d82 BC |
854 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
855 | oh->name, oc->clk); | |
63c85238 | 856 | ret = -EINVAL; |
0e7dc862 | 857 | continue; |
dc75925d | 858 | } |
63c85238 | 859 | oc->_clk = c; |
4d7cb45e RN |
860 | /* |
861 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
862 | * to do something meaningful. Today its just a no-op. | |
863 | * If clk_prepare() is used at some point to do things like | |
864 | * voltage scaling etc, then this would have to be moved to | |
865 | * some point where subsystems like i2c and pmic become | |
866 | * available. | |
867 | */ | |
868 | clk_prepare(oc->_clk); | |
63c85238 PW |
869 | } |
870 | ||
871 | return ret; | |
872 | } | |
873 | ||
874 | /** | |
875 | * _enable_clocks - enable hwmod main clock and interface clocks | |
876 | * @oh: struct omap_hwmod * | |
877 | * | |
878 | * Enables all clocks necessary for register reads and writes to succeed | |
879 | * on the hwmod @oh. Returns 0. | |
880 | */ | |
881 | static int _enable_clocks(struct omap_hwmod *oh) | |
882 | { | |
5d95dde7 | 883 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 884 | struct list_head *p; |
5d95dde7 | 885 | int i = 0; |
63c85238 PW |
886 | |
887 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
888 | ||
4d3ae5a9 | 889 | if (oh->_clk) |
63c85238 PW |
890 | clk_enable(oh->_clk); |
891 | ||
11cd4b94 | 892 | p = oh->slave_ports.next; |
2221b5cd | 893 | |
5d95dde7 | 894 | while (i < oh->slaves_cnt) { |
11cd4b94 | 895 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 896 | |
5d95dde7 PW |
897 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
898 | clk_enable(os->_clk); | |
63c85238 PW |
899 | } |
900 | ||
901 | /* The opt clocks are controlled by the device driver. */ | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | /** | |
907 | * _disable_clocks - disable hwmod main clock and interface clocks | |
908 | * @oh: struct omap_hwmod * | |
909 | * | |
910 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
911 | */ | |
912 | static int _disable_clocks(struct omap_hwmod *oh) | |
913 | { | |
5d95dde7 | 914 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 915 | struct list_head *p; |
5d95dde7 | 916 | int i = 0; |
63c85238 PW |
917 | |
918 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
919 | ||
4d3ae5a9 | 920 | if (oh->_clk) |
63c85238 PW |
921 | clk_disable(oh->_clk); |
922 | ||
11cd4b94 | 923 | p = oh->slave_ports.next; |
2221b5cd | 924 | |
5d95dde7 | 925 | while (i < oh->slaves_cnt) { |
11cd4b94 | 926 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 927 | |
5d95dde7 PW |
928 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
929 | clk_disable(os->_clk); | |
63c85238 PW |
930 | } |
931 | ||
932 | /* The opt clocks are controlled by the device driver. */ | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
96835af9 BC |
937 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
938 | { | |
939 | struct omap_hwmod_opt_clk *oc; | |
940 | int i; | |
941 | ||
942 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
943 | ||
944 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
945 | if (oc->_clk) { | |
946 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 947 | __clk_get_name(oc->_clk)); |
96835af9 BC |
948 | clk_enable(oc->_clk); |
949 | } | |
950 | } | |
951 | ||
952 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
953 | { | |
954 | struct omap_hwmod_opt_clk *oc; | |
955 | int i; | |
956 | ||
957 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
958 | ||
959 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
960 | if (oc->_clk) { | |
961 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 962 | __clk_get_name(oc->_clk)); |
96835af9 BC |
963 | clk_disable(oc->_clk); |
964 | } | |
965 | } | |
966 | ||
45c38252 | 967 | /** |
3d9f0327 | 968 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
969 | * @oh: struct omap_hwmod * |
970 | * | |
971 | * Enables the PRCM module mode related to the hwmod @oh. | |
972 | * No return value. | |
973 | */ | |
3d9f0327 | 974 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 975 | { |
45c38252 BC |
976 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
977 | return; | |
978 | ||
3d9f0327 KH |
979 | pr_debug("omap_hwmod: %s: %s: %d\n", |
980 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
981 | |
982 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
983 | oh->clkdm->prcm_partition, | |
984 | oh->clkdm->cm_inst, | |
985 | oh->clkdm->clkdm_offs, | |
986 | oh->prcm.omap4.clkctrl_offs); | |
987 | } | |
988 | ||
1688bf19 VH |
989 | /** |
990 | * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX | |
991 | * @oh: struct omap_hwmod * | |
992 | * | |
993 | * Enables the PRCM module mode related to the hwmod @oh. | |
994 | * No return value. | |
995 | */ | |
996 | static void _am33xx_enable_module(struct omap_hwmod *oh) | |
997 | { | |
998 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
999 | return; | |
1000 | ||
1001 | pr_debug("omap_hwmod: %s: %s: %d\n", | |
1002 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
1003 | ||
1004 | am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, | |
1005 | oh->clkdm->clkdm_offs, | |
1006 | oh->prcm.omap4.clkctrl_offs); | |
1007 | } | |
1008 | ||
45c38252 | 1009 | /** |
bfc141e3 BC |
1010 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
1011 | * @oh: struct omap_hwmod * | |
1012 | * | |
1013 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1014 | * does not have an IDLEST bit or if the module successfully enters | |
1015 | * slave idle; otherwise, pass along the return value of the | |
1016 | * appropriate *_cm*_wait_module_idle() function. | |
1017 | */ | |
1018 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
1019 | { | |
2b026d13 | 1020 | if (!oh) |
bfc141e3 BC |
1021 | return -EINVAL; |
1022 | ||
2b026d13 | 1023 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1024 | return 0; |
1025 | ||
1026 | if (oh->flags & HWMOD_NO_IDLEST) | |
1027 | return 0; | |
1028 | ||
1029 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
1030 | oh->clkdm->cm_inst, | |
1031 | oh->clkdm->clkdm_offs, | |
1032 | oh->prcm.omap4.clkctrl_offs); | |
1033 | } | |
1034 | ||
1688bf19 VH |
1035 | /** |
1036 | * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX | |
1037 | * @oh: struct omap_hwmod * | |
1038 | * | |
1039 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1040 | * does not have an IDLEST bit or if the module successfully enters | |
1041 | * slave idle; otherwise, pass along the return value of the | |
1042 | * appropriate *_cm*_wait_module_idle() function. | |
1043 | */ | |
1044 | static int _am33xx_wait_target_disable(struct omap_hwmod *oh) | |
1045 | { | |
1046 | if (!oh) | |
1047 | return -EINVAL; | |
1048 | ||
1049 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1050 | return 0; | |
1051 | ||
1052 | if (oh->flags & HWMOD_NO_IDLEST) | |
1053 | return 0; | |
1054 | ||
1055 | return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, | |
1056 | oh->clkdm->clkdm_offs, | |
1057 | oh->prcm.omap4.clkctrl_offs); | |
1058 | } | |
1059 | ||
212738a4 PW |
1060 | /** |
1061 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
1062 | * @oh: struct omap_hwmod *oh | |
1063 | * | |
1064 | * Count and return the number of MPU IRQs associated with the hwmod | |
1065 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
1066 | * NULL. | |
1067 | */ | |
1068 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
1069 | { | |
1070 | struct omap_hwmod_irq_info *ohii; | |
1071 | int i = 0; | |
1072 | ||
1073 | if (!oh || !oh->mpu_irqs) | |
1074 | return 0; | |
1075 | ||
1076 | do { | |
1077 | ohii = &oh->mpu_irqs[i++]; | |
1078 | } while (ohii->irq != -1); | |
1079 | ||
cc1b0765 | 1080 | return i-1; |
212738a4 PW |
1081 | } |
1082 | ||
bc614958 PW |
1083 | /** |
1084 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
1085 | * @oh: struct omap_hwmod *oh | |
1086 | * | |
1087 | * Count and return the number of SDMA request lines associated with | |
1088 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1089 | * if @oh is NULL. | |
1090 | */ | |
1091 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1092 | { | |
1093 | struct omap_hwmod_dma_info *ohdi; | |
1094 | int i = 0; | |
1095 | ||
1096 | if (!oh || !oh->sdma_reqs) | |
1097 | return 0; | |
1098 | ||
1099 | do { | |
1100 | ohdi = &oh->sdma_reqs[i++]; | |
1101 | } while (ohdi->dma_req != -1); | |
1102 | ||
cc1b0765 | 1103 | return i-1; |
bc614958 PW |
1104 | } |
1105 | ||
78183f3f PW |
1106 | /** |
1107 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1108 | * @oh: struct omap_hwmod *oh | |
1109 | * | |
1110 | * Count and return the number of address space ranges associated with | |
1111 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1112 | * if @oh is NULL. | |
1113 | */ | |
1114 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1115 | { | |
1116 | struct omap_hwmod_addr_space *mem; | |
1117 | int i = 0; | |
1118 | ||
1119 | if (!os || !os->addr) | |
1120 | return 0; | |
1121 | ||
1122 | do { | |
1123 | mem = &os->addr[i++]; | |
1124 | } while (mem->pa_start != mem->pa_end); | |
1125 | ||
cc1b0765 | 1126 | return i-1; |
78183f3f PW |
1127 | } |
1128 | ||
5e8370f1 PW |
1129 | /** |
1130 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1131 | * @oh: struct omap_hwmod * to operate on | |
1132 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1133 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1134 | * | |
1135 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1136 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1137 | * into the address pointed to by @dma. When @name is non-null, the | |
1138 | * IRQ line number associated with the named entry will be returned. | |
1139 | * If @name is null, the first matching entry will be returned. Data | |
1140 | * order is not meaningful in hwmod data, so callers are strongly | |
1141 | * encouraged to use a non-null @name whenever possible to avoid | |
1142 | * unpredictable effects if hwmod data is later added that causes data | |
1143 | * ordering to change. Returns 0 upon success or a negative error | |
1144 | * code upon error. | |
1145 | */ | |
1146 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1147 | unsigned int *irq) | |
1148 | { | |
1149 | int i; | |
1150 | bool found = false; | |
1151 | ||
1152 | if (!oh->mpu_irqs) | |
1153 | return -ENOENT; | |
1154 | ||
1155 | i = 0; | |
1156 | while (oh->mpu_irqs[i].irq != -1) { | |
1157 | if (name == oh->mpu_irqs[i].name || | |
1158 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1159 | found = true; | |
1160 | break; | |
1161 | } | |
1162 | i++; | |
1163 | } | |
1164 | ||
1165 | if (!found) | |
1166 | return -ENOENT; | |
1167 | ||
1168 | *irq = oh->mpu_irqs[i].irq; | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1175 | * @oh: struct omap_hwmod * to operate on | |
1176 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1177 | * @dma: pointer to an unsigned int to store the request line ID to | |
1178 | * | |
1179 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1180 | * pointed to by @oh. The ID will be filled into the address pointed | |
1181 | * to by @dma. When @name is non-null, the request line ID associated | |
1182 | * with the named entry will be returned. If @name is null, the first | |
1183 | * matching entry will be returned. Data order is not meaningful in | |
1184 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1185 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1186 | * data is later added that causes data ordering to change. Returns 0 | |
1187 | * upon success or a negative error code upon error. | |
1188 | */ | |
1189 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1190 | unsigned int *dma) | |
1191 | { | |
1192 | int i; | |
1193 | bool found = false; | |
1194 | ||
1195 | if (!oh->sdma_reqs) | |
1196 | return -ENOENT; | |
1197 | ||
1198 | i = 0; | |
1199 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1200 | if (name == oh->sdma_reqs[i].name || | |
1201 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1202 | found = true; | |
1203 | break; | |
1204 | } | |
1205 | i++; | |
1206 | } | |
1207 | ||
1208 | if (!found) | |
1209 | return -ENOENT; | |
1210 | ||
1211 | *dma = oh->sdma_reqs[i].dma_req; | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | /** | |
1217 | * _get_addr_space_by_name - fetch address space start & end by name | |
1218 | * @oh: struct omap_hwmod * to operate on | |
1219 | * @name: pointer to the name of the address space to fetch (optional) | |
1220 | * @pa_start: pointer to a u32 to store the starting address to | |
1221 | * @pa_end: pointer to a u32 to store the ending address to | |
1222 | * | |
1223 | * Retrieve address space start and end addresses for the IP block | |
1224 | * pointed to by @oh. The data will be filled into the addresses | |
1225 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1226 | * address space data associated with the named entry will be | |
1227 | * returned. If @name is null, the first matching entry will be | |
1228 | * returned. Data order is not meaningful in hwmod data, so callers | |
1229 | * are strongly encouraged to use a non-null @name whenever possible | |
1230 | * to avoid unpredictable effects if hwmod data is later added that | |
1231 | * causes data ordering to change. Returns 0 upon success or a | |
1232 | * negative error code upon error. | |
1233 | */ | |
1234 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1235 | u32 *pa_start, u32 *pa_end) | |
1236 | { | |
1237 | int i, j; | |
1238 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1239 | struct list_head *p = NULL; |
5e8370f1 PW |
1240 | bool found = false; |
1241 | ||
11cd4b94 | 1242 | p = oh->slave_ports.next; |
2221b5cd | 1243 | |
5d95dde7 PW |
1244 | i = 0; |
1245 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1246 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1247 | |
1248 | if (!os->addr) | |
1249 | return -ENOENT; | |
1250 | ||
1251 | j = 0; | |
1252 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1253 | if (name == os->addr[j].name || | |
1254 | !strcmp(name, os->addr[j].name)) { | |
1255 | found = true; | |
1256 | break; | |
1257 | } | |
1258 | j++; | |
1259 | } | |
1260 | ||
1261 | if (found) | |
1262 | break; | |
1263 | } | |
1264 | ||
1265 | if (!found) | |
1266 | return -ENOENT; | |
1267 | ||
1268 | *pa_start = os->addr[j].pa_start; | |
1269 | *pa_end = os->addr[j].pa_end; | |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
63c85238 | 1274 | /** |
24dbc213 | 1275 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1276 | * @oh: struct omap_hwmod * |
1277 | * | |
24dbc213 PW |
1278 | * Determines the array index of the OCP slave port that the MPU uses |
1279 | * to address the device, and saves it into the struct omap_hwmod. | |
1280 | * Intended to be called during hwmod registration only. No return | |
1281 | * value. | |
63c85238 | 1282 | */ |
24dbc213 | 1283 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1284 | { |
24dbc213 | 1285 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1286 | struct list_head *p; |
5d95dde7 | 1287 | int i = 0; |
63c85238 | 1288 | |
5d95dde7 | 1289 | if (!oh) |
24dbc213 PW |
1290 | return; |
1291 | ||
1292 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1293 | |
11cd4b94 | 1294 | p = oh->slave_ports.next; |
2221b5cd | 1295 | |
5d95dde7 | 1296 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1297 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1298 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1299 | oh->_mpu_port = os; |
24dbc213 | 1300 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1301 | break; |
1302 | } | |
1303 | } | |
1304 | ||
24dbc213 | 1305 | return; |
63c85238 PW |
1306 | } |
1307 | ||
2d6141ba PW |
1308 | /** |
1309 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1310 | * @oh: struct omap_hwmod * | |
1311 | * | |
1312 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1313 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1314 | * communicate with the IP block. This interface need not be directly | |
1315 | * connected to the MPU (and almost certainly is not), but is directly | |
1316 | * connected to the IP block represented by @oh. Returns a pointer | |
1317 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1318 | * error or if there does not appear to be a path from the MPU to this | |
1319 | * IP block. | |
1320 | */ | |
1321 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1322 | { | |
1323 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1324 | return NULL; | |
1325 | ||
11cd4b94 | 1326 | return oh->_mpu_port; |
2d6141ba PW |
1327 | }; |
1328 | ||
63c85238 | 1329 | /** |
c9aafd23 | 1330 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1331 | * @oh: struct omap_hwmod * |
1332 | * | |
c9aafd23 PW |
1333 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1334 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1335 | */ |
c9aafd23 | 1336 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1337 | { |
1338 | struct omap_hwmod_ocp_if *os; | |
1339 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1340 | int found = 0, i = 0; |
63c85238 | 1341 | |
2d6141ba | 1342 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1343 | if (!os || !os->addr) |
78183f3f PW |
1344 | return NULL; |
1345 | ||
1346 | do { | |
1347 | mem = &os->addr[i++]; | |
1348 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1349 | found = 1; |
78183f3f | 1350 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1351 | |
c9aafd23 | 1352 | return (found) ? mem : NULL; |
63c85238 PW |
1353 | } |
1354 | ||
1355 | /** | |
74ff3a68 | 1356 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1357 | * @oh: struct omap_hwmod * |
1358 | * | |
006c7f18 PW |
1359 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1360 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1361 | * Usually this means placing the module into smart-idle mode and | |
1362 | * smart-standby, but if there is a bug in the automatic idle handling | |
1363 | * for the IP block, it may need to be placed into the force-idle or | |
1364 | * no-idle variants of these modes. No return value. | |
63c85238 | 1365 | */ |
74ff3a68 | 1366 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1367 | { |
43b40992 | 1368 | u8 idlemode, sf; |
63c85238 | 1369 | u32 v; |
006c7f18 | 1370 | bool clkdm_act; |
f5dd3bb5 | 1371 | struct clockdomain *clkdm; |
63c85238 | 1372 | |
43b40992 | 1373 | if (!oh->class->sysc) |
63c85238 PW |
1374 | return; |
1375 | ||
613ad0e9 TK |
1376 | /* |
1377 | * Wait until reset has completed, this is needed as the IP | |
1378 | * block is reset automatically by hardware in some cases | |
1379 | * (off-mode for example), and the drivers require the | |
1380 | * IP to be ready when they access it | |
1381 | */ | |
1382 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1383 | _enable_optional_clocks(oh); | |
1384 | _wait_softreset_complete(oh); | |
1385 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1386 | _disable_optional_clocks(oh); | |
1387 | ||
63c85238 | 1388 | v = oh->_sysc_cache; |
43b40992 | 1389 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1390 | |
f5dd3bb5 | 1391 | clkdm = _get_clkdm(oh); |
43b40992 | 1392 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1393 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1394 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1395 | idlemode = HWMOD_IDLEMODE_NO; |
1396 | } else { | |
1397 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1398 | _enable_wakeup(oh, &v); | |
1399 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1400 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1401 | else | |
1402 | idlemode = HWMOD_IDLEMODE_SMART; | |
1403 | } | |
1404 | ||
1405 | /* | |
1406 | * This is special handling for some IPs like | |
1407 | * 32k sync timer. Force them to idle! | |
1408 | */ | |
f5dd3bb5 | 1409 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1410 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1411 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1412 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1413 | |
63c85238 PW |
1414 | _set_slave_idlemode(oh, idlemode, &v); |
1415 | } | |
1416 | ||
43b40992 | 1417 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1418 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1419 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1420 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1421 | idlemode = HWMOD_IDLEMODE_NO; |
1422 | } else { | |
1423 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1424 | _enable_wakeup(oh, &v); | |
1425 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1426 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1427 | else | |
1428 | idlemode = HWMOD_IDLEMODE_SMART; | |
1429 | } | |
63c85238 PW |
1430 | _set_master_standbymode(oh, idlemode, &v); |
1431 | } | |
1432 | ||
a16b1f7f PW |
1433 | /* |
1434 | * XXX The clock framework should handle this, by | |
1435 | * calling into this code. But this must wait until the | |
1436 | * clock structures are tagged with omap_hwmod entries | |
1437 | */ | |
43b40992 PW |
1438 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1439 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1440 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1441 | |
127500cc JH |
1442 | /* If the cached value is the same as the new value, skip the write */ |
1443 | if (oh->_sysc_cache != v) | |
1444 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1445 | |
1446 | /* | |
1447 | * Set the autoidle bit only after setting the smartidle bit | |
1448 | * Setting this will not have any impact on the other modules. | |
1449 | */ | |
1450 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1451 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1452 | 0 : 1; | |
1453 | _set_module_autoidle(oh, idlemode, &v); | |
1454 | _write_sysconfig(v, oh); | |
1455 | } | |
63c85238 PW |
1456 | } |
1457 | ||
1458 | /** | |
74ff3a68 | 1459 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1460 | * @oh: struct omap_hwmod * |
1461 | * | |
1462 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1463 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1464 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1465 | * configure it for smart-standby. No return value. | |
1466 | */ | |
74ff3a68 | 1467 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1468 | { |
43b40992 | 1469 | u8 idlemode, sf; |
63c85238 PW |
1470 | u32 v; |
1471 | ||
43b40992 | 1472 | if (!oh->class->sysc) |
63c85238 PW |
1473 | return; |
1474 | ||
1475 | v = oh->_sysc_cache; | |
43b40992 | 1476 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1477 | |
43b40992 | 1478 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1479 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1480 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1481 | } else { |
1482 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1483 | _enable_wakeup(oh, &v); | |
1484 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1485 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1486 | else | |
1487 | idlemode = HWMOD_IDLEMODE_SMART; | |
1488 | } | |
63c85238 PW |
1489 | _set_slave_idlemode(oh, idlemode, &v); |
1490 | } | |
1491 | ||
43b40992 | 1492 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1493 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1494 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1495 | idlemode = HWMOD_IDLEMODE_FORCE; |
1496 | } else { | |
1497 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1498 | _enable_wakeup(oh, &v); | |
1499 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1500 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1501 | else | |
1502 | idlemode = HWMOD_IDLEMODE_SMART; | |
1503 | } | |
63c85238 PW |
1504 | _set_master_standbymode(oh, idlemode, &v); |
1505 | } | |
1506 | ||
1507 | _write_sysconfig(v, oh); | |
1508 | } | |
1509 | ||
1510 | /** | |
74ff3a68 | 1511 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1512 | * @oh: struct omap_hwmod * |
1513 | * | |
1514 | * Force the module into slave idle and master suspend. No return | |
1515 | * value. | |
1516 | */ | |
74ff3a68 | 1517 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1518 | { |
1519 | u32 v; | |
43b40992 | 1520 | u8 sf; |
63c85238 | 1521 | |
43b40992 | 1522 | if (!oh->class->sysc) |
63c85238 PW |
1523 | return; |
1524 | ||
1525 | v = oh->_sysc_cache; | |
43b40992 | 1526 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1527 | |
43b40992 | 1528 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1529 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1530 | ||
43b40992 | 1531 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1532 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1533 | ||
43b40992 | 1534 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1535 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1536 | |
1537 | _write_sysconfig(v, oh); | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * _lookup - find an omap_hwmod by name | |
1542 | * @name: find an omap_hwmod by name | |
1543 | * | |
1544 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1545 | */ |
1546 | static struct omap_hwmod *_lookup(const char *name) | |
1547 | { | |
1548 | struct omap_hwmod *oh, *temp_oh; | |
1549 | ||
1550 | oh = NULL; | |
1551 | ||
1552 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1553 | if (!strcmp(name, temp_oh->name)) { | |
1554 | oh = temp_oh; | |
1555 | break; | |
1556 | } | |
1557 | } | |
1558 | ||
1559 | return oh; | |
1560 | } | |
868c157d | 1561 | |
6ae76997 BC |
1562 | /** |
1563 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1564 | * @oh: struct omap_hwmod * | |
1565 | * | |
1566 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1567 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1568 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1569 | */ |
1570 | static int _init_clkdm(struct omap_hwmod *oh) | |
1571 | { | |
3bb05dbf PW |
1572 | if (!oh->clkdm_name) { |
1573 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1574 | return 0; |
3bb05dbf | 1575 | } |
6ae76997 | 1576 | |
6ae76997 BC |
1577 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1578 | if (!oh->clkdm) { | |
1579 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1580 | oh->name, oh->clkdm_name); | |
0385c582 | 1581 | return 0; |
6ae76997 BC |
1582 | } |
1583 | ||
1584 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1585 | oh->name, oh->clkdm_name); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
63c85238 PW |
1589 | |
1590 | /** | |
6ae76997 BC |
1591 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1592 | * well the clockdomain. | |
63c85238 | 1593 | * @oh: struct omap_hwmod * |
97d60162 | 1594 | * @data: not used; pass NULL |
63c85238 | 1595 | * |
a2debdbd | 1596 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1597 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1598 | * success, or a negative error code on failure. | |
63c85238 | 1599 | */ |
97d60162 | 1600 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1601 | { |
1602 | int ret = 0; | |
1603 | ||
48d54f3f PW |
1604 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1605 | return 0; | |
63c85238 PW |
1606 | |
1607 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1608 | ||
b797be1d VH |
1609 | if (soc_ops.init_clkdm) |
1610 | ret |= soc_ops.init_clkdm(oh); | |
1611 | ||
63c85238 PW |
1612 | ret |= _init_main_clk(oh); |
1613 | ret |= _init_interface_clks(oh); | |
1614 | ret |= _init_opt_clks(oh); | |
1615 | ||
f5c1f84b BC |
1616 | if (!ret) |
1617 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1618 | else |
1619 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1620 | |
09c35f2f | 1621 | return ret; |
63c85238 PW |
1622 | } |
1623 | ||
5365efbe | 1624 | /** |
cc1226e7 | 1625 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1626 | * @oh: struct omap_hwmod * |
1627 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1628 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1629 | * |
1630 | * Return the bit position of the reset line that match the | |
1631 | * input name. Return -ENOENT if not found. | |
1632 | */ | |
a032d33b PW |
1633 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1634 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1635 | { |
1636 | int i; | |
1637 | ||
1638 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1639 | const char *rst_line = oh->rst_lines[i].name; | |
1640 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1641 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1642 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1643 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1644 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1645 | ohri->st_shift); | |
5365efbe | 1646 | |
cc1226e7 | 1647 | return 0; |
5365efbe BC |
1648 | } |
1649 | } | |
1650 | ||
1651 | return -ENOENT; | |
1652 | } | |
1653 | ||
1654 | /** | |
1655 | * _assert_hardreset - assert the HW reset line of submodules | |
1656 | * contained in the hwmod module. | |
1657 | * @oh: struct omap_hwmod * | |
1658 | * @name: name of the reset line to lookup and assert | |
1659 | * | |
b8249cf2 KH |
1660 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1661 | * reset line to be assert / deassert in order to enable fully the IP. | |
1662 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1663 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1664 | * along the return value from _lookup_hardreset() or the SoC's | |
1665 | * assert_hardreset code. | |
5365efbe BC |
1666 | */ |
1667 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1668 | { | |
cc1226e7 | 1669 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1670 | int ret = -EINVAL; |
5365efbe BC |
1671 | |
1672 | if (!oh) | |
1673 | return -EINVAL; | |
1674 | ||
b8249cf2 KH |
1675 | if (!soc_ops.assert_hardreset) |
1676 | return -ENOSYS; | |
1677 | ||
cc1226e7 | 1678 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1679 | if (ret < 0) |
cc1226e7 | 1680 | return ret; |
5365efbe | 1681 | |
b8249cf2 KH |
1682 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1683 | ||
1684 | return ret; | |
5365efbe BC |
1685 | } |
1686 | ||
1687 | /** | |
1688 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1689 | * in the hwmod module. | |
1690 | * @oh: struct omap_hwmod * | |
1691 | * @name: name of the reset line to look up and deassert | |
1692 | * | |
b8249cf2 KH |
1693 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1694 | * reset line to be assert / deassert in order to enable fully the IP. | |
1695 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1696 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1697 | * along the return value from _lookup_hardreset() or the SoC's | |
1698 | * deassert_hardreset code. | |
5365efbe BC |
1699 | */ |
1700 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1701 | { | |
cc1226e7 | 1702 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1703 | int ret = -EINVAL; |
e8e96dff | 1704 | int hwsup = 0; |
5365efbe BC |
1705 | |
1706 | if (!oh) | |
1707 | return -EINVAL; | |
1708 | ||
b8249cf2 KH |
1709 | if (!soc_ops.deassert_hardreset) |
1710 | return -ENOSYS; | |
1711 | ||
cc1226e7 | 1712 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1713 | if (ret < 0) |
cc1226e7 | 1714 | return ret; |
5365efbe | 1715 | |
e8e96dff ORL |
1716 | if (oh->clkdm) { |
1717 | /* | |
1718 | * A clockdomain must be in SW_SUP otherwise reset | |
1719 | * might not be completed. The clockdomain can be set | |
1720 | * in HW_AUTO only when the module become ready. | |
1721 | */ | |
1722 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1723 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1724 | if (ret) { | |
1725 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1726 | oh->name, oh->clkdm->name, ret); | |
1727 | return ret; | |
1728 | } | |
1729 | } | |
1730 | ||
1731 | _enable_clocks(oh); | |
1732 | if (soc_ops.enable_module) | |
1733 | soc_ops.enable_module(oh); | |
1734 | ||
b8249cf2 | 1735 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1736 | |
1737 | if (soc_ops.disable_module) | |
1738 | soc_ops.disable_module(oh); | |
1739 | _disable_clocks(oh); | |
1740 | ||
cc1226e7 | 1741 | if (ret == -EBUSY) |
5365efbe BC |
1742 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1743 | ||
e8e96dff ORL |
1744 | if (!ret) { |
1745 | /* | |
1746 | * Set the clockdomain to HW_AUTO, assuming that the | |
1747 | * previous state was HW_AUTO. | |
1748 | */ | |
1749 | if (oh->clkdm && hwsup) | |
1750 | clkdm_allow_idle(oh->clkdm); | |
1751 | } else { | |
1752 | if (oh->clkdm) | |
1753 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1754 | } | |
1755 | ||
cc1226e7 | 1756 | return ret; |
5365efbe BC |
1757 | } |
1758 | ||
1759 | /** | |
1760 | * _read_hardreset - read the HW reset line state of submodules | |
1761 | * contained in the hwmod module | |
1762 | * @oh: struct omap_hwmod * | |
1763 | * @name: name of the reset line to look up and read | |
1764 | * | |
b8249cf2 KH |
1765 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1766 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1767 | * status on the currently-booted SoC, or passes along the return | |
1768 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1769 | * code. | |
5365efbe BC |
1770 | */ |
1771 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1772 | { | |
cc1226e7 | 1773 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1774 | int ret = -EINVAL; |
5365efbe BC |
1775 | |
1776 | if (!oh) | |
1777 | return -EINVAL; | |
1778 | ||
b8249cf2 KH |
1779 | if (!soc_ops.is_hardreset_asserted) |
1780 | return -ENOSYS; | |
1781 | ||
cc1226e7 | 1782 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1783 | if (ret < 0) |
cc1226e7 | 1784 | return ret; |
5365efbe | 1785 | |
b8249cf2 | 1786 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1787 | } |
1788 | ||
747834ab | 1789 | /** |
eb05f691 | 1790 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1791 | * @oh: struct omap_hwmod * |
1792 | * | |
eb05f691 ORL |
1793 | * If all hardreset lines associated with @oh are asserted, then return true. |
1794 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1795 | * associated with @oh are asserted, then return false. | |
747834ab | 1796 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1797 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1798 | */ |
eb05f691 | 1799 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1800 | { |
eb05f691 | 1801 | int i, rst_cnt = 0; |
747834ab PW |
1802 | |
1803 | if (oh->rst_lines_cnt == 0) | |
1804 | return false; | |
1805 | ||
1806 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1807 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1808 | rst_cnt++; |
1809 | ||
1810 | if (oh->rst_lines_cnt == rst_cnt) | |
1811 | return true; | |
747834ab PW |
1812 | |
1813 | return false; | |
1814 | } | |
1815 | ||
e9332b6e PW |
1816 | /** |
1817 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1818 | * hard-reset | |
1819 | * @oh: struct omap_hwmod * | |
1820 | * | |
1821 | * If any hardreset lines associated with @oh are asserted, then | |
1822 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1823 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1824 | * This function is used to avoid executing some parts of the IP block | |
1825 | * enable/disable sequence if any hardreset line is set. | |
1826 | */ | |
1827 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1828 | { | |
1829 | int rst_cnt = 0; | |
1830 | int i; | |
1831 | ||
1832 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1833 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1834 | rst_cnt++; | |
1835 | ||
1836 | return (rst_cnt) ? true : false; | |
1837 | } | |
1838 | ||
747834ab PW |
1839 | /** |
1840 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1841 | * @oh: struct omap_hwmod * | |
1842 | * | |
1843 | * Disable the PRCM module mode related to the hwmod @oh. | |
1844 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1845 | */ | |
1846 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1847 | { | |
1848 | int v; | |
1849 | ||
747834ab PW |
1850 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1851 | return -EINVAL; | |
1852 | ||
eb05f691 ORL |
1853 | /* |
1854 | * Since integration code might still be doing something, only | |
1855 | * disable if all lines are under hardreset. | |
1856 | */ | |
e9332b6e | 1857 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1858 | return 0; |
1859 | ||
747834ab PW |
1860 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1861 | ||
1862 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1863 | oh->clkdm->cm_inst, | |
1864 | oh->clkdm->clkdm_offs, | |
1865 | oh->prcm.omap4.clkctrl_offs); | |
1866 | ||
747834ab PW |
1867 | v = _omap4_wait_target_disable(oh); |
1868 | if (v) | |
1869 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1870 | oh->name); | |
1871 | ||
1872 | return 0; | |
1873 | } | |
1874 | ||
1688bf19 VH |
1875 | /** |
1876 | * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX | |
1877 | * @oh: struct omap_hwmod * | |
1878 | * | |
1879 | * Disable the PRCM module mode related to the hwmod @oh. | |
1880 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1881 | */ | |
1882 | static int _am33xx_disable_module(struct omap_hwmod *oh) | |
1883 | { | |
1884 | int v; | |
1885 | ||
1886 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1887 | return -EINVAL; | |
1888 | ||
1889 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1890 | ||
e9332b6e PW |
1891 | if (_are_any_hardreset_lines_asserted(oh)) |
1892 | return 0; | |
1893 | ||
1688bf19 VH |
1894 | am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, |
1895 | oh->prcm.omap4.clkctrl_offs); | |
1896 | ||
1688bf19 VH |
1897 | v = _am33xx_wait_target_disable(oh); |
1898 | if (v) | |
1899 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1900 | oh->name); | |
1901 | ||
1902 | return 0; | |
1903 | } | |
1904 | ||
63c85238 | 1905 | /** |
bd36179e | 1906 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1907 | * @oh: struct omap_hwmod * |
1908 | * | |
1909 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1910 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1911 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1912 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1913 | * |
1914 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1915 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1916 | * use the SYSCONFIG softreset bit to provide the status. |
1917 | * | |
bd36179e PW |
1918 | * Note that some IP like McBSP do have reset control but don't have |
1919 | * reset status. | |
63c85238 | 1920 | */ |
bd36179e | 1921 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1922 | { |
613ad0e9 | 1923 | u32 v; |
6f8b7ff5 | 1924 | int c = 0; |
96835af9 | 1925 | int ret = 0; |
63c85238 | 1926 | |
43b40992 | 1927 | if (!oh->class->sysc || |
2cb06814 | 1928 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1929 | return -ENOENT; |
63c85238 PW |
1930 | |
1931 | /* clocks must be on for this operation */ | |
1932 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1933 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1934 | oh->name); | |
63c85238 PW |
1935 | return -EINVAL; |
1936 | } | |
1937 | ||
96835af9 BC |
1938 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1939 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1940 | _enable_optional_clocks(oh); | |
1941 | ||
bd36179e | 1942 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1943 | |
1944 | v = oh->_sysc_cache; | |
96835af9 BC |
1945 | ret = _set_softreset(oh, &v); |
1946 | if (ret) | |
1947 | goto dis_opt_clks; | |
313a76ee | 1948 | |
63c85238 PW |
1949 | _write_sysconfig(v, oh); |
1950 | ||
d99de7f5 FGL |
1951 | if (oh->class->sysc->srst_udelay) |
1952 | udelay(oh->class->sysc->srst_udelay); | |
1953 | ||
613ad0e9 | 1954 | c = _wait_softreset_complete(oh); |
01142519 | 1955 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
76e5589e BC |
1956 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1957 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1958 | ret = -ETIMEDOUT; |
1959 | goto dis_opt_clks; | |
1960 | } else { | |
5365efbe | 1961 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1962 | } |
1963 | ||
1964 | ret = _clear_softreset(oh, &v); | |
1965 | if (ret) | |
1966 | goto dis_opt_clks; | |
1967 | ||
1968 | _write_sysconfig(v, oh); | |
63c85238 PW |
1969 | |
1970 | /* | |
1971 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1972 | * _wait_target_ready() or _reset() | |
1973 | */ | |
1974 | ||
96835af9 BC |
1975 | dis_opt_clks: |
1976 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1977 | _disable_optional_clocks(oh); | |
1978 | ||
1979 | return ret; | |
63c85238 PW |
1980 | } |
1981 | ||
bd36179e PW |
1982 | /** |
1983 | * _reset - reset an omap_hwmod | |
1984 | * @oh: struct omap_hwmod * | |
1985 | * | |
30e105c0 PW |
1986 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1987 | * function pointer defined, then call it to reset the IP block, and | |
1988 | * pass along its return value to the caller. Otherwise, if the IP | |
1989 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1990 | * associated with it, call a function to reset the IP block via that | |
1991 | * method, and pass along the return value to the caller. Finally, if | |
1992 | * the IP block has some hardreset lines associated with it, assert | |
1993 | * all of those, but do _not_ deassert them. (This is because driver | |
1994 | * authors have expressed an apparent requirement to control the | |
1995 | * deassertion of the hardreset lines themselves.) | |
1996 | * | |
1997 | * The default software reset mechanism for most OMAP IP blocks is | |
1998 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1999 | * hwmods cannot be reset via this method. Some are not targets and | |
2000 | * therefore have no OCP header registers to access. Others (like the | |
2001 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
2002 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
2003 | * omap_hwmod_class .reset function pointer. |
2004 | * | |
2005 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
2006 | * does not prevent idling of the system. This is necessary for cases | |
2007 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
2008 | * kernel without disabling dma. | |
2009 | * | |
2010 | * Passes along the return value from either _ocp_softreset() or the | |
2011 | * custom reset function - these must return -EINVAL if the hwmod | |
2012 | * cannot be reset this way or if the hwmod is in the wrong state, | |
2013 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
2014 | */ |
2015 | static int _reset(struct omap_hwmod *oh) | |
2016 | { | |
30e105c0 | 2017 | int i, r; |
bd36179e PW |
2018 | |
2019 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
2020 | ||
30e105c0 PW |
2021 | if (oh->class->reset) { |
2022 | r = oh->class->reset(oh); | |
2023 | } else { | |
2024 | if (oh->rst_lines_cnt > 0) { | |
2025 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
2026 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
2027 | return 0; | |
2028 | } else { | |
2029 | r = _ocp_softreset(oh); | |
2030 | if (r == -ENOENT) | |
2031 | r = 0; | |
2032 | } | |
2033 | } | |
2034 | ||
6668546f KVA |
2035 | _set_dmadisable(oh); |
2036 | ||
9c8b0ec7 | 2037 | /* |
30e105c0 PW |
2038 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
2039 | * softreset. The _enable() function should be split to avoid | |
2040 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 2041 | */ |
2800852a RN |
2042 | if (oh->class->sysc) { |
2043 | _update_sysc_cache(oh); | |
2044 | _enable_sysc(oh); | |
2045 | } | |
2046 | ||
30e105c0 | 2047 | return r; |
bd36179e PW |
2048 | } |
2049 | ||
5165882a VB |
2050 | /** |
2051 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
2052 | * | |
2053 | * Call the appropriate PRM function to clear any logged I/O chain | |
2054 | * wakeups and to reconfigure the chain. This apparently needs to be | |
2055 | * done upon every mux change. Since hwmods can be concurrently | |
2056 | * enabled and idled, hold a spinlock around the I/O chain | |
2057 | * reconfiguration sequence. No return value. | |
2058 | * | |
2059 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
2060 | * as the PRM infrastructure should abstract this. | |
2061 | */ | |
2062 | static void _reconfigure_io_chain(void) | |
2063 | { | |
2064 | unsigned long flags; | |
2065 | ||
2066 | spin_lock_irqsave(&io_chain_lock, flags); | |
2067 | ||
2068 | if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) | |
2069 | omap3xxx_prm_reconfigure_io_chain(); | |
2070 | else if (cpu_is_omap44xx()) | |
2071 | omap44xx_prm_reconfigure_io_chain(); | |
2072 | ||
2073 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
2074 | } | |
2075 | ||
e6d3a8b0 RN |
2076 | /** |
2077 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
2078 | * hwmod context was lost, and clear hardware context loss reg | |
2079 | * @oh: hwmod to check for context loss | |
2080 | * | |
2081 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
2082 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
2083 | * bits. No return value. | |
2084 | */ | |
2085 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
2086 | { | |
2087 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
2088 | return; | |
2089 | ||
2090 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2091 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2092 | oh->prcm.omap4.context_offs)) | |
2093 | return; | |
2094 | ||
2095 | oh->prcm.omap4.context_lost_counter++; | |
2096 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2097 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2098 | oh->prcm.omap4.context_offs); | |
2099 | } | |
2100 | ||
2101 | /** | |
2102 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
2103 | * @oh: hwmod to get context loss counter for | |
2104 | * | |
2105 | * Returns the in-memory context loss counter for a hwmod. | |
2106 | */ | |
2107 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
2108 | { | |
2109 | return oh->prcm.omap4.context_lost_counter; | |
2110 | } | |
2111 | ||
6d266f63 PW |
2112 | /** |
2113 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
2114 | * @oh: struct omap_hwmod * | |
2115 | * | |
2116 | * Some IP blocks (such as AESS) require some additional programming | |
2117 | * after enable before they can enter idle. If a function pointer to | |
2118 | * do so is present in the hwmod data, then call it and pass along the | |
2119 | * return value; otherwise, return 0. | |
2120 | */ | |
0f497039 | 2121 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
2122 | { |
2123 | if (!oh->class->enable_preprogram) | |
2124 | return 0; | |
2125 | ||
2126 | return oh->class->enable_preprogram(oh); | |
2127 | } | |
2128 | ||
63c85238 | 2129 | /** |
dc6d1cda | 2130 | * _enable - enable an omap_hwmod |
63c85238 PW |
2131 | * @oh: struct omap_hwmod * |
2132 | * | |
2133 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
2134 | * register target. Returns -EINVAL if the hwmod is in the wrong |
2135 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 2136 | */ |
dc6d1cda | 2137 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 2138 | { |
747834ab | 2139 | int r; |
665d0013 | 2140 | int hwsup = 0; |
63c85238 | 2141 | |
34617e2a BC |
2142 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
2143 | ||
aacf0941 | 2144 | /* |
64813c3f PW |
2145 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
2146 | * state at init. Now that someone is really trying to enable | |
2147 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
2148 | */ |
2149 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
2150 | /* | |
2151 | * If the caller has mux data populated, do the mux'ing | |
2152 | * which wouldn't have been done as part of the _enable() | |
2153 | * done during setup. | |
2154 | */ | |
2155 | if (oh->mux) | |
2156 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
2157 | ||
2158 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
2159 | return 0; | |
2160 | } | |
2161 | ||
63c85238 PW |
2162 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
2163 | oh->_state != _HWMOD_STATE_IDLE && | |
2164 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2165 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2166 | oh->name); | |
63c85238 PW |
2167 | return -EINVAL; |
2168 | } | |
2169 | ||
31f62866 | 2170 | /* |
eb05f691 | 2171 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2172 | * asserted, we let integration code associated with that |
2173 | * block handle the enable. We've received very little | |
2174 | * information on what those driver authors need, and until | |
2175 | * detailed information is provided and the driver code is | |
2176 | * posted to the public lists, this is probably the best we | |
2177 | * can do. | |
31f62866 | 2178 | */ |
eb05f691 | 2179 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2180 | return 0; |
63c85238 | 2181 | |
665d0013 RN |
2182 | /* Mux pins for device runtime if populated */ |
2183 | if (oh->mux && (!oh->mux->enabled || | |
2184 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2185 | oh->mux->pads_dynamic))) { |
665d0013 | 2186 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a VB |
2187 | _reconfigure_io_chain(); |
2188 | } | |
665d0013 RN |
2189 | |
2190 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2191 | |
665d0013 RN |
2192 | if (oh->clkdm) { |
2193 | /* | |
2194 | * A clockdomain must be in SW_SUP before enabling | |
2195 | * completely the module. The clockdomain can be set | |
2196 | * in HW_AUTO only when the module become ready. | |
2197 | */ | |
b71c7217 PW |
2198 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2199 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2200 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2201 | if (r) { | |
2202 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2203 | oh->name, oh->clkdm->name, r); | |
2204 | return r; | |
2205 | } | |
34617e2a | 2206 | } |
665d0013 RN |
2207 | |
2208 | _enable_clocks(oh); | |
9ebfd285 KH |
2209 | if (soc_ops.enable_module) |
2210 | soc_ops.enable_module(oh); | |
fa200222 | 2211 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2212 | cpu_idle_poll_ctrl(true); |
34617e2a | 2213 | |
e6d3a8b0 RN |
2214 | if (soc_ops.update_context_lost) |
2215 | soc_ops.update_context_lost(oh); | |
2216 | ||
8f6aa8ee KH |
2217 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2218 | -EINVAL; | |
665d0013 RN |
2219 | if (!r) { |
2220 | /* | |
2221 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2222 | * assuming that the previous state was HW_AUTO | |
2223 | */ | |
2224 | if (oh->clkdm && hwsup) | |
2225 | clkdm_allow_idle(oh->clkdm); | |
2226 | ||
2227 | oh->_state = _HWMOD_STATE_ENABLED; | |
2228 | ||
2229 | /* Access the sysconfig only if the target is ready */ | |
2230 | if (oh->class->sysc) { | |
2231 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2232 | _update_sysc_cache(oh); | |
2233 | _enable_sysc(oh); | |
2234 | } | |
6d266f63 | 2235 | r = _enable_preprogram(oh); |
665d0013 | 2236 | } else { |
2577a4a6 PW |
2237 | if (soc_ops.disable_module) |
2238 | soc_ops.disable_module(oh); | |
665d0013 RN |
2239 | _disable_clocks(oh); |
2240 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2241 | oh->name, r); | |
34617e2a | 2242 | |
665d0013 RN |
2243 | if (oh->clkdm) |
2244 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2245 | } |
2246 | ||
63c85238 PW |
2247 | return r; |
2248 | } | |
2249 | ||
2250 | /** | |
dc6d1cda | 2251 | * _idle - idle an omap_hwmod |
63c85238 PW |
2252 | * @oh: struct omap_hwmod * |
2253 | * | |
2254 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2255 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2256 | * state or returns 0. | |
63c85238 | 2257 | */ |
dc6d1cda | 2258 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2259 | { |
34617e2a BC |
2260 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2261 | ||
63c85238 | 2262 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2263 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2264 | oh->name); | |
63c85238 PW |
2265 | return -EINVAL; |
2266 | } | |
2267 | ||
eb05f691 | 2268 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2269 | return 0; |
2270 | ||
43b40992 | 2271 | if (oh->class->sysc) |
74ff3a68 | 2272 | _idle_sysc(oh); |
63c85238 | 2273 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2274 | |
fa200222 | 2275 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2276 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2277 | if (soc_ops.disable_module) |
2278 | soc_ops.disable_module(oh); | |
bfc141e3 | 2279 | |
45c38252 BC |
2280 | /* |
2281 | * The module must be in idle mode before disabling any parents | |
2282 | * clocks. Otherwise, the parent clock might be disabled before | |
2283 | * the module transition is done, and thus will prevent the | |
2284 | * transition to complete properly. | |
2285 | */ | |
2286 | _disable_clocks(oh); | |
665d0013 RN |
2287 | if (oh->clkdm) |
2288 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2289 | |
8d9af88f | 2290 | /* Mux pins for device idle if populated */ |
5165882a | 2291 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2292 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a VB |
2293 | _reconfigure_io_chain(); |
2294 | } | |
8d9af88f | 2295 | |
63c85238 PW |
2296 | oh->_state = _HWMOD_STATE_IDLE; |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * _shutdown - shutdown an omap_hwmod | |
2303 | * @oh: struct omap_hwmod * | |
2304 | * | |
2305 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2306 | * used for the hwmod is removed or unloaded or if the driver is not | |
2307 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2308 | * state or returns 0. | |
2309 | */ | |
2310 | static int _shutdown(struct omap_hwmod *oh) | |
2311 | { | |
9c8b0ec7 | 2312 | int ret, i; |
e4dc8f50 PW |
2313 | u8 prev_state; |
2314 | ||
63c85238 PW |
2315 | if (oh->_state != _HWMOD_STATE_IDLE && |
2316 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2317 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2318 | oh->name); | |
63c85238 PW |
2319 | return -EINVAL; |
2320 | } | |
2321 | ||
eb05f691 | 2322 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2323 | return 0; |
2324 | ||
63c85238 PW |
2325 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2326 | ||
e4dc8f50 PW |
2327 | if (oh->class->pre_shutdown) { |
2328 | prev_state = oh->_state; | |
2329 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2330 | _enable(oh); |
e4dc8f50 PW |
2331 | ret = oh->class->pre_shutdown(oh); |
2332 | if (ret) { | |
2333 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2334 | _idle(oh); |
e4dc8f50 PW |
2335 | return ret; |
2336 | } | |
2337 | } | |
2338 | ||
6481c73c MV |
2339 | if (oh->class->sysc) { |
2340 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2341 | _enable(oh); | |
74ff3a68 | 2342 | _shutdown_sysc(oh); |
6481c73c | 2343 | } |
5365efbe | 2344 | |
3827f949 BC |
2345 | /* clocks and deps are already disabled in idle */ |
2346 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2347 | _del_initiator_dep(oh, mpu_oh); | |
2348 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2349 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2350 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2351 | if (soc_ops.disable_module) |
2352 | soc_ops.disable_module(oh); | |
45c38252 | 2353 | _disable_clocks(oh); |
665d0013 RN |
2354 | if (oh->clkdm) |
2355 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2356 | } |
63c85238 PW |
2357 | /* XXX Should this code also force-disable the optional clocks? */ |
2358 | ||
9c8b0ec7 PW |
2359 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2360 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2361 | |
8d9af88f TL |
2362 | /* Mux pins to safe mode or use populated off mode values */ |
2363 | if (oh->mux) | |
2364 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2365 | |
2366 | oh->_state = _HWMOD_STATE_DISABLED; | |
2367 | ||
2368 | return 0; | |
2369 | } | |
2370 | ||
5e863c56 TL |
2371 | static int of_dev_find_hwmod(struct device_node *np, |
2372 | struct omap_hwmod *oh) | |
2373 | { | |
2374 | int count, i, res; | |
2375 | const char *p; | |
2376 | ||
2377 | count = of_property_count_strings(np, "ti,hwmods"); | |
2378 | if (count < 1) | |
2379 | return -ENODEV; | |
2380 | ||
2381 | for (i = 0; i < count; i++) { | |
2382 | res = of_property_read_string_index(np, "ti,hwmods", | |
2383 | i, &p); | |
2384 | if (res) | |
2385 | continue; | |
2386 | if (!strcmp(p, oh->name)) { | |
2387 | pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n", | |
2388 | np->name, i, oh->name); | |
2389 | return i; | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | return -ENODEV; | |
2394 | } | |
2395 | ||
079abade SS |
2396 | /** |
2397 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2398 | * @np: struct device_node * | |
2399 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2400 | * @index: index of the entry found |
2401 | * @found: struct device_node * found or NULL | |
079abade SS |
2402 | * |
2403 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2404 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2405 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2406 | */ |
5e863c56 TL |
2407 | static int of_dev_hwmod_lookup(struct device_node *np, |
2408 | struct omap_hwmod *oh, | |
2409 | int *index, | |
2410 | struct device_node **found) | |
079abade | 2411 | { |
5e863c56 TL |
2412 | struct device_node *np0 = NULL; |
2413 | int res; | |
2414 | ||
2415 | res = of_dev_find_hwmod(np, oh); | |
2416 | if (res >= 0) { | |
2417 | *found = np; | |
2418 | *index = res; | |
2419 | return 0; | |
2420 | } | |
079abade SS |
2421 | |
2422 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2423 | struct device_node *fc; |
2424 | int i; | |
2425 | ||
2426 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2427 | if (res == 0) { | |
2428 | *found = fc; | |
2429 | *index = i; | |
2430 | return 0; | |
079abade SS |
2431 | } |
2432 | } | |
5e863c56 TL |
2433 | |
2434 | *found = NULL; | |
2435 | *index = 0; | |
2436 | ||
2437 | return -ENODEV; | |
079abade SS |
2438 | } |
2439 | ||
381d033a PW |
2440 | /** |
2441 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2442 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2443 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2444 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2445 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2446 | * |
2447 | * Cache the virtual address used by the MPU to access this IP block's | |
2448 | * registers. This address is needed early so the OCP registers that | |
2449 | * are part of the device's address space can be ioremapped properly. | |
6423d6df SA |
2450 | * |
2451 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and | |
2452 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2453 | */ |
f92d9597 | 2454 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2455 | int index, struct device_node *np) |
381d033a | 2456 | { |
c9aafd23 | 2457 | struct omap_hwmod_addr_space *mem; |
079abade | 2458 | void __iomem *va_start = NULL; |
c9aafd23 PW |
2459 | |
2460 | if (!oh) | |
6423d6df | 2461 | return -EINVAL; |
c9aafd23 | 2462 | |
2221b5cd PW |
2463 | _save_mpu_port_index(oh); |
2464 | ||
381d033a | 2465 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2466 | return -ENXIO; |
381d033a | 2467 | |
c9aafd23 PW |
2468 | mem = _find_mpu_rt_addr_space(oh); |
2469 | if (!mem) { | |
2470 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2471 | oh->name); | |
079abade SS |
2472 | |
2473 | /* Extract the IO space from device tree blob */ | |
f92d9597 | 2474 | if (!np) |
6423d6df | 2475 | return -ENXIO; |
079abade | 2476 | |
5e863c56 | 2477 | va_start = of_iomap(np, index + oh->mpu_rt_idx); |
079abade SS |
2478 | } else { |
2479 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
c9aafd23 PW |
2480 | } |
2481 | ||
c9aafd23 | 2482 | if (!va_start) { |
5e863c56 TL |
2483 | if (mem) |
2484 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2485 | else | |
2486 | pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n", | |
2487 | oh->name, index, np->full_name); | |
6423d6df | 2488 | return -ENXIO; |
c9aafd23 PW |
2489 | } |
2490 | ||
2491 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2492 | oh->name, va_start); | |
2493 | ||
2494 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2495 | return 0; |
381d033a PW |
2496 | } |
2497 | ||
2498 | /** | |
2499 | * _init - initialize internal data for the hwmod @oh | |
2500 | * @oh: struct omap_hwmod * | |
2501 | * @n: (unused) | |
2502 | * | |
2503 | * Look up the clocks and the address space used by the MPU to access | |
2504 | * registers belonging to the hwmod @oh. @oh must already be | |
2505 | * registered at this point. This is the first of two phases for | |
2506 | * hwmod initialization. Code called here does not touch any hardware | |
2507 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2508 | * upon success or if the hwmod isn't registered or if the hwmod's |
2509 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2510 | */ |
2511 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2512 | { | |
5e863c56 | 2513 | int r, index; |
f92d9597 | 2514 | struct device_node *np = NULL; |
381d033a PW |
2515 | |
2516 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2517 | return 0; | |
2518 | ||
5e863c56 TL |
2519 | if (of_have_populated_dt()) { |
2520 | struct device_node *bus; | |
2521 | ||
2522 | bus = of_find_node_by_name(NULL, "ocp"); | |
2523 | if (!bus) | |
2524 | return -ENODEV; | |
2525 | ||
2526 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); | |
2527 | if (r) | |
2528 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2529 | else if (np && index) | |
2530 | pr_warn("omap_hwmod: %s using broken dt data from %s\n", | |
2531 | oh->name, np->name); | |
2532 | } | |
f92d9597 | 2533 | |
6423d6df | 2534 | if (oh->class->sysc) { |
5e863c56 | 2535 | r = _init_mpu_rt_base(oh, NULL, index, np); |
6423d6df SA |
2536 | if (r < 0) { |
2537 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2538 | oh->name); | |
2539 | return 0; | |
2540 | } | |
2541 | } | |
381d033a PW |
2542 | |
2543 | r = _init_clocks(oh, NULL); | |
c48cd659 | 2544 | if (r < 0) { |
381d033a PW |
2545 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2546 | return -EINVAL; | |
2547 | } | |
2548 | ||
3d36ad7e | 2549 | if (np) { |
f92d9597 RN |
2550 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) |
2551 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2552 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2553 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
3d36ad7e | 2554 | } |
f92d9597 | 2555 | |
381d033a PW |
2556 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2557 | ||
2558 | return 0; | |
2559 | } | |
2560 | ||
63c85238 | 2561 | /** |
64813c3f | 2562 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2563 | * @oh: struct omap_hwmod * |
2564 | * | |
64813c3f PW |
2565 | * Set up the module's interface clocks. XXX This function is still mostly |
2566 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2567 | * the clock code. No return value. | |
63c85238 | 2568 | */ |
64813c3f | 2569 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2570 | { |
5d95dde7 | 2571 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2572 | struct list_head *p; |
5d95dde7 | 2573 | int i = 0; |
381d033a | 2574 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2575 | return; |
48d54f3f | 2576 | |
11cd4b94 | 2577 | p = oh->slave_ports.next; |
63c85238 | 2578 | |
5d95dde7 | 2579 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2580 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2581 | if (!os->_clk) |
64813c3f | 2582 | continue; |
63c85238 | 2583 | |
64813c3f PW |
2584 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2585 | /* XXX omap_iclk_deny_idle(c); */ | |
2586 | } else { | |
2587 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2588 | clk_enable(os->_clk); |
63c85238 PW |
2589 | } |
2590 | } | |
2591 | ||
64813c3f PW |
2592 | return; |
2593 | } | |
2594 | ||
2595 | /** | |
2596 | * _setup_reset - reset an IP block during the setup process | |
2597 | * @oh: struct omap_hwmod * | |
2598 | * | |
2599 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2600 | * process. The IP block is first enabled so it can be successfully | |
2601 | * reset. Returns 0 upon success or a negative error code upon | |
2602 | * failure. | |
2603 | */ | |
2604 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2605 | { | |
2606 | int r; | |
2607 | ||
2608 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2609 | return -EINVAL; | |
63c85238 | 2610 | |
5fb3d522 PW |
2611 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2612 | return -EPERM; | |
2613 | ||
747834ab PW |
2614 | if (oh->rst_lines_cnt == 0) { |
2615 | r = _enable(oh); | |
2616 | if (r) { | |
2617 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2618 | oh->name, oh->_state); | |
2619 | return -EINVAL; | |
2620 | } | |
9a23dfe1 | 2621 | } |
63c85238 | 2622 | |
2800852a | 2623 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2624 | r = _reset(oh); |
2625 | ||
2626 | return r; | |
2627 | } | |
2628 | ||
2629 | /** | |
2630 | * _setup_postsetup - transition to the appropriate state after _setup | |
2631 | * @oh: struct omap_hwmod * | |
2632 | * | |
2633 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2634 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2635 | * this function is called at the end of _setup().) The postsetup | |
2636 | * state for an IP block can be changed by calling | |
2637 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2638 | * before one of the omap_hwmod_setup*() functions are called for the | |
2639 | * IP block. | |
2640 | * | |
2641 | * The IP block stays in this state until a PM runtime-based driver is | |
2642 | * loaded for that IP block. A post-setup state of IDLE is | |
2643 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2644 | * drivers, since those drivers are able to enable the IP block. A | |
2645 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2646 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2647 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2648 | * included, since the WDTIMER starts running on reset and will reset | |
2649 | * the MPU if left active. | |
2650 | * | |
2651 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2652 | * drivers have been converted to use PM runtime, and all of the IP | |
2653 | * block data and interconnect data is available to the hwmod code, it | |
2654 | * should be possible to replace this mechanism with a "lazy reset" | |
2655 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2656 | * when the driver first probes, then all remaining IP blocks without | |
2657 | * drivers are either shut down or enabled after the drivers have | |
2658 | * loaded. However, this cannot take place until the above | |
2659 | * preconditions have been met, since otherwise the late reset code | |
2660 | * has no way of knowing which IP blocks are in use by drivers, and | |
2661 | * which ones are unused. | |
2662 | * | |
2663 | * No return value. | |
2664 | */ | |
2665 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2666 | { | |
2667 | u8 postsetup_state; | |
2668 | ||
2669 | if (oh->rst_lines_cnt > 0) | |
2670 | return; | |
76e5589e | 2671 | |
2092e5cc PW |
2672 | postsetup_state = oh->_postsetup_state; |
2673 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2674 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2675 | ||
2676 | /* | |
2677 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2678 | * it should be set by the core code as a runtime flag during startup | |
2679 | */ | |
2680 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2681 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2682 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2683 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2684 | } |
2092e5cc PW |
2685 | |
2686 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2687 | _idle(oh); |
2092e5cc PW |
2688 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2689 | _shutdown(oh); | |
2690 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2691 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2692 | oh->name, postsetup_state); | |
63c85238 | 2693 | |
64813c3f PW |
2694 | return; |
2695 | } | |
2696 | ||
2697 | /** | |
2698 | * _setup - prepare IP block hardware for use | |
2699 | * @oh: struct omap_hwmod * | |
2700 | * @n: (unused, pass NULL) | |
2701 | * | |
2702 | * Configure the IP block represented by @oh. This may include | |
2703 | * enabling the IP block, resetting it, and placing it into a | |
2704 | * post-setup state, depending on the type of IP block and applicable | |
2705 | * flags. IP blocks are reset to prevent any previous configuration | |
2706 | * by the bootloader or previous operating system from interfering | |
2707 | * with power management or other parts of the system. The reset can | |
2708 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2709 | * two phases for hwmod initialization. Code called here generally | |
2710 | * affects the IP block hardware, or system integration hardware | |
2711 | * associated with the IP block. Returns 0. | |
2712 | */ | |
2713 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2714 | { | |
2715 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2716 | return 0; | |
2717 | ||
2718 | _setup_iclk_autoidle(oh); | |
2719 | ||
2720 | if (!_setup_reset(oh)) | |
2721 | _setup_postsetup(oh); | |
2722 | ||
63c85238 PW |
2723 | return 0; |
2724 | } | |
2725 | ||
63c85238 | 2726 | /** |
0102b627 | 2727 | * _register - register a struct omap_hwmod |
63c85238 PW |
2728 | * @oh: struct omap_hwmod * |
2729 | * | |
43b40992 PW |
2730 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2731 | * already has been registered by the same name; -EINVAL if the | |
2732 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2733 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2734 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2735 | * success. | |
63c85238 PW |
2736 | * |
2737 | * XXX The data should be copied into bootmem, so the original data | |
2738 | * should be marked __initdata and freed after init. This would allow | |
2739 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2740 | * that the copy process would be relatively complex due to the large number | |
2741 | * of substructures. | |
2742 | */ | |
01592df9 | 2743 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2744 | { |
43b40992 PW |
2745 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2746 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2747 | return -EINVAL; |
2748 | ||
63c85238 PW |
2749 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2750 | ||
ce35b244 BC |
2751 | if (_lookup(oh->name)) |
2752 | return -EEXIST; | |
63c85238 | 2753 | |
63c85238 PW |
2754 | list_add_tail(&oh->node, &omap_hwmod_list); |
2755 | ||
2221b5cd PW |
2756 | INIT_LIST_HEAD(&oh->master_ports); |
2757 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2758 | spin_lock_init(&oh->_lock); |
2092e5cc | 2759 | |
63c85238 PW |
2760 | oh->_state = _HWMOD_STATE_REGISTERED; |
2761 | ||
569edd70 PW |
2762 | /* |
2763 | * XXX Rather than doing a strcmp(), this should test a flag | |
2764 | * set in the hwmod data, inserted by the autogenerator code. | |
2765 | */ | |
2766 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2767 | mpu_oh = oh; | |
63c85238 | 2768 | |
569edd70 | 2769 | return 0; |
63c85238 PW |
2770 | } |
2771 | ||
2221b5cd PW |
2772 | /** |
2773 | * _alloc_links - return allocated memory for hwmod links | |
2774 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2775 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2776 | * | |
2777 | * Return pointers to two struct omap_hwmod_link records, via the | |
2778 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2779 | * memory allocated as part of a large initial block, but if that has | |
2780 | * been exhausted, will allocate memory itself. Since ideally this | |
2781 | * second allocation path will never occur, the number of these | |
2782 | * 'supplemental' allocations will be logged when debugging is | |
2783 | * enabled. Returns 0. | |
2784 | */ | |
2785 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2786 | struct omap_hwmod_link **sl) | |
2787 | { | |
2788 | unsigned int sz; | |
2789 | ||
2790 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2791 | *ml = &linkspace[free_ls++]; | |
2792 | *sl = &linkspace[free_ls++]; | |
2793 | return 0; | |
2794 | } | |
2795 | ||
2796 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2797 | ||
2798 | *sl = NULL; | |
b6cb5bab | 2799 | *ml = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2800 | |
2801 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2802 | ||
2803 | ls_supp++; | |
2804 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2805 | ls_supp * LINKS_PER_OCP_IF); | |
2806 | ||
2807 | return 0; | |
2808 | }; | |
2809 | ||
2810 | /** | |
2811 | * _add_link - add an interconnect between two IP blocks | |
2812 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2813 | * | |
2814 | * Add struct omap_hwmod_link records connecting the master IP block | |
2815 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2816 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2817 | * preemption or SMP has been enabled, thus avoiding the need for | |
2818 | * locking in this code. Changes to this assumption will require | |
2819 | * additional locking. Returns 0. | |
2820 | */ | |
2821 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2822 | { | |
2823 | struct omap_hwmod_link *ml, *sl; | |
2824 | ||
2825 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2826 | oi->slave->name); | |
2827 | ||
2828 | _alloc_links(&ml, &sl); | |
2829 | ||
2830 | ml->ocp_if = oi; | |
2831 | INIT_LIST_HEAD(&ml->node); | |
2832 | list_add(&ml->node, &oi->master->master_ports); | |
2833 | oi->master->masters_cnt++; | |
2834 | ||
2835 | sl->ocp_if = oi; | |
2836 | INIT_LIST_HEAD(&sl->node); | |
2837 | list_add(&sl->node, &oi->slave->slave_ports); | |
2838 | oi->slave->slaves_cnt++; | |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | ||
2843 | /** | |
2844 | * _register_link - register a struct omap_hwmod_ocp_if | |
2845 | * @oi: struct omap_hwmod_ocp_if * | |
2846 | * | |
2847 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2848 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2849 | * record pointed to by @oi is missing required fields; or 0 upon | |
2850 | * success. | |
2851 | * | |
2852 | * XXX The data should be copied into bootmem, so the original data | |
2853 | * should be marked __initdata and freed after init. This would allow | |
2854 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2855 | */ | |
2856 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2857 | { | |
2858 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2859 | return -EINVAL; | |
2860 | ||
2861 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2862 | return -EEXIST; | |
2863 | ||
2864 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2865 | oi->master->name, oi->slave->name); | |
2866 | ||
2867 | /* | |
2868 | * Register the connected hwmods, if they haven't been | |
2869 | * registered already | |
2870 | */ | |
2871 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2872 | _register(oi->master); | |
2873 | ||
2874 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2875 | _register(oi->slave); | |
2876 | ||
2877 | _add_link(oi); | |
2878 | ||
2879 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2880 | ||
2881 | return 0; | |
2882 | } | |
2883 | ||
2884 | /** | |
2885 | * _alloc_linkspace - allocate large block of hwmod links | |
2886 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2887 | * | |
2888 | * Allocate a large block of struct omap_hwmod_link records. This | |
2889 | * improves boot time significantly by avoiding the need to allocate | |
2890 | * individual records one by one. If the number of records to | |
2891 | * allocate in the block hasn't been manually specified, this function | |
2892 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2893 | * and use that to determine the allocation size. For SoC families | |
2894 | * that require multiple list registrations, such as OMAP3xxx, this | |
2895 | * estimation process isn't optimal, so manual estimation is advised | |
2896 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2897 | * or 0 upon success. | |
2898 | */ | |
2899 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2900 | { | |
2901 | unsigned int i = 0; | |
2902 | unsigned int sz; | |
2903 | ||
2904 | if (linkspace) { | |
2905 | WARN(1, "linkspace already allocated\n"); | |
2906 | return -EEXIST; | |
2907 | } | |
2908 | ||
2909 | if (max_ls == 0) | |
2910 | while (ois[i++]) | |
2911 | max_ls += LINKS_PER_OCP_IF; | |
2912 | ||
2913 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2914 | ||
2915 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2916 | __func__, sz, max_ls); | |
2917 | ||
b6cb5bab | 2918 | linkspace = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2919 | |
2920 | return 0; | |
2921 | } | |
0102b627 | 2922 | |
8f6aa8ee KH |
2923 | /* Static functions intended only for use in soc_ops field function pointers */ |
2924 | ||
2925 | /** | |
ff4ae5d9 | 2926 | * _omap2xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2927 | * @oh: struct omap_hwmod * |
2928 | * | |
2929 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2930 | * does not have an IDLEST bit or if the module successfully leaves | |
2931 | * slave idle; otherwise, pass along the return value of the | |
2932 | * appropriate *_cm*_wait_module_ready() function. | |
2933 | */ | |
ff4ae5d9 | 2934 | static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2935 | { |
2936 | if (!oh) | |
2937 | return -EINVAL; | |
2938 | ||
2939 | if (oh->flags & HWMOD_NO_IDLEST) | |
2940 | return 0; | |
2941 | ||
2942 | if (!_find_mpu_rt_port(oh)) | |
2943 | return 0; | |
2944 | ||
2945 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2946 | ||
ff4ae5d9 PW |
2947 | return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, |
2948 | oh->prcm.omap2.idlest_reg_id, | |
2949 | oh->prcm.omap2.idlest_idle_bit); | |
2950 | } | |
2951 | ||
2952 | /** | |
2953 | * _omap3xxx_wait_target_ready - wait for a module to leave slave idle | |
2954 | * @oh: struct omap_hwmod * | |
2955 | * | |
2956 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2957 | * does not have an IDLEST bit or if the module successfully leaves | |
2958 | * slave idle; otherwise, pass along the return value of the | |
2959 | * appropriate *_cm*_wait_module_ready() function. | |
2960 | */ | |
2961 | static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh) | |
2962 | { | |
2963 | if (!oh) | |
2964 | return -EINVAL; | |
2965 | ||
2966 | if (oh->flags & HWMOD_NO_IDLEST) | |
2967 | return 0; | |
2968 | ||
2969 | if (!_find_mpu_rt_port(oh)) | |
2970 | return 0; | |
2971 | ||
2972 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2973 | ||
2974 | return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2975 | oh->prcm.omap2.idlest_reg_id, | |
2976 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2977 | } |
2978 | ||
2979 | /** | |
2980 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2981 | * @oh: struct omap_hwmod * | |
2982 | * | |
2983 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2984 | * does not have an IDLEST bit or if the module successfully leaves | |
2985 | * slave idle; otherwise, pass along the return value of the | |
2986 | * appropriate *_cm*_wait_module_ready() function. | |
2987 | */ | |
2988 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2989 | { | |
2b026d13 | 2990 | if (!oh) |
8f6aa8ee KH |
2991 | return -EINVAL; |
2992 | ||
2b026d13 | 2993 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2994 | return 0; |
2995 | ||
2996 | if (!_find_mpu_rt_port(oh)) | |
2997 | return 0; | |
2998 | ||
2999 | /* XXX check module SIDLEMODE, hardreset status */ | |
3000 | ||
3001 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
3002 | oh->clkdm->cm_inst, | |
3003 | oh->clkdm->clkdm_offs, | |
3004 | oh->prcm.omap4.clkctrl_offs); | |
3005 | } | |
3006 | ||
1688bf19 VH |
3007 | /** |
3008 | * _am33xx_wait_target_ready - wait for a module to leave slave idle | |
3009 | * @oh: struct omap_hwmod * | |
3010 | * | |
3011 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
3012 | * does not have an IDLEST bit or if the module successfully leaves | |
3013 | * slave idle; otherwise, pass along the return value of the | |
3014 | * appropriate *_cm*_wait_module_ready() function. | |
3015 | */ | |
3016 | static int _am33xx_wait_target_ready(struct omap_hwmod *oh) | |
3017 | { | |
3018 | if (!oh || !oh->clkdm) | |
3019 | return -EINVAL; | |
3020 | ||
3021 | if (oh->flags & HWMOD_NO_IDLEST) | |
3022 | return 0; | |
3023 | ||
3024 | if (!_find_mpu_rt_port(oh)) | |
3025 | return 0; | |
3026 | ||
3027 | /* XXX check module SIDLEMODE, hardreset status */ | |
3028 | ||
3029 | return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, | |
3030 | oh->clkdm->clkdm_offs, | |
3031 | oh->prcm.omap4.clkctrl_offs); | |
3032 | } | |
3033 | ||
b8249cf2 KH |
3034 | /** |
3035 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
3036 | * @oh: struct omap_hwmod * to assert hardreset | |
3037 | * @ohri: hardreset line data | |
3038 | * | |
3039 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
3040 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
3041 | * use as an soc_ops function pointer. Passes along the return value | |
3042 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
3043 | * for removal when the PRM code is moved into drivers/. | |
3044 | */ | |
3045 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
3046 | struct omap_hwmod_rst_info *ohri) | |
3047 | { | |
3048 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
3049 | ohri->rst_shift); | |
3050 | } | |
3051 | ||
3052 | /** | |
3053 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
3054 | * @oh: struct omap_hwmod * to deassert hardreset | |
3055 | * @ohri: hardreset line data | |
3056 | * | |
3057 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
3058 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
3059 | * use as an soc_ops function pointer. Passes along the return value | |
3060 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
3061 | * scheduled for removal when the PRM code is moved into drivers/. | |
3062 | */ | |
3063 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
3064 | struct omap_hwmod_rst_info *ohri) | |
3065 | { | |
3066 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
3067 | ohri->rst_shift, | |
3068 | ohri->st_shift); | |
3069 | } | |
3070 | ||
3071 | /** | |
3072 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
3073 | * @oh: struct omap_hwmod * to test hardreset | |
3074 | * @ohri: hardreset line data | |
3075 | * | |
3076 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
3077 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3078 | * intended for use as an soc_ops function pointer. Passes along the | |
3079 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
3080 | * function is scheduled for removal when the PRM code is moved into | |
3081 | * drivers/. | |
3082 | */ | |
3083 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
3084 | struct omap_hwmod_rst_info *ohri) | |
3085 | { | |
3086 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
3087 | ohri->st_shift); | |
3088 | } | |
3089 | ||
3090 | /** | |
3091 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
3092 | * @oh: struct omap_hwmod * to assert hardreset | |
3093 | * @ohri: hardreset line data | |
3094 | * | |
3095 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
3096 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3097 | * intended for use as an soc_ops function pointer. Passes along the | |
3098 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
3099 | * function is scheduled for removal when the PRM code is moved into | |
3100 | * drivers/. | |
3101 | */ | |
3102 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
3103 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 3104 | { |
07b3a139 PW |
3105 | if (!oh->clkdm) |
3106 | return -EINVAL; | |
3107 | ||
b8249cf2 KH |
3108 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
3109 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
3110 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3111 | oh->prcm.omap4.rstctrl_offs); | |
3112 | } | |
3113 | ||
3114 | /** | |
3115 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
3116 | * @oh: struct omap_hwmod * to deassert hardreset | |
3117 | * @ohri: hardreset line data | |
3118 | * | |
3119 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
3120 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3121 | * intended for use as an soc_ops function pointer. Passes along the | |
3122 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
3123 | * function is scheduled for removal when the PRM code is moved into | |
3124 | * drivers/. | |
3125 | */ | |
3126 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
3127 | struct omap_hwmod_rst_info *ohri) | |
3128 | { | |
07b3a139 PW |
3129 | if (!oh->clkdm) |
3130 | return -EINVAL; | |
3131 | ||
b8249cf2 KH |
3132 | if (ohri->st_shift) |
3133 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
3134 | oh->name, ohri->name); | |
3135 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
3136 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
3137 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3138 | oh->prcm.omap4.rstctrl_offs); | |
3139 | } | |
3140 | ||
3141 | /** | |
3142 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
3143 | * @oh: struct omap_hwmod * to test hardreset | |
3144 | * @ohri: hardreset line data | |
3145 | * | |
3146 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
3147 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
3148 | * Only intended for use as an soc_ops function pointer. Passes along | |
3149 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
3150 | * This function is scheduled for removal when the PRM code is moved | |
3151 | * into drivers/. | |
3152 | */ | |
3153 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
3154 | struct omap_hwmod_rst_info *ohri) | |
3155 | { | |
07b3a139 PW |
3156 | if (!oh->clkdm) |
3157 | return -EINVAL; | |
3158 | ||
b8249cf2 KH |
3159 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
3160 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
3161 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3162 | oh->prcm.omap4.rstctrl_offs); | |
3163 | } | |
3164 | ||
1688bf19 VH |
3165 | /** |
3166 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
3167 | * @oh: struct omap_hwmod * to assert hardreset | |
3168 | * @ohri: hardreset line data | |
3169 | * | |
3170 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
3171 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3172 | * intended for use as an soc_ops function pointer. Passes along the | |
3173 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
3174 | * function is scheduled for removal when the PRM code is moved into | |
3175 | * drivers/. | |
3176 | */ | |
3177 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
3178 | struct omap_hwmod_rst_info *ohri) | |
3179 | ||
3180 | { | |
3181 | return am33xx_prm_assert_hardreset(ohri->rst_shift, | |
3182 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3183 | oh->prcm.omap4.rstctrl_offs); | |
3184 | } | |
3185 | ||
3186 | /** | |
3187 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
3188 | * @oh: struct omap_hwmod * to deassert hardreset | |
3189 | * @ohri: hardreset line data | |
3190 | * | |
3191 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
3192 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3193 | * intended for use as an soc_ops function pointer. Passes along the | |
3194 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
3195 | * function is scheduled for removal when the PRM code is moved into | |
3196 | * drivers/. | |
3197 | */ | |
3198 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
3199 | struct omap_hwmod_rst_info *ohri) | |
3200 | { | |
1688bf19 | 3201 | return am33xx_prm_deassert_hardreset(ohri->rst_shift, |
3c06f1b8 | 3202 | ohri->st_shift, |
1688bf19 VH |
3203 | oh->clkdm->pwrdm.ptr->prcm_offs, |
3204 | oh->prcm.omap4.rstctrl_offs, | |
3205 | oh->prcm.omap4.rstst_offs); | |
3206 | } | |
3207 | ||
3208 | /** | |
3209 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
3210 | * @oh: struct omap_hwmod * to test hardreset | |
3211 | * @ohri: hardreset line data | |
3212 | * | |
3213 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
3214 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
3215 | * Only intended for use as an soc_ops function pointer. Passes along | |
3216 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
3217 | * This function is scheduled for removal when the PRM code is moved | |
3218 | * into drivers/. | |
3219 | */ | |
3220 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
3221 | struct omap_hwmod_rst_info *ohri) | |
3222 | { | |
3223 | return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, | |
3224 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3225 | oh->prcm.omap4.rstctrl_offs); | |
3226 | } | |
3227 | ||
0102b627 BC |
3228 | /* Public functions */ |
3229 | ||
3230 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
3231 | { | |
3232 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3233 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 3234 | else |
edfaf05c | 3235 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3236 | } |
3237 | ||
3238 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
3239 | { | |
3240 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3241 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 3242 | else |
edfaf05c | 3243 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3244 | } |
3245 | ||
6d3c55fd A |
3246 | /** |
3247 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
3248 | * @oh: struct omap_hwmod * | |
3249 | * | |
3250 | * This is a public function exposed to drivers. Some drivers may need to do | |
3251 | * some settings before and after resetting the device. Those drivers after | |
3252 | * doing the necessary settings could use this function to start a reset by | |
3253 | * setting the SYSCONFIG.SOFTRESET bit. | |
3254 | */ | |
3255 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3256 | { | |
3c55c1ba PW |
3257 | u32 v; |
3258 | int ret; | |
3259 | ||
3260 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3261 | return -EINVAL; |
3262 | ||
3c55c1ba PW |
3263 | v = oh->_sysc_cache; |
3264 | ret = _set_softreset(oh, &v); | |
3265 | if (ret) | |
3266 | goto error; | |
3267 | _write_sysconfig(v, oh); | |
3268 | ||
313a76ee RQ |
3269 | ret = _clear_softreset(oh, &v); |
3270 | if (ret) | |
3271 | goto error; | |
3272 | _write_sysconfig(v, oh); | |
3273 | ||
3c55c1ba PW |
3274 | error: |
3275 | return ret; | |
6d3c55fd A |
3276 | } |
3277 | ||
63c85238 PW |
3278 | /** |
3279 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3280 | * @name: name of the omap_hwmod to look up | |
3281 | * | |
3282 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3283 | * struct omap_hwmod *, or NULL upon error. | |
3284 | */ | |
3285 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3286 | { | |
3287 | struct omap_hwmod *oh; | |
3288 | ||
3289 | if (!name) | |
3290 | return NULL; | |
3291 | ||
63c85238 | 3292 | oh = _lookup(name); |
63c85238 PW |
3293 | |
3294 | return oh; | |
3295 | } | |
3296 | ||
3297 | /** | |
3298 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3299 | * @fn: pointer to a callback function | |
97d60162 | 3300 | * @data: void * data to pass to callback function |
63c85238 PW |
3301 | * |
3302 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3303 | * function. @fn must return 0 for success or any other value for | |
3304 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3305 | * will stop and the non-zero return value will be passed to the | |
3306 | * caller of omap_hwmod_for_each(). @fn is called with | |
3307 | * omap_hwmod_for_each() held. | |
3308 | */ | |
97d60162 PW |
3309 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3310 | void *data) | |
63c85238 PW |
3311 | { |
3312 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3313 | int ret = 0; |
63c85238 PW |
3314 | |
3315 | if (!fn) | |
3316 | return -EINVAL; | |
3317 | ||
63c85238 | 3318 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3319 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3320 | if (ret) |
3321 | break; | |
3322 | } | |
63c85238 PW |
3323 | |
3324 | return ret; | |
3325 | } | |
3326 | ||
2221b5cd PW |
3327 | /** |
3328 | * omap_hwmod_register_links - register an array of hwmod links | |
3329 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3330 | * | |
3331 | * Intended to be called early in boot before the clock framework is | |
3332 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3333 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3334 | * omap_hwmod_init() hasn't been called before calling this function, | |
3335 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3336 | * success. | |
2221b5cd PW |
3337 | */ |
3338 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3339 | { | |
3340 | int r, i; | |
3341 | ||
9ebfd285 KH |
3342 | if (!inited) |
3343 | return -EINVAL; | |
3344 | ||
2221b5cd PW |
3345 | if (!ois) |
3346 | return 0; | |
3347 | ||
2221b5cd PW |
3348 | if (!linkspace) { |
3349 | if (_alloc_linkspace(ois)) { | |
3350 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3351 | return -ENOMEM; | |
3352 | } | |
3353 | } | |
3354 | ||
3355 | i = 0; | |
3356 | do { | |
3357 | r = _register_link(ois[i]); | |
3358 | WARN(r && r != -EEXIST, | |
3359 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3360 | ois[i]->master->name, ois[i]->slave->name, r); | |
3361 | } while (ois[++i]); | |
3362 | ||
3363 | return 0; | |
3364 | } | |
3365 | ||
381d033a PW |
3366 | /** |
3367 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3368 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3369 | * | |
3370 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3371 | * hasn't been initialized and set up yet, do so now. This must be | |
3372 | * done first since sleep dependencies may be added from other hwmods | |
3373 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3374 | * return value. | |
63c85238 | 3375 | */ |
381d033a | 3376 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3377 | { |
381d033a PW |
3378 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3379 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3380 | __func__, MPU_INITIATOR_NAME); | |
3381 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3382 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3383 | } |
3384 | ||
63c85238 | 3385 | /** |
a2debdbd PW |
3386 | * omap_hwmod_setup_one - set up a single hwmod |
3387 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3388 | * | |
381d033a PW |
3389 | * Initialize and set up a single hwmod. Intended to be used for a |
3390 | * small number of early devices, such as the timer IP blocks used for | |
3391 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3392 | * Resolves the struct clk names to struct clk pointers for each | |
3393 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3394 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3395 | */ |
3396 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3397 | { |
3398 | struct omap_hwmod *oh; | |
63c85238 | 3399 | |
a2debdbd PW |
3400 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3401 | ||
a2debdbd PW |
3402 | oh = _lookup(oh_name); |
3403 | if (!oh) { | |
3404 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3405 | return -EINVAL; | |
3406 | } | |
63c85238 | 3407 | |
381d033a | 3408 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3409 | |
381d033a | 3410 | _init(oh, NULL); |
a2debdbd PW |
3411 | _setup(oh, NULL); |
3412 | ||
63c85238 PW |
3413 | return 0; |
3414 | } | |
3415 | ||
3416 | /** | |
381d033a | 3417 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3418 | * |
381d033a PW |
3419 | * Initialize and set up all IP blocks registered with the hwmod code. |
3420 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3421 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3422 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3423 | */ |
550c8092 | 3424 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3425 | { |
381d033a | 3426 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3427 | |
381d033a | 3428 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3429 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3430 | |
3431 | return 0; | |
3432 | } | |
b76c8b19 | 3433 | omap_core_initcall(omap_hwmod_setup_all); |
63c85238 | 3434 | |
63c85238 PW |
3435 | /** |
3436 | * omap_hwmod_enable - enable an omap_hwmod | |
3437 | * @oh: struct omap_hwmod * | |
3438 | * | |
74ff3a68 | 3439 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3440 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3441 | */ | |
3442 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3443 | { | |
3444 | int r; | |
dc6d1cda | 3445 | unsigned long flags; |
63c85238 PW |
3446 | |
3447 | if (!oh) | |
3448 | return -EINVAL; | |
3449 | ||
dc6d1cda PW |
3450 | spin_lock_irqsave(&oh->_lock, flags); |
3451 | r = _enable(oh); | |
3452 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3453 | |
3454 | return r; | |
3455 | } | |
3456 | ||
3457 | /** | |
3458 | * omap_hwmod_idle - idle an omap_hwmod | |
3459 | * @oh: struct omap_hwmod * | |
3460 | * | |
74ff3a68 | 3461 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3462 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3463 | */ | |
3464 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3465 | { | |
dc6d1cda PW |
3466 | unsigned long flags; |
3467 | ||
63c85238 PW |
3468 | if (!oh) |
3469 | return -EINVAL; | |
3470 | ||
dc6d1cda PW |
3471 | spin_lock_irqsave(&oh->_lock, flags); |
3472 | _idle(oh); | |
3473 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3474 | |
3475 | return 0; | |
3476 | } | |
3477 | ||
3478 | /** | |
3479 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3480 | * @oh: struct omap_hwmod * | |
3481 | * | |
74ff3a68 | 3482 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3483 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3484 | * the return value from _shutdown(). | |
3485 | */ | |
3486 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3487 | { | |
dc6d1cda PW |
3488 | unsigned long flags; |
3489 | ||
63c85238 PW |
3490 | if (!oh) |
3491 | return -EINVAL; | |
3492 | ||
dc6d1cda | 3493 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3494 | _shutdown(oh); |
dc6d1cda | 3495 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3496 | |
3497 | return 0; | |
3498 | } | |
3499 | ||
3500 | /** | |
3501 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3502 | * @oh: struct omap_hwmod *oh | |
3503 | * | |
3504 | * Intended to be called by the omap_device code. | |
3505 | */ | |
3506 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3507 | { | |
dc6d1cda PW |
3508 | unsigned long flags; |
3509 | ||
3510 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3511 | _enable_clocks(oh); |
dc6d1cda | 3512 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3513 | |
3514 | return 0; | |
3515 | } | |
3516 | ||
3517 | /** | |
3518 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3519 | * @oh: struct omap_hwmod *oh | |
3520 | * | |
3521 | * Intended to be called by the omap_device code. | |
3522 | */ | |
3523 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3524 | { | |
dc6d1cda PW |
3525 | unsigned long flags; |
3526 | ||
3527 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3528 | _disable_clocks(oh); |
dc6d1cda | 3529 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3530 | |
3531 | return 0; | |
3532 | } | |
3533 | ||
3534 | /** | |
3535 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3536 | * @oh: struct omap_hwmod *oh | |
3537 | * | |
3538 | * Intended to be called by drivers and core code when all posted | |
3539 | * writes to a device must complete before continuing further | |
3540 | * execution (for example, after clearing some device IRQSTATUS | |
3541 | * register bits) | |
3542 | * | |
3543 | * XXX what about targets with multiple OCP threads? | |
3544 | */ | |
3545 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3546 | { | |
3547 | BUG_ON(!oh); | |
3548 | ||
43b40992 | 3549 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3550 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3551 | oh->name); | |
63c85238 PW |
3552 | return; |
3553 | } | |
3554 | ||
3555 | /* | |
3556 | * Forces posted writes to complete on the OCP thread handling | |
3557 | * register writes | |
3558 | */ | |
cc7a1d2a | 3559 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3560 | } |
3561 | ||
3562 | /** | |
3563 | * omap_hwmod_reset - reset the hwmod | |
3564 | * @oh: struct omap_hwmod * | |
3565 | * | |
3566 | * Under some conditions, a driver may wish to reset the entire device. | |
3567 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3568 | * the return value from _reset(). |
63c85238 PW |
3569 | */ |
3570 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3571 | { | |
3572 | int r; | |
dc6d1cda | 3573 | unsigned long flags; |
63c85238 | 3574 | |
9b579114 | 3575 | if (!oh) |
63c85238 PW |
3576 | return -EINVAL; |
3577 | ||
dc6d1cda | 3578 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3579 | r = _reset(oh); |
dc6d1cda | 3580 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3581 | |
3582 | return r; | |
3583 | } | |
3584 | ||
5e8370f1 PW |
3585 | /* |
3586 | * IP block data retrieval functions | |
3587 | */ | |
3588 | ||
63c85238 PW |
3589 | /** |
3590 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3591 | * @oh: struct omap_hwmod * | |
dad4191d | 3592 | * @flags: Type of resources to include when counting (IRQ/DMA/MEM) |
63c85238 PW |
3593 | * |
3594 | * Count the number of struct resource array elements necessary to | |
3595 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3596 | * that registers omap_devices. Intended to be used to determine the | |
3597 | * size of a dynamically-allocated struct resource array, before | |
3598 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3599 | * resource array elements needed. | |
3600 | * | |
3601 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3602 | * resource IDs. | |
3603 | * | |
3604 | */ | |
dad4191d | 3605 | int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags) |
63c85238 | 3606 | { |
dad4191d | 3607 | int ret = 0; |
63c85238 | 3608 | |
dad4191d PU |
3609 | if (flags & IORESOURCE_IRQ) |
3610 | ret += _count_mpu_irqs(oh); | |
63c85238 | 3611 | |
dad4191d PU |
3612 | if (flags & IORESOURCE_DMA) |
3613 | ret += _count_sdma_reqs(oh); | |
2221b5cd | 3614 | |
dad4191d PU |
3615 | if (flags & IORESOURCE_MEM) { |
3616 | int i = 0; | |
3617 | struct omap_hwmod_ocp_if *os; | |
3618 | struct list_head *p = oh->slave_ports.next; | |
3619 | ||
3620 | while (i < oh->slaves_cnt) { | |
3621 | os = _fetch_next_ocp_if(&p, &i); | |
3622 | ret += _count_ocp_if_addr_spaces(os); | |
3623 | } | |
5d95dde7 | 3624 | } |
63c85238 PW |
3625 | |
3626 | return ret; | |
3627 | } | |
3628 | ||
3629 | /** | |
3630 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3631 | * @oh: struct omap_hwmod * | |
3632 | * @res: pointer to the first element of an array of struct resource to fill | |
3633 | * | |
3634 | * Fill the struct resource array @res with resource data from the | |
3635 | * omap_hwmod @oh. Intended to be called by code that registers | |
3636 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3637 | * number of array elements filled. | |
3638 | */ | |
3639 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3640 | { | |
5d95dde7 | 3641 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3642 | struct list_head *p; |
5d95dde7 | 3643 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3644 | int r = 0; |
3645 | ||
3646 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3647 | ||
212738a4 PW |
3648 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3649 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3650 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3651 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3652 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3653 | (res + r)->flags = IORESOURCE_IRQ; |
3654 | r++; | |
3655 | } | |
3656 | ||
bc614958 PW |
3657 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3658 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3659 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3660 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3661 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3662 | (res + r)->flags = IORESOURCE_DMA; |
3663 | r++; | |
3664 | } | |
3665 | ||
11cd4b94 | 3666 | p = oh->slave_ports.next; |
2221b5cd | 3667 | |
5d95dde7 PW |
3668 | i = 0; |
3669 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3670 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3671 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3672 | |
78183f3f | 3673 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3674 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3675 | (res + r)->start = (os->addr + j)->pa_start; |
3676 | (res + r)->end = (os->addr + j)->pa_end; | |
3677 | (res + r)->flags = IORESOURCE_MEM; | |
3678 | r++; | |
3679 | } | |
3680 | } | |
3681 | ||
3682 | return r; | |
3683 | } | |
3684 | ||
b82b04e8 VH |
3685 | /** |
3686 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3687 | * @oh: struct omap_hwmod * | |
3688 | * @res: pointer to the array of struct resource to fill | |
3689 | * | |
3690 | * Fill the struct resource array @res with dma resource data from the | |
3691 | * omap_hwmod @oh. Intended to be called by code that registers | |
3692 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3693 | * number of array elements filled. | |
3694 | */ | |
3695 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3696 | { | |
3697 | int i, sdma_reqs_cnt; | |
3698 | int r = 0; | |
3699 | ||
3700 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3701 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3702 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3703 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3704 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3705 | (res + r)->flags = IORESOURCE_DMA; | |
3706 | r++; | |
3707 | } | |
3708 | ||
3709 | return r; | |
3710 | } | |
3711 | ||
5e8370f1 PW |
3712 | /** |
3713 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3714 | * @oh: struct omap_hwmod * to operate on | |
3715 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3716 | * @name: pointer to the name of the data to fetch (optional) | |
3717 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3718 | * | |
3719 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3720 | * data for the IP block pointed to by @oh. The data will be filled | |
3721 | * into a struct resource record pointed to by @rsrc. The struct | |
3722 | * resource must be allocated by the caller. When @name is non-null, | |
3723 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3724 | * space hwmod data arrays will be returned. If @name is null, the | |
3725 | * first array entry will be returned. Data order is not meaningful | |
3726 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3727 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3728 | * data is later added that causes data ordering to change. This | |
3729 | * function is only intended for use by OMAP core code. Device | |
3730 | * drivers should not call this function - the appropriate bus-related | |
3731 | * data accessor functions should be used instead. Returns 0 upon | |
3732 | * success or a negative error code upon error. | |
3733 | */ | |
3734 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3735 | const char *name, struct resource *rsrc) | |
3736 | { | |
3737 | int r; | |
3738 | unsigned int irq, dma; | |
3739 | u32 pa_start, pa_end; | |
3740 | ||
3741 | if (!oh || !rsrc) | |
3742 | return -EINVAL; | |
3743 | ||
3744 | if (type == IORESOURCE_IRQ) { | |
3745 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3746 | if (r) | |
3747 | return r; | |
3748 | ||
3749 | rsrc->start = irq; | |
3750 | rsrc->end = irq; | |
3751 | } else if (type == IORESOURCE_DMA) { | |
3752 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3753 | if (r) | |
3754 | return r; | |
3755 | ||
3756 | rsrc->start = dma; | |
3757 | rsrc->end = dma; | |
3758 | } else if (type == IORESOURCE_MEM) { | |
3759 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3760 | if (r) | |
3761 | return r; | |
3762 | ||
3763 | rsrc->start = pa_start; | |
3764 | rsrc->end = pa_end; | |
3765 | } else { | |
3766 | return -EINVAL; | |
3767 | } | |
3768 | ||
3769 | rsrc->flags = type; | |
3770 | rsrc->name = name; | |
3771 | ||
3772 | return 0; | |
3773 | } | |
3774 | ||
63c85238 PW |
3775 | /** |
3776 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3777 | * @oh: struct omap_hwmod * | |
3778 | * | |
3779 | * Return the powerdomain pointer associated with the OMAP module | |
3780 | * @oh's main clock. If @oh does not have a main clk, return the | |
3781 | * powerdomain associated with the interface clock associated with the | |
3782 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3783 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3784 | * success. | |
3785 | */ | |
3786 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3787 | { | |
3788 | struct clk *c; | |
2d6141ba | 3789 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3790 | struct clockdomain *clkdm; |
f5dd3bb5 | 3791 | struct clk_hw_omap *clk; |
63c85238 PW |
3792 | |
3793 | if (!oh) | |
3794 | return NULL; | |
3795 | ||
f5dd3bb5 RN |
3796 | if (oh->clkdm) |
3797 | return oh->clkdm->pwrdm.ptr; | |
3798 | ||
63c85238 PW |
3799 | if (oh->_clk) { |
3800 | c = oh->_clk; | |
3801 | } else { | |
2d6141ba PW |
3802 | oi = _find_mpu_rt_port(oh); |
3803 | if (!oi) | |
63c85238 | 3804 | return NULL; |
2d6141ba | 3805 | c = oi->_clk; |
63c85238 PW |
3806 | } |
3807 | ||
f5dd3bb5 RN |
3808 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3809 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3810 | if (!clkdm) |
d5647c18 TG |
3811 | return NULL; |
3812 | ||
f5dd3bb5 | 3813 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3814 | } |
3815 | ||
db2a60bf PW |
3816 | /** |
3817 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3818 | * @oh: struct omap_hwmod * | |
3819 | * | |
3820 | * Returns the virtual address corresponding to the beginning of the | |
3821 | * module's register target, in the address range that is intended to | |
3822 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3823 | * upon error. | |
3824 | */ | |
3825 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3826 | { | |
3827 | if (!oh) | |
3828 | return NULL; | |
3829 | ||
3830 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3831 | return NULL; | |
3832 | ||
3833 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3834 | return NULL; | |
3835 | ||
3836 | return oh->_mpu_rt_va; | |
3837 | } | |
3838 | ||
63c85238 PW |
3839 | /** |
3840 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3841 | * @oh: struct omap_hwmod * | |
3842 | * @init_oh: struct omap_hwmod * (initiator) | |
3843 | * | |
3844 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3845 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3846 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3847 | * code needs to add/del initiator dependencies dynamically | |
3848 | * before/after accessing a device. Returns the return value from | |
3849 | * _add_initiator_dep(). | |
3850 | * | |
3851 | * XXX Keep a usecount in the clockdomain code | |
3852 | */ | |
3853 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3854 | struct omap_hwmod *init_oh) | |
3855 | { | |
3856 | return _add_initiator_dep(oh, init_oh); | |
3857 | } | |
3858 | ||
3859 | /* | |
3860 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3861 | * for context save/restore operations? | |
3862 | */ | |
3863 | ||
3864 | /** | |
3865 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3866 | * @oh: struct omap_hwmod * | |
3867 | * @init_oh: struct omap_hwmod * (initiator) | |
3868 | * | |
3869 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3870 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3871 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3872 | * code needs to add/del initiator dependencies dynamically | |
3873 | * before/after accessing a device. Returns the return value from | |
3874 | * _del_initiator_dep(). | |
3875 | * | |
3876 | * XXX Keep a usecount in the clockdomain code | |
3877 | */ | |
3878 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3879 | struct omap_hwmod *init_oh) | |
3880 | { | |
3881 | return _del_initiator_dep(oh, init_oh); | |
3882 | } | |
3883 | ||
63c85238 PW |
3884 | /** |
3885 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3886 | * @oh: struct omap_hwmod * | |
3887 | * | |
3888 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3889 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3890 | * this IP block if it has dynamic mux entries. Eventually this | |
3891 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3892 | * wakeup events from the module. Does not set any wakeup routing | |
3893 | * registers beyond this point - if the module is to wake up any other | |
3894 | * module or subsystem, that must be set separately. Called by | |
3895 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3896 | */ |
3897 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3898 | { | |
dc6d1cda | 3899 | unsigned long flags; |
5a7ddcbd | 3900 | u32 v; |
dc6d1cda | 3901 | |
dc6d1cda | 3902 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3903 | |
3904 | if (oh->class->sysc && | |
3905 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3906 | v = oh->_sysc_cache; | |
3907 | _enable_wakeup(oh, &v); | |
3908 | _write_sysconfig(v, oh); | |
3909 | } | |
3910 | ||
eceec009 | 3911 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3912 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3913 | |
3914 | return 0; | |
3915 | } | |
3916 | ||
3917 | /** | |
3918 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3919 | * @oh: struct omap_hwmod * | |
3920 | * | |
3921 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3922 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3923 | * events for this IP block if it has dynamic mux entries. Eventually | |
3924 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3925 | * wakeup events from the module. Does not set any wakeup routing | |
3926 | * registers beyond this point - if the module is to wake up any other | |
3927 | * module or subsystem, that must be set separately. Called by | |
3928 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3929 | */ |
3930 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3931 | { | |
dc6d1cda | 3932 | unsigned long flags; |
5a7ddcbd | 3933 | u32 v; |
dc6d1cda | 3934 | |
dc6d1cda | 3935 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3936 | |
3937 | if (oh->class->sysc && | |
3938 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3939 | v = oh->_sysc_cache; | |
3940 | _disable_wakeup(oh, &v); | |
3941 | _write_sysconfig(v, oh); | |
3942 | } | |
3943 | ||
eceec009 | 3944 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3945 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3946 | |
3947 | return 0; | |
3948 | } | |
43b40992 | 3949 | |
aee48e3c PW |
3950 | /** |
3951 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3952 | * contained in the hwmod module. | |
3953 | * @oh: struct omap_hwmod * | |
3954 | * @name: name of the reset line to lookup and assert | |
3955 | * | |
3956 | * Some IP like dsp, ipu or iva contain processor that require | |
3957 | * an HW reset line to be assert / deassert in order to enable fully | |
3958 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3959 | * yet supported on this OMAP; otherwise, passes along the return value | |
3960 | * from _assert_hardreset(). | |
3961 | */ | |
3962 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3963 | { | |
3964 | int ret; | |
dc6d1cda | 3965 | unsigned long flags; |
aee48e3c PW |
3966 | |
3967 | if (!oh) | |
3968 | return -EINVAL; | |
3969 | ||
dc6d1cda | 3970 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3971 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3972 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3973 | |
3974 | return ret; | |
3975 | } | |
3976 | ||
3977 | /** | |
3978 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3979 | * contained in the hwmod module. | |
3980 | * @oh: struct omap_hwmod * | |
3981 | * @name: name of the reset line to look up and deassert | |
3982 | * | |
3983 | * Some IP like dsp, ipu or iva contain processor that require | |
3984 | * an HW reset line to be assert / deassert in order to enable fully | |
3985 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3986 | * yet supported on this OMAP; otherwise, passes along the return value | |
3987 | * from _deassert_hardreset(). | |
3988 | */ | |
3989 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3990 | { | |
3991 | int ret; | |
dc6d1cda | 3992 | unsigned long flags; |
aee48e3c PW |
3993 | |
3994 | if (!oh) | |
3995 | return -EINVAL; | |
3996 | ||
dc6d1cda | 3997 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3998 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3999 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
4000 | |
4001 | return ret; | |
4002 | } | |
4003 | ||
4004 | /** | |
4005 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
4006 | * contained in the hwmod module | |
4007 | * @oh: struct omap_hwmod * | |
4008 | * @name: name of the reset line to look up and read | |
4009 | * | |
4010 | * Return the current state of the hwmod @oh's reset line named @name: | |
4011 | * returns -EINVAL upon parameter error or if this operation | |
4012 | * is unsupported on the current OMAP; otherwise, passes along the return | |
4013 | * value from _read_hardreset(). | |
4014 | */ | |
4015 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
4016 | { | |
4017 | int ret; | |
dc6d1cda | 4018 | unsigned long flags; |
aee48e3c PW |
4019 | |
4020 | if (!oh) | |
4021 | return -EINVAL; | |
4022 | ||
dc6d1cda | 4023 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 4024 | ret = _read_hardreset(oh, name); |
dc6d1cda | 4025 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
4026 | |
4027 | return ret; | |
4028 | } | |
4029 | ||
4030 | ||
43b40992 PW |
4031 | /** |
4032 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
4033 | * @classname: struct omap_hwmod_class name to search for | |
4034 | * @fn: callback function pointer to call for each hwmod in class @classname | |
4035 | * @user: arbitrary context data to pass to the callback function | |
4036 | * | |
ce35b244 BC |
4037 | * For each omap_hwmod of class @classname, call @fn. |
4038 | * If the callback function returns something other than | |
43b40992 PW |
4039 | * zero, the iterator is terminated, and the callback function's return |
4040 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
4041 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
4042 | */ | |
4043 | int omap_hwmod_for_each_by_class(const char *classname, | |
4044 | int (*fn)(struct omap_hwmod *oh, | |
4045 | void *user), | |
4046 | void *user) | |
4047 | { | |
4048 | struct omap_hwmod *temp_oh; | |
4049 | int ret = 0; | |
4050 | ||
4051 | if (!classname || !fn) | |
4052 | return -EINVAL; | |
4053 | ||
4054 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
4055 | __func__, classname); | |
4056 | ||
43b40992 PW |
4057 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
4058 | if (!strcmp(temp_oh->class->name, classname)) { | |
4059 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
4060 | __func__, temp_oh->name); | |
4061 | ret = (*fn)(temp_oh, user); | |
4062 | if (ret) | |
4063 | break; | |
4064 | } | |
4065 | } | |
4066 | ||
43b40992 PW |
4067 | if (ret) |
4068 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
4069 | __func__, ret); | |
4070 | ||
4071 | return ret; | |
4072 | } | |
4073 | ||
2092e5cc PW |
4074 | /** |
4075 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
4076 | * @oh: struct omap_hwmod * | |
4077 | * @state: state that _setup() should leave the hwmod in | |
4078 | * | |
550c8092 | 4079 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
4080 | * (called by omap_hwmod_setup_*()). See also the documentation |
4081 | * for _setup_postsetup(), above. Returns 0 upon success or | |
4082 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
4083 | * in the wrong state. | |
2092e5cc PW |
4084 | */ |
4085 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
4086 | { | |
4087 | int ret; | |
dc6d1cda | 4088 | unsigned long flags; |
2092e5cc PW |
4089 | |
4090 | if (!oh) | |
4091 | return -EINVAL; | |
4092 | ||
4093 | if (state != _HWMOD_STATE_DISABLED && | |
4094 | state != _HWMOD_STATE_ENABLED && | |
4095 | state != _HWMOD_STATE_IDLE) | |
4096 | return -EINVAL; | |
4097 | ||
dc6d1cda | 4098 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
4099 | |
4100 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
4101 | ret = -EINVAL; | |
4102 | goto ohsps_unlock; | |
4103 | } | |
4104 | ||
4105 | oh->_postsetup_state = state; | |
4106 | ret = 0; | |
4107 | ||
4108 | ohsps_unlock: | |
dc6d1cda | 4109 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
4110 | |
4111 | return ret; | |
4112 | } | |
c80705aa KH |
4113 | |
4114 | /** | |
4115 | * omap_hwmod_get_context_loss_count - get lost context count | |
4116 | * @oh: struct omap_hwmod * | |
4117 | * | |
e6d3a8b0 RN |
4118 | * Returns the context loss count of associated @oh |
4119 | * upon success, or zero if no context loss data is available. | |
c80705aa | 4120 | * |
e6d3a8b0 RN |
4121 | * On OMAP4, this queries the per-hwmod context loss register, |
4122 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
4123 | * enclosing powerdomain context loss count. | |
c80705aa | 4124 | */ |
fc013873 | 4125 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
4126 | { |
4127 | struct powerdomain *pwrdm; | |
4128 | int ret = 0; | |
4129 | ||
e6d3a8b0 RN |
4130 | if (soc_ops.get_context_lost) |
4131 | return soc_ops.get_context_lost(oh); | |
4132 | ||
c80705aa KH |
4133 | pwrdm = omap_hwmod_get_pwrdm(oh); |
4134 | if (pwrdm) | |
4135 | ret = pwrdm_get_context_loss_count(pwrdm); | |
4136 | ||
4137 | return ret; | |
4138 | } | |
43b01643 PW |
4139 | |
4140 | /** | |
4141 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
4142 | * @oh: struct omap_hwmod * | |
4143 | * | |
4144 | * Prevent the hwmod @oh from being reset during the setup process. | |
4145 | * Intended for use by board-*.c files on boards with devices that | |
4146 | * cannot tolerate being reset. Must be called before the hwmod has | |
4147 | * been set up. Returns 0 upon success or negative error code upon | |
4148 | * failure. | |
4149 | */ | |
4150 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
4151 | { | |
4152 | if (!oh) | |
4153 | return -EINVAL; | |
4154 | ||
4155 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
4156 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
4157 | oh->name); | |
4158 | return -EINVAL; | |
4159 | } | |
4160 | ||
4161 | oh->flags |= HWMOD_INIT_NO_RESET; | |
4162 | ||
4163 | return 0; | |
4164 | } | |
abc2d545 TK |
4165 | |
4166 | /** | |
4167 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
4168 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
4169 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
4170 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
4171 | * | |
4172 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
4173 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
4174 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
4175 | * this function is not called for a given pad_idx, then the ISR | |
4176 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
4177 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
4178 | * the _dynamic or wakeup_ entry: if there are other entries not | |
4179 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
4180 | * entries are NOT COUNTED in the dynamic pad index. This function | |
4181 | * must be called separately for each pad that requires its interrupt | |
4182 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
4183 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
4184 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
4185 | * | |
4186 | * XXX This function interface is fragile. Rather than using array | |
4187 | * indexes, which are subject to unpredictable change, it should be | |
4188 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
4189 | * pad records. | |
4190 | */ | |
4191 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
4192 | { | |
4193 | int nr_irqs; | |
4194 | ||
4195 | might_sleep(); | |
4196 | ||
4197 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
4198 | pad_idx >= oh->mux->nr_pads_dynamic) | |
4199 | return -EINVAL; | |
4200 | ||
4201 | /* Check the number of available mpu_irqs */ | |
4202 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
4203 | ; | |
4204 | ||
4205 | if (irq_idx >= nr_irqs) | |
4206 | return -EINVAL; | |
4207 | ||
4208 | if (!oh->mux->irqs) { | |
4209 | /* XXX What frees this? */ | |
4210 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
4211 | GFP_KERNEL); | |
4212 | if (!oh->mux->irqs) | |
4213 | return -ENOMEM; | |
4214 | } | |
4215 | oh->mux->irqs[pad_idx] = irq_idx; | |
4216 | ||
4217 | return 0; | |
4218 | } | |
9ebfd285 KH |
4219 | |
4220 | /** | |
4221 | * omap_hwmod_init - initialize the hwmod code | |
4222 | * | |
4223 | * Sets up some function pointers needed by the hwmod code to operate on the | |
4224 | * currently-booted SoC. Intended to be called once during kernel init | |
4225 | * before any hwmods are registered. No return value. | |
4226 | */ | |
4227 | void __init omap_hwmod_init(void) | |
4228 | { | |
ff4ae5d9 PW |
4229 | if (cpu_is_omap24xx()) { |
4230 | soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; | |
4231 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | |
4232 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4233 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
4234 | } else if (cpu_is_omap34xx()) { | |
4235 | soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; | |
b8249cf2 KH |
4236 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
4237 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4238 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 4239 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 4240 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
4241 | soc_ops.enable_module = _omap4_enable_module; |
4242 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4243 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4244 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4245 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4246 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4247 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
4248 | soc_ops.update_context_lost = _omap4_update_context_lost; |
4249 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
c8b428a5 AM |
4250 | } else if (soc_is_am43xx()) { |
4251 | soc_ops.enable_module = _omap4_enable_module; | |
4252 | soc_ops.disable_module = _omap4_disable_module; | |
4253 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
98bbc114 DG |
4254 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; |
4255 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4256 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
c8b428a5 | 4257 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 VH |
4258 | } else if (soc_is_am33xx()) { |
4259 | soc_ops.enable_module = _am33xx_enable_module; | |
4260 | soc_ops.disable_module = _am33xx_disable_module; | |
4261 | soc_ops.wait_target_ready = _am33xx_wait_target_ready; | |
4262 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | |
4263 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4264 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4265 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4266 | } else { |
4267 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4268 | } |
4269 | ||
4270 | inited = true; | |
4271 | } | |
68c9a95e TL |
4272 | |
4273 | /** | |
4274 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4275 | * @oh: struct omap_hwmod * | |
4276 | * | |
4277 | * Returns the main clock name assocated with @oh upon success, | |
4278 | * or NULL if @oh is NULL. | |
4279 | */ | |
4280 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4281 | { | |
4282 | if (!oh) | |
4283 | return NULL; | |
4284 | ||
4285 | return oh->main_clk; | |
4286 | } |