[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c

/*
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */

#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"

/*
 * OMAP2420 hardware module integration data
 *
 * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

/*
 * IP blocks
 */

/* IVA1 (IVA1) */
static struct omap_hwmod_class iva1_hwmod_class = {
	.name		= "iva1",
};

static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	{ .name = "iva", .rst_shift = 8 },
};

static struct omap_hwmod omap2420_iva_hwmod = {
	.name		= "iva",
	.class		= &iva1_hwmod_class,
	.clkdm_name	= "iva1_clkdm",
	.rst_lines	= omap2420_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
	.main_clk	= "iva1_ifck",
};

/* DSP */
static struct omap_hwmod_class dsp_hwmod_class = {
	.name		= "dsp",
};

static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	{ .name = "logic", .rst_shift = 0 },
	{ .name = "mmu", .rst_shift = 1 },
};

static struct omap_hwmod omap2420_dsp_hwmod = {
	.name		= "dsp",
	.class		= &dsp_hwmod_class,
	.clkdm_name	= "dsp_clkdm",
	.rst_lines	= omap2420_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
	.main_clk	= "dsp_fck",
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
	.rev		= OMAP_I2C_IP_VERSION_1,
	.reset		= &omap_i2c_reset,
};

static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags		= OMAP_I2C_FLAG_NO_FIFO |
			  OMAP_I2C_FLAG_SIMPLE_CLOCK |
			  OMAP_I2C_FLAG_16BIT_DATA_REG |
			  OMAP_I2C_FLAG_BUS_SHIFT_2,
};

/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
	.name		= "i2c1",
	.main_clk	= "i2c1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	/*
	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	 * while a transfer is active seems to cause the I2C block to
	 * timeout. Why? Good question."
	 */
	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
};

/* I2C2 */
static struct omap_hwmod omap2420_i2c2_hwmod = {
	.name		= "i2c2",
	.main_clk	= "i2c2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	.flags		= HWMOD_16BIT_REG,
};

/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
						IS_CSSA_32 | IS_CDSA_32,
	.lch_count = 32,
};

static struct omap_hwmod omap2420_dma_system_hwmod = {
	.name		= "dma",
	.class		= &omap2xxx_dma_hwmod_class,
	.mpu_irqs	= omap2_dma_system_irqs,
	.main_clk	= "core_l3_ck",
	.dev_attr	= &dma_dev_attr,
	.flags		= HWMOD_NO_IDLEST,
};

/* mailbox */
static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
	{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
	{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
};

static struct omap_mbox_pdata omap2420_mailbox_attrs = {
	.num_users	= 4,
	.num_fifos	= 6,
	.info_cnt	= ARRAY_SIZE(omap2420_mailbox_info),
	.info		= omap2420_mailbox_info,
};

static struct omap_hwmod omap2420_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap2xxx_mailbox_hwmod_class,
	.main_clk	= "mailboxes_ick",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
		},
	},
	.dev_attr	= &omap2420_mailbox_attrs,
};

/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	.name = "mcbsp",
};

static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	{ .role = "prcm_fck", .clk = "func_96m_ck" },
};

/* mcbsp1 */
static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

/* mcbsp2 */
static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	.rev_offs	= 0x3c,
	.sysc_offs	= 0x64,
	.syss_offs	= 0x68,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	.name	= "msdi",
	.sysc	= &omap2420_msdi_sysc,
	.reset	= &omap_msdi_reset,
};

/* msdi1 */
static struct omap_hwmod omap2420_msdi1_hwmod = {
	.name		= "msdi1",
	.class		= &omap2420_msdi_hwmod_class,
	.main_clk	= "mmc_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_MMC_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
		},
	},
	.flags		= HWMOD_16BIT_REG,
};

/* HDQ1W/1-wire */
static struct omap_hwmod omap2420_hdq1w_hwmod = {
	.name		= "hdq1w",
	.main_clk	= "hdq_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
		},
	},
	.class		= &omap2_hdq1w_class,
};

/*
 * interfaces
 */

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* IVA <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__iva = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_iva_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* DSP <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_dsp_hwmod,
	.clk		= "dsp_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_timer1_hwmod,
	.clk		= "gpt1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio1_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio2_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio3 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio3_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio4 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio4_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	.master		= &omap2420_dma_system_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_dma_system_hwmod,
	.clk		= "sdma_ick",
	.addr		= omap2_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mailbox_hwmod,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp1_hwmod,
	.clk		= "mcbsp1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp2_hwmod,
	.clk		= "mcbsp2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> msdi1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_msdi1_hwmod,
	.clk		= "mmc_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> hdq1w interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_hdq1w_hwmod,
	.clk		= "hdq_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};


/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_counter_32k_hwmod,
	.clk		= "sync_32k_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2xxx_gpmc_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
	&omap2xxx_l3_main__l4_core,
	&omap2xxx_mpu__l3_main,
	&omap2xxx_dss__l3,
	&omap2xxx_l4_core__mcspi1,
	&omap2xxx_l4_core__mcspi2,
	&omap2xxx_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
	&omap2420_l4_core__i2c1,
	&omap2420_l4_core__i2c2,
	&omap2420_l3__iva,
	&omap2420_l3__dsp,
	&omap2420_l4_wkup__timer1,
	&omap2xxx_l4_core__timer2,
	&omap2xxx_l4_core__timer3,
	&omap2xxx_l4_core__timer4,
	&omap2xxx_l4_core__timer5,
	&omap2xxx_l4_core__timer6,
	&omap2xxx_l4_core__timer7,
	&omap2xxx_l4_core__timer8,
	&omap2xxx_l4_core__timer9,
	&omap2xxx_l4_core__timer10,
	&omap2xxx_l4_core__timer11,
	&omap2xxx_l4_core__timer12,
	&omap2420_l4_wkup__wd_timer2,
	&omap2xxx_l4_core__dss,
	&omap2xxx_l4_core__dss_dispc,
	&omap2xxx_l4_core__dss_rfbi,
	&omap2xxx_l4_core__dss_venc,
	&omap2420_l4_wkup__gpio1,
	&omap2420_l4_wkup__gpio2,
	&omap2420_l4_wkup__gpio3,
	&omap2420_l4_wkup__gpio4,
	&omap2420_dma_system__l3,
	&omap2420_l4_core__dma_system,
	&omap2420_l4_core__mailbox,
	&omap2420_l4_core__mcbsp1,
	&omap2420_l4_core__mcbsp2,
	&omap2420_l4_core__msdi1,
	&omap2xxx_l4_core__rng,
	&omap2xxx_l4_core__sham,
	&omap2xxx_l4_core__aes,
	&omap2420_l4_core__hdq1w,
	&omap2420_l4_wkup__counter_32k,
	&omap2420_l3__gpmc,
	NULL,
};

int __init omap2420_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
Commit	Line	Data
02bfc030	1	/*
7359154e	2	* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
02bfc030	3	*
78183f3f	4	* Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5	5	* Copyright (C) 2012 Texas Instruments, Inc.
02bfc030 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* XXX handle crossbar/shared link difference for L3?
7359154e	13	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	14	*/
3a8761c0 TL	15
3a8761c0 TL	16	#include <linux/i2c-omap.h>
2203747c	17	#include <linux/platform_data/spi-omap2-mcspi.h>
45c3eb7d	18	#include <linux/omap-dma.h>
b8a7cf8e	19	#include <linux/platform_data/mailbox-omap.h>
eddb1262	20	#include <plat/dmtimer.h>
2a296c8f TL	21
2a296c8f TL	22	#include "omap_hwmod.h"
1e0f51a9	23	#include "l3_2xxx.h"
70606b1c	24	#include "l4_2xxx.h"
02bfc030	25
43b40992 PW	26	#include "omap_hwmod_common_data.h"
43b40992 PW	27
a714b9cf	28	#include "cm-regbits-24xx.h"
2004290f	29	#include "prm-regbits-24xx.h"
3a8761c0	30	#include "i2c.h"
68f39e74	31	#include "mmc.h"
3d82cbbb	32	#include "serial.h"
ff2516fb	33	#include "wd_timer.h"
02bfc030	34
7359154e PW	35	/*
	36	* OMAP2420 hardware module integration data
	37	*
844a3b63	38	* All of the data in this section should be autogeneratable from the
7359154e PW	39	* TI hardware database or other technical documentation. Data that
	40	* is driver-specific or driver-kernel integration-specific belongs
	41	* elsewhere.
	42	*/
	43
844a3b63 PW	44	/*
	45	* IP blocks
	46	*/
996746ca	47
3af35fbc PW	48	/* IVA1 (IVA1) */
	49	static struct omap_hwmod_class iva1_hwmod_class = {
	50	.name = "iva1",
	51	};
	52
	53	static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	54	{ .name = "iva", .rst_shift = 8 },
	55	};
	56
08072acf PW	57	static struct omap_hwmod omap2420_iva_hwmod = {
08072acf PW	58	.name = "iva",
3af35fbc PW	59	.class = &iva1_hwmod_class,
	60	.clkdm_name = "iva1_clkdm",
	61	.rst_lines = omap2420_iva_resets,
	62	.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
	63	.main_clk = "iva1_ifck",
	64	};
	65
	66	/* DSP */
	67	static struct omap_hwmod_class dsp_hwmod_class = {
	68	.name = "dsp",
	69	};
	70
	71	static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	72	{ .name = "logic", .rst_shift = 0 },
	73	{ .name = "mmu", .rst_shift = 1 },
	74	};
	75
	76	static struct omap_hwmod omap2420_dsp_hwmod = {
	77	.name = "dsp",
	78	.class = &dsp_hwmod_class,
	79	.clkdm_name = "dsp_clkdm",
	80	.rst_lines = omap2420_dsp_resets,
	81	.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
	82	.main_clk = "dsp_fck",
08072acf PW	83	};
08072acf PW	84
2004290f PW	85	/* I2C common */
	86	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	87	.rev_offs = 0x00,
	88	.sysc_offs = 0x20,
	89	.syss_offs = 0x10,
d73d65fa	90	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
2004290f PW	91	.sysc_fields = &omap_hwmod_sysc_type1,
	92	};
	93
	94	static struct omap_hwmod_class i2c_class = {
	95	.name = "i2c",
	96	.sysc = &i2c_sysc,
db791a75	97	.rev = OMAP_I2C_IP_VERSION_1,
6d3c55fd	98	.reset = &omap_i2c_reset,
2004290f PW	99	};
2004290f PW	100
4d4441a6 AG	101	static struct omap_i2c_dev_attr i2c_dev_attr = {
	102	.flags = OMAP_I2C_FLAG_NO_FIFO \|
	103	OMAP_I2C_FLAG_SIMPLE_CLOCK \|
	104	OMAP_I2C_FLAG_16BIT_DATA_REG \|
	105	OMAP_I2C_FLAG_BUS_SHIFT_2,
	106	};
2004290f PW	107
2004290f PW	108	/* I2C1 */
2004290f PW	109	static struct omap_hwmod omap2420_i2c1_hwmod = {
2004290f PW	110	.name = "i2c1",
2004290f PW	111	.main_clk = "i2c1_fck",
	112	.prcm = {
	113	.omap2 = {
	114	.module_offs = CORE_MOD,
	115	.prcm_reg_id = 1,
	116	.module_bit = OMAP2420_EN_I2C1_SHIFT,
	117	.idlest_reg_id = 1,
	118	.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
	119	},
	120	},
2004290f PW	121	.class = &i2c_class,
2004290f PW	122	.dev_attr = &i2c_dev_attr,
aff2f7d9 PW	123	/*
	124	* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	125	* while a transfer is active seems to cause the I2C block to
	126	* timeout. Why? Good question."
	127	*/
	128	.flags = (HWMOD_16BIT_REG \| HWMOD_BLOCK_WFI),
2004290f PW	129	};
	130
	131	/* I2C2 */
2004290f PW	132	static struct omap_hwmod omap2420_i2c2_hwmod = {
2004290f PW	133	.name = "i2c2",
2004290f PW	134	.main_clk = "i2c2_fck",
	135	.prcm = {
	136	.omap2 = {
	137	.module_offs = CORE_MOD,
	138	.prcm_reg_id = 1,
	139	.module_bit = OMAP2420_EN_I2C2_SHIFT,
	140	.idlest_reg_id = 1,
	141	.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
	142	},
	143	},
2004290f PW	144	.class = &i2c_class,
2004290f PW	145	.dev_attr = &i2c_dev_attr,
2004290f PW	146	.flags = HWMOD_16BIT_REG,
	147	};
	148
745685df MK	149	/* dma attributes */
	150	static struct omap_dma_dev_attr dma_dev_attr = {
	151	.dev_caps = RESERVE_CHANNEL \| DMA_LINKED_LCH \| GLOBAL_PRIORITY \|
	152	IS_CSSA_32 \| IS_CDSA_32,
	153	.lch_count = 32,
	154	};
	155
745685df MK	156	static struct omap_hwmod omap2420_dma_system_hwmod = {
745685df MK	157	.name = "dma",
273b9465	158	.class = &omap2xxx_dma_hwmod_class,
0d619a89	159	.mpu_irqs = omap2_dma_system_irqs,
745685df	160	.main_clk = "core_l3_ck",
745685df	161	.dev_attr = &dma_dev_attr,
745685df MK	162	.flags = HWMOD_NO_IDLEST,
	163	};
	164
fca1ab55	165	/* mailbox */
b8a7cf8e SA	166	static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
	167	{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
	168	{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
	169	};
	170
	171	static struct omap_mbox_pdata omap2420_mailbox_attrs = {
fe32c1f6 SA	172	.num_users = 4,
fe32c1f6 SA	173	.num_fifos = 6,
b8a7cf8e SA	174	.info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
	175	.info = omap2420_mailbox_info,
	176	};
	177
fca1ab55 ORL	178	static struct omap_hwmod omap2420_mailbox_hwmod = {
fca1ab55 ORL	179	.name = "mailbox",
273b9465	180	.class = &omap2xxx_mailbox_hwmod_class,
fca1ab55 ORL	181	.main_clk = "mailboxes_ick",
	182	.prcm = {
	183	.omap2 = {
	184	.prcm_reg_id = 1,
	185	.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
	186	.module_offs = CORE_MOD,
	187	.idlest_reg_id = 1,
	188	.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
	189	},
	190	},
b8a7cf8e	191	.dev_attr = &omap2420_mailbox_attrs,
fca1ab55 ORL	192	};
fca1ab55 ORL	193
3cb72fa4 C	194	/*
	195	* 'mcbsp' class
	196	* multi channel buffered serial port controller
	197	*/
	198
	199	static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	200	.name = "mcbsp",
	201	};
	202
b3153100 PU	203	static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	204	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	205	{ .role = "prcm_fck", .clk = "func_96m_ck" },
	206	};
	207
3cb72fa4	208	/* mcbsp1 */
3cb72fa4 C	209	static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	210	.name = "mcbsp1",
	211	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	212	.main_clk = "mcbsp1_fck",
	213	.prcm = {
	214	.omap2 = {
	215	.prcm_reg_id = 1,
	216	.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
	217	.module_offs = CORE_MOD,
	218	.idlest_reg_id = 1,
	219	.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
	220	},
	221	},
b3153100 PU	222	.opt_clks = mcbsp_opt_clks,
b3153100 PU	223	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
3cb72fa4 C	224	};
	225
	226	/* mcbsp2 */
3cb72fa4 C	227	static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	228	.name = "mcbsp2",
	229	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	230	.main_clk = "mcbsp2_fck",
	231	.prcm = {
	232	.omap2 = {
	233	.prcm_reg_id = 1,
	234	.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
	235	.module_offs = CORE_MOD,
	236	.idlest_reg_id = 1,
	237	.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
	238	},
	239	},
b3153100 PU	240	.opt_clks = mcbsp_opt_clks,
b3153100 PU	241	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
0a78c5c5 PW	242	};
0a78c5c5 PW	243
ad1b6662 TL	244	static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	245	.rev_offs = 0x3c,
	246	.sysc_offs = 0x64,
	247	.syss_offs = 0x68,
	248	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
	249	.sysc_fields = &omap_hwmod_sysc_type1,
	250	};
	251
	252	static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	253	.name = "msdi",
	254	.sysc = &omap2420_msdi_sysc,
	255	.reset = &omap_msdi_reset,
	256	};
	257
	258	/* msdi1 */
ad1b6662 TL	259	static struct omap_hwmod omap2420_msdi1_hwmod = {
	260	.name = "msdi1",
	261	.class = &omap2420_msdi_hwmod_class,
ad1b6662 TL	262	.main_clk = "mmc_fck",
	263	.prcm = {
	264	.omap2 = {
	265	.prcm_reg_id = 1,
	266	.module_bit = OMAP2420_EN_MMC_SHIFT,
	267	.module_offs = CORE_MOD,
	268	.idlest_reg_id = 1,
	269	.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
	270	},
	271	},
	272	.flags = HWMOD_16BIT_REG,
	273	};
	274
f32bd778 PW	275	/* HDQ1W/1-wire */
	276	static struct omap_hwmod omap2420_hdq1w_hwmod = {
	277	.name = "hdq1w",
f32bd778 PW	278	.main_clk = "hdq_fck",
	279	.prcm = {
	280	.omap2 = {
	281	.module_offs = CORE_MOD,
	282	.prcm_reg_id = 1,
	283	.module_bit = OMAP24XX_EN_HDQ_SHIFT,
	284	.idlest_reg_id = 1,
	285	.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
	286	},
	287	},
	288	.class = &omap2_hdq1w_class,
	289	};
	290
844a3b63 PW	291	/*
	292	* interfaces
	293	*/
	294
844a3b63 PW	295	/* L4 CORE -> I2C1 interface */
844a3b63 PW	296	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
cb48427e	297	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	298	.slave = &omap2420_i2c1_hwmod,
844a3b63 PW	299	.clk = "i2c1_ick",
844a3b63 PW	300	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	301	};
	302
	303	/* L4 CORE -> I2C2 interface */
	304	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
cb48427e	305	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	306	.slave = &omap2420_i2c2_hwmod,
844a3b63 PW	307	.clk = "i2c2_ick",
844a3b63 PW	308	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	309	};
	310
	311	/* IVA <- L3 interface */
	312	static struct omap_hwmod_ocp_if omap2420_l3__iva = {
cb48427e	313	.master = &omap2xxx_l3_main_hwmod,
844a3b63	314	.slave = &omap2420_iva_hwmod,
3af35fbc PW	315	.clk = "core_l3_ck",
	316	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	317	};
	318
	319	/* DSP <- L3 interface */
	320	static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	321	.master = &omap2xxx_l3_main_hwmod,
	322	.slave = &omap2420_dsp_hwmod,
	323	.clk = "dsp_ick",
844a3b63 PW	324	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	325	};
	326
844a3b63 PW	327	/* l4_wkup -> timer1 */
844a3b63 PW	328	static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
cb48427e PW	329	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	330	.slave = &omap2xxx_timer1_hwmod,
844a3b63	331	.clk = "gpt1_ick",
844a3b63 PW	332	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	333	};
	334
844a3b63	335	/* l4_wkup -> wd_timer2 */
844a3b63	336	static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
cb48427e PW	337	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	338	.slave = &omap2xxx_wd_timer2_hwmod,
844a3b63	339	.clk = "mpu_wdt_ick",
844a3b63 PW	340	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	341	};
	342
844a3b63	343	/* l4_wkup -> gpio1 */
844a3b63	344	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
cb48427e PW	345	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	346	.slave = &omap2xxx_gpio1_hwmod,
844a3b63	347	.clk = "gpios_ick",
844a3b63 PW	348	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	349	};
	350
	351	/* l4_wkup -> gpio2 */
844a3b63	352	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
cb48427e PW	353	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	354	.slave = &omap2xxx_gpio2_hwmod,
844a3b63	355	.clk = "gpios_ick",
844a3b63 PW	356	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	357	};
	358
	359	/* l4_wkup -> gpio3 */
844a3b63	360	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
cb48427e PW	361	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	362	.slave = &omap2xxx_gpio3_hwmod,
844a3b63	363	.clk = "gpios_ick",
844a3b63 PW	364	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	365	};
	366
	367	/* l4_wkup -> gpio4 */
844a3b63	368	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
cb48427e PW	369	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	370	.slave = &omap2xxx_gpio4_hwmod,
844a3b63	371	.clk = "gpios_ick",
844a3b63 PW	372	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	373	};
	374
	375	/* dma_system -> L3 */
	376	static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	377	.master = &omap2420_dma_system_hwmod,
cb48427e	378	.slave = &omap2xxx_l3_main_hwmod,
844a3b63 PW	379	.clk = "core_l3_ck",
	380	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	381	};
	382
	383	/* l4_core -> dma_system */
	384	static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
cb48427e	385	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	386	.slave = &omap2420_dma_system_hwmod,
	387	.clk = "sdma_ick",
	388	.addr = omap2_dma_system_addrs,
	389	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	390	};
	391
	392	/* l4_core -> mailbox */
	393	static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
cb48427e	394	.master = &omap2xxx_l4_core_hwmod,
844a3b63	395	.slave = &omap2420_mailbox_hwmod,
844a3b63 PW	396	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	397	};
	398
	399	/* l4_core -> mcbsp1 */
	400	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
cb48427e	401	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	402	.slave = &omap2420_mcbsp1_hwmod,
844a3b63 PW	403	.clk = "mcbsp1_ick",
844a3b63 PW	404	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	405	};
	406
	407	/* l4_core -> mcbsp2 */
	408	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
cb48427e	409	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	410	.slave = &omap2420_mcbsp2_hwmod,
844a3b63 PW	411	.clk = "mcbsp2_ick",
844a3b63 PW	412	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	413	};
	414
ad1b6662 TL	415	/* l4_core -> msdi1 */
	416	static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	417	.master = &omap2xxx_l4_core_hwmod,
	418	.slave = &omap2420_msdi1_hwmod,
	419	.clk = "mmc_ick",
ad1b6662 TL	420	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	421	};
	422
f32bd778 PW	423	/* l4_core -> hdq1w interface */
	424	static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	425	.master = &omap2xxx_l4_core_hwmod,
	426	.slave = &omap2420_hdq1w_hwmod,
	427	.clk = "hdq_ick",
f32bd778 PW	428	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	429	.flags = OMAP_FIREWALL_L4 \| OCPIF_SWSUP_IDLE,
	430	};
	431
	432
c8d82ff6	433	/* l4_wkup -> 32ksync_counter */
c8d82ff6 VH	434	static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	435	.master = &omap2xxx_l4_wkup_hwmod,
	436	.slave = &omap2xxx_counter_32k_hwmod,
	437	.clk = "sync_32k_ick",
c8d82ff6 VH	438	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	439	};
	440
49484a60 AM	441	static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	442	.master = &omap2xxx_l3_main_hwmod,
	443	.slave = &omap2xxx_gpmc_hwmod,
	444	.clk = "core_l3_ck",
49484a60 AM	445	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	446	};
	447
0a78c5c5	448	static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
6a29755f PW	449	&omap2xxx_l3_main__l4_core,
	450	&omap2xxx_mpu__l3_main,
	451	&omap2xxx_dss__l3,
	452	&omap2xxx_l4_core__mcspi1,
	453	&omap2xxx_l4_core__mcspi2,
	454	&omap2xxx_l4_core__l4_wkup,
0a78c5c5 PW	455	&omap2_l4_core__uart1,
	456	&omap2_l4_core__uart2,
	457	&omap2_l4_core__uart3,
	458	&omap2420_l4_core__i2c1,
	459	&omap2420_l4_core__i2c2,
	460	&omap2420_l3__iva,
3af35fbc	461	&omap2420_l3__dsp,
0a78c5c5	462	&omap2420_l4_wkup__timer1,
6a29755f PW	463	&omap2xxx_l4_core__timer2,
	464	&omap2xxx_l4_core__timer3,
	465	&omap2xxx_l4_core__timer4,
	466	&omap2xxx_l4_core__timer5,
	467	&omap2xxx_l4_core__timer6,
	468	&omap2xxx_l4_core__timer7,
	469	&omap2xxx_l4_core__timer8,
	470	&omap2xxx_l4_core__timer9,
	471	&omap2xxx_l4_core__timer10,
	472	&omap2xxx_l4_core__timer11,
	473	&omap2xxx_l4_core__timer12,
0a78c5c5	474	&omap2420_l4_wkup__wd_timer2,
6a29755f PW	475	&omap2xxx_l4_core__dss,
	476	&omap2xxx_l4_core__dss_dispc,
	477	&omap2xxx_l4_core__dss_rfbi,
	478	&omap2xxx_l4_core__dss_venc,
0a78c5c5 PW	479	&omap2420_l4_wkup__gpio1,
	480	&omap2420_l4_wkup__gpio2,
	481	&omap2420_l4_wkup__gpio3,
	482	&omap2420_l4_wkup__gpio4,
	483	&omap2420_dma_system__l3,
	484	&omap2420_l4_core__dma_system,
	485	&omap2420_l4_core__mailbox,
	486	&omap2420_l4_core__mcbsp1,
	487	&omap2420_l4_core__mcbsp2,
ad1b6662	488	&omap2420_l4_core__msdi1,
e9b0a2fb	489	&omap2xxx_l4_core__rng,
e569e994	490	&omap2xxx_l4_core__sham,
660ffd6b	491	&omap2xxx_l4_core__aes,
f32bd778	492	&omap2420_l4_core__hdq1w,
c8d82ff6	493	&omap2420_l4_wkup__counter_32k,
49484a60	494	&omap2420_l3__gpmc,
02bfc030 PW	495	NULL,
	496	};
	497
7359154e PW	498	int __init omap2420_hwmod_init(void)
7359154e PW	499	{
9ebfd285	500	omap_hwmod_init();
0a78c5c5	501	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
7359154e	502	}