[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c

/*
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */

#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"

/*
 * OMAP2420 hardware module integration data
 *
 * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

/*
 * IP blocks
 */

/* IVA1 (IVA1) */
static struct omap_hwmod_class iva1_hwmod_class = {
	.name		= "iva1",
};

static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	{ .name = "iva", .rst_shift = 8 },
};

static struct omap_hwmod omap2420_iva_hwmod = {
	.name		= "iva",
	.class		= &iva1_hwmod_class,
	.clkdm_name	= "iva1_clkdm",
	.rst_lines	= omap2420_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
	.main_clk	= "iva1_ifck",
};

/* DSP */
static struct omap_hwmod_class dsp_hwmod_class = {
	.name		= "dsp",
};

static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	{ .name = "logic", .rst_shift = 0 },
	{ .name = "mmu", .rst_shift = 1 },
};

static struct omap_hwmod omap2420_dsp_hwmod = {
	.name		= "dsp",
	.class		= &dsp_hwmod_class,
	.clkdm_name	= "dsp_clkdm",
	.rst_lines	= omap2420_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
	.main_clk	= "dsp_fck",
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
	.rev		= OMAP_I2C_IP_VERSION_1,
	.reset		= &omap_i2c_reset,
};

static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags		= OMAP_I2C_FLAG_NO_FIFO |
			  OMAP_I2C_FLAG_SIMPLE_CLOCK |
			  OMAP_I2C_FLAG_16BIT_DATA_REG |
			  OMAP_I2C_FLAG_BUS_SHIFT_2,
};

/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
	.name		= "i2c1",
	.mpu_irqs	= omap2_i2c1_mpu_irqs,
	.sdma_reqs	= omap2_i2c1_sdma_reqs,
	.main_clk	= "i2c1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	.flags		= HWMOD_16BIT_REG,
};

/* I2C2 */
static struct omap_hwmod omap2420_i2c2_hwmod = {
	.name		= "i2c2",
	.mpu_irqs	= omap2_i2c2_mpu_irqs,
	.sdma_reqs	= omap2_i2c2_sdma_reqs,
	.main_clk	= "i2c2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	.flags		= HWMOD_16BIT_REG,
};

/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
						IS_CSSA_32 | IS_CDSA_32,
	.lch_count = 32,
};

static struct omap_hwmod omap2420_dma_system_hwmod = {
	.name		= "dma",
	.class		= &omap2xxx_dma_hwmod_class,
	.mpu_irqs	= omap2_dma_system_irqs,
	.main_clk	= "core_l3_ck",
	.dev_attr	= &dma_dev_attr,
	.flags		= HWMOD_NO_IDLEST,
};

/* mailbox */
static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap2xxx_mailbox_hwmod_class,
	.mpu_irqs	= omap2420_mailbox_irqs,
	.main_clk	= "mailboxes_ick",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
		},
	},
};

/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	.name = "mcbsp",
};

static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	{ .role = "prcm_fck", .clk = "func_96m_ck" },
};

/* mcbsp1 */
static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
	{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
	{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap2420_mcbsp_hwmod_class,
	.mpu_irqs	= omap2420_mcbsp1_irqs,
	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
	.main_clk	= "mcbsp1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

/* mcbsp2 */
static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
	{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
	{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap2420_mcbsp_hwmod_class,
	.mpu_irqs	= omap2420_mcbsp2_irqs,
	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
	.main_clk	= "mcbsp2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	.rev_offs	= 0x3c,
	.sysc_offs	= 0x64,
	.syss_offs	= 0x68,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	.name	= "msdi",
	.sysc	= &omap2420_msdi_sysc,
	.reset	= &omap_msdi_reset,
};

/* msdi1 */
static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
	{ .irq = 83 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
	{ .dma_req = -1 }
};

static struct omap_hwmod omap2420_msdi1_hwmod = {
	.name		= "msdi1",
	.class		= &omap2420_msdi_hwmod_class,
	.mpu_irqs	= omap2420_msdi1_irqs,
	.sdma_reqs	= omap2420_msdi1_sdma_reqs,
	.main_clk	= "mmc_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_MMC_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
		},
	},
	.flags		= HWMOD_16BIT_REG,
};

/* HDQ1W/1-wire */
static struct omap_hwmod omap2420_hdq1w_hwmod = {
	.name		= "hdq1w",
	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
	.main_clk	= "hdq_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
		},
	},
	.class		= &omap2_hdq1w_class,
};

/*
 * interfaces
 */

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.addr		= omap2_i2c1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.addr		= omap2_i2c2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* IVA <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__iva = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_iva_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* DSP <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_dsp_hwmod,
	.clk		= "dsp_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
	{
		.pa_start	= 0x48028000,
		.pa_end		= 0x48028000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_timer1_hwmod,
	.clk		= "gpt1_ick",
	.addr		= omap2420_timer1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
	{
		.pa_start	= 0x48022000,
		.pa_end		= 0x4802207f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.addr		= omap2420_wd_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
	{
		.pa_start	= 0x48018000,
		.pa_end		= 0x480181ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio1_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio2 */
static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
	{
		.pa_start	= 0x4801a000,
		.pa_end		= 0x4801a1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio2_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio3 */
static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
	{
		.pa_start	= 0x4801c000,
		.pa_end		= 0x4801c1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio3_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio3_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio4 */
static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
	{
		.pa_start	= 0x4801e000,
		.pa_end		= 0x4801e1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio4_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio4_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	.master		= &omap2420_dma_system_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_dma_system_hwmod,
	.clk		= "sdma_ick",
	.addr		= omap2_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mailbox_hwmod,
	.addr		= omap2_mailbox_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp1_hwmod,
	.clk		= "mcbsp1_ick",
	.addr		= omap2_mcbsp1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp2_hwmod,
	.clk		= "mcbsp2_ick",
	.addr		= omap2xxx_mcbsp2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
	{
		.pa_start	= 0x4809c000,
		.pa_end		= 0x4809c000 + SZ_128 - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l4_core -> msdi1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_msdi1_hwmod,
	.clk		= "mmc_ick",
	.addr		= omap2420_msdi1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> hdq1w interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_hdq1w_hwmod,
	.clk		= "hdq_ick",
	.addr		= omap2_hdq1w_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};


/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
	{
		.pa_start	= 0x48004000,
		.pa_end		= 0x4800401f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
	{
		.pa_start	= 0x6800a000,
		.pa_end		= 0x6800afff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_counter_32k_hwmod,
	.clk		= "sync_32k_ick",
	.addr		= omap2420_counter_32k_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2xxx_gpmc_hwmod,
	.clk		= "core_l3_ck",
	.addr		= omap2420_gpmc_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
	&omap2xxx_l3_main__l4_core,
	&omap2xxx_mpu__l3_main,
	&omap2xxx_dss__l3,
	&omap2xxx_l4_core__mcspi1,
	&omap2xxx_l4_core__mcspi2,
	&omap2xxx_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
	&omap2420_l4_core__i2c1,
	&omap2420_l4_core__i2c2,
	&omap2420_l3__iva,
	&omap2420_l3__dsp,
	&omap2420_l4_wkup__timer1,
	&omap2xxx_l4_core__timer2,
	&omap2xxx_l4_core__timer3,
	&omap2xxx_l4_core__timer4,
	&omap2xxx_l4_core__timer5,
	&omap2xxx_l4_core__timer6,
	&omap2xxx_l4_core__timer7,
	&omap2xxx_l4_core__timer8,
	&omap2xxx_l4_core__timer9,
	&omap2xxx_l4_core__timer10,
	&omap2xxx_l4_core__timer11,
	&omap2xxx_l4_core__timer12,
	&omap2420_l4_wkup__wd_timer2,
	&omap2xxx_l4_core__dss,
	&omap2xxx_l4_core__dss_dispc,
	&omap2xxx_l4_core__dss_rfbi,
	&omap2xxx_l4_core__dss_venc,
	&omap2420_l4_wkup__gpio1,
	&omap2420_l4_wkup__gpio2,
	&omap2420_l4_wkup__gpio3,
	&omap2420_l4_wkup__gpio4,
	&omap2420_dma_system__l3,
	&omap2420_l4_core__dma_system,
	&omap2420_l4_core__mailbox,
	&omap2420_l4_core__mcbsp1,
	&omap2420_l4_core__mcbsp2,
	&omap2420_l4_core__msdi1,
	&omap2xxx_l4_core__rng,
	&omap2420_l4_core__hdq1w,
	&omap2420_l4_wkup__counter_32k,
	&omap2420_l3__gpmc,
	NULL,
};

int __init omap2420_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
Commit	Line	Data
02bfc030	1	/*
7359154e	2	* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
02bfc030	3	*
78183f3f	4	* Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5	5	* Copyright (C) 2012 Texas Instruments, Inc.
02bfc030 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* XXX handle crossbar/shared link difference for L3?
7359154e	13	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	14	*/
3a8761c0 TL	15
3a8761c0 TL	16	#include <linux/i2c-omap.h>
2203747c	17	#include <linux/platform_data/spi-omap2-mcspi.h>
45c3eb7d	18	#include <linux/omap-dma.h>
eddb1262	19	#include <plat/dmtimer.h>
2a296c8f TL	20
2a296c8f TL	21	#include "omap_hwmod.h"
1e0f51a9	22	#include "l3_2xxx.h"
70606b1c	23	#include "l4_2xxx.h"
02bfc030	24
43b40992 PW	25	#include "omap_hwmod_common_data.h"
43b40992 PW	26
a714b9cf	27	#include "cm-regbits-24xx.h"
2004290f	28	#include "prm-regbits-24xx.h"
3a8761c0	29	#include "i2c.h"
68f39e74	30	#include "mmc.h"
3d82cbbb	31	#include "serial.h"
ff2516fb	32	#include "wd_timer.h"
02bfc030	33
7359154e PW	34	/*
	35	* OMAP2420 hardware module integration data
	36	*
844a3b63	37	* All of the data in this section should be autogeneratable from the
7359154e PW	38	* TI hardware database or other technical documentation. Data that
	39	* is driver-specific or driver-kernel integration-specific belongs
	40	* elsewhere.
	41	*/
	42
844a3b63 PW	43	/*
	44	* IP blocks
	45	*/
996746ca	46
3af35fbc PW	47	/* IVA1 (IVA1) */
	48	static struct omap_hwmod_class iva1_hwmod_class = {
	49	.name = "iva1",
	50	};
	51
	52	static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	53	{ .name = "iva", .rst_shift = 8 },
	54	};
	55
08072acf PW	56	static struct omap_hwmod omap2420_iva_hwmod = {
08072acf PW	57	.name = "iva",
3af35fbc PW	58	.class = &iva1_hwmod_class,
	59	.clkdm_name = "iva1_clkdm",
	60	.rst_lines = omap2420_iva_resets,
	61	.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
	62	.main_clk = "iva1_ifck",
	63	};
	64
	65	/* DSP */
	66	static struct omap_hwmod_class dsp_hwmod_class = {
	67	.name = "dsp",
	68	};
	69
	70	static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	71	{ .name = "logic", .rst_shift = 0 },
	72	{ .name = "mmu", .rst_shift = 1 },
	73	};
	74
	75	static struct omap_hwmod omap2420_dsp_hwmod = {
	76	.name = "dsp",
	77	.class = &dsp_hwmod_class,
	78	.clkdm_name = "dsp_clkdm",
	79	.rst_lines = omap2420_dsp_resets,
	80	.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
	81	.main_clk = "dsp_fck",
08072acf PW	82	};
08072acf PW	83
2004290f PW	84	/* I2C common */
	85	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	86	.rev_offs = 0x00,
	87	.sysc_offs = 0x20,
	88	.syss_offs = 0x10,
d73d65fa	89	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
2004290f PW	90	.sysc_fields = &omap_hwmod_sysc_type1,
	91	};
	92
	93	static struct omap_hwmod_class i2c_class = {
	94	.name = "i2c",
	95	.sysc = &i2c_sysc,
db791a75	96	.rev = OMAP_I2C_IP_VERSION_1,
6d3c55fd	97	.reset = &omap_i2c_reset,
2004290f PW	98	};
2004290f PW	99
4d4441a6 AG	100	static struct omap_i2c_dev_attr i2c_dev_attr = {
	101	.flags = OMAP_I2C_FLAG_NO_FIFO \|
	102	OMAP_I2C_FLAG_SIMPLE_CLOCK \|
	103	OMAP_I2C_FLAG_16BIT_DATA_REG \|
	104	OMAP_I2C_FLAG_BUS_SHIFT_2,
	105	};
2004290f PW	106
2004290f PW	107	/* I2C1 */
2004290f PW	108	static struct omap_hwmod omap2420_i2c1_hwmod = {
2004290f PW	109	.name = "i2c1",
0d619a89	110	.mpu_irqs = omap2_i2c1_mpu_irqs,
d826ebfa	111	.sdma_reqs = omap2_i2c1_sdma_reqs,
2004290f PW	112	.main_clk = "i2c1_fck",
	113	.prcm = {
	114	.omap2 = {
	115	.module_offs = CORE_MOD,
	116	.prcm_reg_id = 1,
	117	.module_bit = OMAP2420_EN_I2C1_SHIFT,
	118	.idlest_reg_id = 1,
	119	.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
	120	},
	121	},
2004290f PW	122	.class = &i2c_class,
2004290f PW	123	.dev_attr = &i2c_dev_attr,
2004290f PW	124	.flags = HWMOD_16BIT_REG,
	125	};
	126
	127	/* I2C2 */
2004290f PW	128	static struct omap_hwmod omap2420_i2c2_hwmod = {
2004290f PW	129	.name = "i2c2",
0d619a89	130	.mpu_irqs = omap2_i2c2_mpu_irqs,
d826ebfa	131	.sdma_reqs = omap2_i2c2_sdma_reqs,
2004290f PW	132	.main_clk = "i2c2_fck",
	133	.prcm = {
	134	.omap2 = {
	135	.module_offs = CORE_MOD,
	136	.prcm_reg_id = 1,
	137	.module_bit = OMAP2420_EN_I2C2_SHIFT,
	138	.idlest_reg_id = 1,
	139	.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
	140	},
	141	},
2004290f PW	142	.class = &i2c_class,
2004290f PW	143	.dev_attr = &i2c_dev_attr,
2004290f PW	144	.flags = HWMOD_16BIT_REG,
	145	};
	146
745685df MK	147	/* dma attributes */
	148	static struct omap_dma_dev_attr dma_dev_attr = {
	149	.dev_caps = RESERVE_CHANNEL \| DMA_LINKED_LCH \| GLOBAL_PRIORITY \|
	150	IS_CSSA_32 \| IS_CDSA_32,
	151	.lch_count = 32,
	152	};
	153
745685df MK	154	static struct omap_hwmod omap2420_dma_system_hwmod = {
745685df MK	155	.name = "dma",
273b9465	156	.class = &omap2xxx_dma_hwmod_class,
0d619a89	157	.mpu_irqs = omap2_dma_system_irqs,
745685df	158	.main_clk = "core_l3_ck",
745685df	159	.dev_attr = &dma_dev_attr,
745685df MK	160	.flags = HWMOD_NO_IDLEST,
	161	};
	162
fca1ab55	163	/* mailbox */
fca1ab55	164	static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
7d7e1eba TL	165	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
	166	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
	167	{ .irq = -1 },
fca1ab55 ORL	168	};
fca1ab55 ORL	169
fca1ab55 ORL	170	static struct omap_hwmod omap2420_mailbox_hwmod = {
fca1ab55 ORL	171	.name = "mailbox",
273b9465	172	.class = &omap2xxx_mailbox_hwmod_class,
fca1ab55	173	.mpu_irqs = omap2420_mailbox_irqs,
fca1ab55 ORL	174	.main_clk = "mailboxes_ick",
	175	.prcm = {
	176	.omap2 = {
	177	.prcm_reg_id = 1,
	178	.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
	179	.module_offs = CORE_MOD,
	180	.idlest_reg_id = 1,
	181	.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
	182	},
	183	},
fca1ab55 ORL	184	};
fca1ab55 ORL	185
3cb72fa4 C	186	/*
	187	* 'mcbsp' class
	188	* multi channel buffered serial port controller
	189	*/
	190
	191	static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	192	.name = "mcbsp",
	193	};
	194
b3153100 PU	195	static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	196	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	197	{ .role = "prcm_fck", .clk = "func_96m_ck" },
	198	};
	199
3cb72fa4 C	200	/* mcbsp1 */
3cb72fa4 C	201	static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
7d7e1eba TL	202	{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
	203	{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
	204	{ .irq = -1 },
3cb72fa4 C	205	};
3cb72fa4 C	206
3cb72fa4 C	207	static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	208	.name = "mcbsp1",
	209	.class = &omap2420_mcbsp_hwmod_class,
	210	.mpu_irqs = omap2420_mcbsp1_irqs,
d826ebfa	211	.sdma_reqs = omap2_mcbsp1_sdma_reqs,
3cb72fa4 C	212	.main_clk = "mcbsp1_fck",
	213	.prcm = {
	214	.omap2 = {
	215	.prcm_reg_id = 1,
	216	.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
	217	.module_offs = CORE_MOD,
	218	.idlest_reg_id = 1,
	219	.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
	220	},
	221	},
b3153100 PU	222	.opt_clks = mcbsp_opt_clks,
b3153100 PU	223	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
3cb72fa4 C	224	};
	225
	226	/* mcbsp2 */
	227	static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
7d7e1eba TL	228	{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
	229	{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
	230	{ .irq = -1 },
3cb72fa4 C	231	};
3cb72fa4 C	232
3cb72fa4 C	233	static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	234	.name = "mcbsp2",
	235	.class = &omap2420_mcbsp_hwmod_class,
	236	.mpu_irqs = omap2420_mcbsp2_irqs,
d826ebfa	237	.sdma_reqs = omap2_mcbsp2_sdma_reqs,
3cb72fa4 C	238	.main_clk = "mcbsp2_fck",
	239	.prcm = {
	240	.omap2 = {
	241	.prcm_reg_id = 1,
	242	.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
	243	.module_offs = CORE_MOD,
	244	.idlest_reg_id = 1,
	245	.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
	246	},
	247	},
b3153100 PU	248	.opt_clks = mcbsp_opt_clks,
b3153100 PU	249	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
0a78c5c5 PW	250	};
0a78c5c5 PW	251
ad1b6662 TL	252	static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	253	.rev_offs = 0x3c,
	254	.sysc_offs = 0x64,
	255	.syss_offs = 0x68,
	256	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
	257	.sysc_fields = &omap_hwmod_sysc_type1,
	258	};
	259
	260	static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	261	.name = "msdi",
	262	.sysc = &omap2420_msdi_sysc,
	263	.reset = &omap_msdi_reset,
	264	};
	265
	266	/* msdi1 */
	267	static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
7d7e1eba TL	268	{ .irq = 83 + OMAP_INTC_START, },
7d7e1eba TL	269	{ .irq = -1 },
ad1b6662 TL	270	};
	271
	272	static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
	273	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
	274	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
	275	{ .dma_req = -1 }
	276	};
	277
	278	static struct omap_hwmod omap2420_msdi1_hwmod = {
	279	.name = "msdi1",
	280	.class = &omap2420_msdi_hwmod_class,
	281	.mpu_irqs = omap2420_msdi1_irqs,
	282	.sdma_reqs = omap2420_msdi1_sdma_reqs,
	283	.main_clk = "mmc_fck",
	284	.prcm = {
	285	.omap2 = {
	286	.prcm_reg_id = 1,
	287	.module_bit = OMAP2420_EN_MMC_SHIFT,
	288	.module_offs = CORE_MOD,
	289	.idlest_reg_id = 1,
	290	.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
	291	},
	292	},
	293	.flags = HWMOD_16BIT_REG,
	294	};
	295
f32bd778 PW	296	/* HDQ1W/1-wire */
	297	static struct omap_hwmod omap2420_hdq1w_hwmod = {
	298	.name = "hdq1w",
	299	.mpu_irqs = omap2_hdq1w_mpu_irqs,
	300	.main_clk = "hdq_fck",
	301	.prcm = {
	302	.omap2 = {
	303	.module_offs = CORE_MOD,
	304	.prcm_reg_id = 1,
	305	.module_bit = OMAP24XX_EN_HDQ_SHIFT,
	306	.idlest_reg_id = 1,
	307	.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
	308	},
	309	},
	310	.class = &omap2_hdq1w_class,
	311	};
	312
844a3b63 PW	313	/*
	314	* interfaces
	315	*/
	316
844a3b63 PW	317	/* L4 CORE -> I2C1 interface */
844a3b63 PW	318	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
cb48427e	319	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	320	.slave = &omap2420_i2c1_hwmod,
	321	.clk = "i2c1_ick",
	322	.addr = omap2_i2c1_addr_space,
	323	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	324	};
	325
	326	/* L4 CORE -> I2C2 interface */
	327	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
cb48427e	328	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	329	.slave = &omap2420_i2c2_hwmod,
	330	.clk = "i2c2_ick",
	331	.addr = omap2_i2c2_addr_space,
	332	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	333	};
	334
	335	/* IVA <- L3 interface */
	336	static struct omap_hwmod_ocp_if omap2420_l3__iva = {
cb48427e	337	.master = &omap2xxx_l3_main_hwmod,
844a3b63	338	.slave = &omap2420_iva_hwmod,
3af35fbc PW	339	.clk = "core_l3_ck",
	340	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	341	};
	342
	343	/* DSP <- L3 interface */
	344	static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	345	.master = &omap2xxx_l3_main_hwmod,
	346	.slave = &omap2420_dsp_hwmod,
	347	.clk = "dsp_ick",
844a3b63 PW	348	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	349	};
	350
	351	static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
	352	{
	353	.pa_start = 0x48028000,
	354	.pa_end = 0x48028000 + SZ_1K - 1,
	355	.flags = ADDR_TYPE_RT
	356	},
	357	{ }
	358	};
	359
	360	/* l4_wkup -> timer1 */
	361	static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
cb48427e PW	362	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	363	.slave = &omap2xxx_timer1_hwmod,
844a3b63 PW	364	.clk = "gpt1_ick",
	365	.addr = omap2420_timer1_addrs,
	366	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	367	};
	368
844a3b63 PW	369	/* l4_wkup -> wd_timer2 */
	370	static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
	371	{
	372	.pa_start = 0x48022000,
	373	.pa_end = 0x4802207f,
	374	.flags = ADDR_TYPE_RT
	375	},
	376	{ }
	377	};
	378
	379	static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
cb48427e PW	380	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	381	.slave = &omap2xxx_wd_timer2_hwmod,
844a3b63 PW	382	.clk = "mpu_wdt_ick",
	383	.addr = omap2420_wd_timer2_addrs,
	384	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	385	};
	386
844a3b63 PW	387	/* l4_wkup -> gpio1 */
	388	static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
	389	{
	390	.pa_start = 0x48018000,
	391	.pa_end = 0x480181ff,
	392	.flags = ADDR_TYPE_RT
	393	},
	394	{ }
	395	};
	396
	397	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
cb48427e PW	398	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	399	.slave = &omap2xxx_gpio1_hwmod,
844a3b63 PW	400	.clk = "gpios_ick",
	401	.addr = omap2420_gpio1_addr_space,
	402	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	403	};
	404
	405	/* l4_wkup -> gpio2 */
	406	static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
	407	{
	408	.pa_start = 0x4801a000,
	409	.pa_end = 0x4801a1ff,
	410	.flags = ADDR_TYPE_RT
	411	},
	412	{ }
	413	};
	414
	415	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
cb48427e PW	416	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	417	.slave = &omap2xxx_gpio2_hwmod,
844a3b63 PW	418	.clk = "gpios_ick",
	419	.addr = omap2420_gpio2_addr_space,
	420	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	421	};
	422
	423	/* l4_wkup -> gpio3 */
	424	static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
	425	{
	426	.pa_start = 0x4801c000,
	427	.pa_end = 0x4801c1ff,
	428	.flags = ADDR_TYPE_RT
	429	},
	430	{ }
	431	};
	432
	433	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
cb48427e PW	434	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	435	.slave = &omap2xxx_gpio3_hwmod,
844a3b63 PW	436	.clk = "gpios_ick",
	437	.addr = omap2420_gpio3_addr_space,
	438	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	439	};
	440
	441	/* l4_wkup -> gpio4 */
	442	static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
	443	{
	444	.pa_start = 0x4801e000,
	445	.pa_end = 0x4801e1ff,
	446	.flags = ADDR_TYPE_RT
	447	},
	448	{ }
	449	};
	450
	451	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
cb48427e PW	452	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	453	.slave = &omap2xxx_gpio4_hwmod,
844a3b63 PW	454	.clk = "gpios_ick",
	455	.addr = omap2420_gpio4_addr_space,
	456	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	457	};
	458
	459	/* dma_system -> L3 */
	460	static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	461	.master = &omap2420_dma_system_hwmod,
cb48427e	462	.slave = &omap2xxx_l3_main_hwmod,
844a3b63 PW	463	.clk = "core_l3_ck",
	464	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	465	};
	466
	467	/* l4_core -> dma_system */
	468	static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
cb48427e	469	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	470	.slave = &omap2420_dma_system_hwmod,
	471	.clk = "sdma_ick",
	472	.addr = omap2_dma_system_addrs,
	473	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	474	};
	475
	476	/* l4_core -> mailbox */
	477	static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
cb48427e	478	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	479	.slave = &omap2420_mailbox_hwmod,
	480	.addr = omap2_mailbox_addrs,
	481	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	482	};
	483
	484	/* l4_core -> mcbsp1 */
	485	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
cb48427e	486	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	487	.slave = &omap2420_mcbsp1_hwmod,
	488	.clk = "mcbsp1_ick",
	489	.addr = omap2_mcbsp1_addrs,
	490	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	491	};
	492
	493	/* l4_core -> mcbsp2 */
	494	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
cb48427e	495	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	496	.slave = &omap2420_mcbsp2_hwmod,
	497	.clk = "mcbsp2_ick",
	498	.addr = omap2xxx_mcbsp2_addrs,
	499	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	500	};
	501
ad1b6662 TL	502	static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
	503	{
	504	.pa_start = 0x4809c000,
	505	.pa_end = 0x4809c000 + SZ_128 - 1,
	506	.flags = ADDR_TYPE_RT,
	507	},
	508	{ }
	509	};
	510
	511	/* l4_core -> msdi1 */
	512	static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	513	.master = &omap2xxx_l4_core_hwmod,
	514	.slave = &omap2420_msdi1_hwmod,
	515	.clk = "mmc_ick",
	516	.addr = omap2420_msdi1_addrs,
	517	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	518	};
	519
f32bd778 PW	520	/* l4_core -> hdq1w interface */
	521	static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	522	.master = &omap2xxx_l4_core_hwmod,
	523	.slave = &omap2420_hdq1w_hwmod,
	524	.clk = "hdq_ick",
	525	.addr = omap2_hdq1w_addr_space,
	526	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	527	.flags = OMAP_FIREWALL_L4 \| OCPIF_SWSUP_IDLE,
	528	};
	529
	530
c8d82ff6 VH	531	/* l4_wkup -> 32ksync_counter */
	532	static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
	533	{
	534	.pa_start = 0x48004000,
	535	.pa_end = 0x4800401f,
	536	.flags = ADDR_TYPE_RT
	537	},
	538	{ }
	539	};
	540
49484a60 AM	541	static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
	542	{
	543	.pa_start = 0x6800a000,
	544	.pa_end = 0x6800afff,
	545	.flags = ADDR_TYPE_RT
	546	},
	547	{ }
	548	};
	549
c8d82ff6 VH	550	static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	551	.master = &omap2xxx_l4_wkup_hwmod,
	552	.slave = &omap2xxx_counter_32k_hwmod,
	553	.clk = "sync_32k_ick",
	554	.addr = omap2420_counter_32k_addrs,
	555	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	556	};
	557
49484a60 AM	558	static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	559	.master = &omap2xxx_l3_main_hwmod,
	560	.slave = &omap2xxx_gpmc_hwmod,
	561	.clk = "core_l3_ck",
	562	.addr = omap2420_gpmc_addrs,
	563	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	564	};
	565
0a78c5c5	566	static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
6a29755f PW	567	&omap2xxx_l3_main__l4_core,
	568	&omap2xxx_mpu__l3_main,
	569	&omap2xxx_dss__l3,
	570	&omap2xxx_l4_core__mcspi1,
	571	&omap2xxx_l4_core__mcspi2,
	572	&omap2xxx_l4_core__l4_wkup,
0a78c5c5 PW	573	&omap2_l4_core__uart1,
	574	&omap2_l4_core__uart2,
	575	&omap2_l4_core__uart3,
	576	&omap2420_l4_core__i2c1,
	577	&omap2420_l4_core__i2c2,
	578	&omap2420_l3__iva,
3af35fbc	579	&omap2420_l3__dsp,
0a78c5c5	580	&omap2420_l4_wkup__timer1,
6a29755f PW	581	&omap2xxx_l4_core__timer2,
	582	&omap2xxx_l4_core__timer3,
	583	&omap2xxx_l4_core__timer4,
	584	&omap2xxx_l4_core__timer5,
	585	&omap2xxx_l4_core__timer6,
	586	&omap2xxx_l4_core__timer7,
	587	&omap2xxx_l4_core__timer8,
	588	&omap2xxx_l4_core__timer9,
	589	&omap2xxx_l4_core__timer10,
	590	&omap2xxx_l4_core__timer11,
	591	&omap2xxx_l4_core__timer12,
0a78c5c5	592	&omap2420_l4_wkup__wd_timer2,
6a29755f PW	593	&omap2xxx_l4_core__dss,
	594	&omap2xxx_l4_core__dss_dispc,
	595	&omap2xxx_l4_core__dss_rfbi,
	596	&omap2xxx_l4_core__dss_venc,
0a78c5c5 PW	597	&omap2420_l4_wkup__gpio1,
	598	&omap2420_l4_wkup__gpio2,
	599	&omap2420_l4_wkup__gpio3,
	600	&omap2420_l4_wkup__gpio4,
	601	&omap2420_dma_system__l3,
	602	&omap2420_l4_core__dma_system,
	603	&omap2420_l4_core__mailbox,
	604	&omap2420_l4_core__mcbsp1,
	605	&omap2420_l4_core__mcbsp2,
ad1b6662	606	&omap2420_l4_core__msdi1,
e9b0a2fb	607	&omap2xxx_l4_core__rng,
f32bd778	608	&omap2420_l4_core__hdq1w,
c8d82ff6	609	&omap2420_l4_wkup__counter_32k,
49484a60	610	&omap2420_l3__gpmc,
02bfc030 PW	611	NULL,
	612	};
	613
7359154e PW	614	int __init omap2420_hwmod_init(void)
7359154e PW	615	{
9ebfd285	616	omap_hwmod_init();
0a78c5c5	617	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
7359154e	618	}