Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
59c348c3 | 20 | #include <plat/gpio.h> |
617871de | 21 | #include <plat/mcspi.h> |
eddb1262 | 22 | #include <plat/dmtimer.h> |
996746ca SG |
23 | #include <plat/l3_2xxx.h> |
24 | #include <plat/l4_2xxx.h> | |
02bfc030 | 25 | |
43b40992 PW |
26 | #include "omap_hwmod_common_data.h" |
27 | ||
a714b9cf | 28 | #include "cm-regbits-24xx.h" |
2004290f | 29 | #include "prm-regbits-24xx.h" |
ff2516fb | 30 | #include "wd_timer.h" |
02bfc030 | 31 | |
7359154e PW |
32 | /* |
33 | * OMAP2420 hardware module integration data | |
34 | * | |
35 | * ALl of the data in this section should be autogeneratable from the | |
36 | * TI hardware database or other technical documentation. Data that | |
37 | * is driver-specific or driver-kernel integration-specific belongs | |
38 | * elsewhere. | |
39 | */ | |
40 | ||
02bfc030 | 41 | static struct omap_hwmod omap2420_mpu_hwmod; |
08072acf | 42 | static struct omap_hwmod omap2420_iva_hwmod; |
4a7cf90a | 43 | static struct omap_hwmod omap2420_l3_main_hwmod; |
02bfc030 | 44 | static struct omap_hwmod omap2420_l4_core_hwmod; |
996746ca SG |
45 | static struct omap_hwmod omap2420_dss_core_hwmod; |
46 | static struct omap_hwmod omap2420_dss_dispc_hwmod; | |
47 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; | |
48 | static struct omap_hwmod omap2420_dss_venc_hwmod; | |
a714b9cf | 49 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
59c348c3 VC |
50 | static struct omap_hwmod omap2420_gpio1_hwmod; |
51 | static struct omap_hwmod omap2420_gpio2_hwmod; | |
52 | static struct omap_hwmod omap2420_gpio3_hwmod; | |
53 | static struct omap_hwmod omap2420_gpio4_hwmod; | |
745685df | 54 | static struct omap_hwmod omap2420_dma_system_hwmod; |
617871de C |
55 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
56 | static struct omap_hwmod omap2420_mcspi2_hwmod; | |
02bfc030 PW |
57 | |
58 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
59 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
60 | .master = &omap2420_l3_main_hwmod, | |
02bfc030 PW |
61 | .slave = &omap2420_l4_core_hwmod, |
62 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
63 | }; | |
64 | ||
65 | /* MPU -> L3 interface */ | |
4a7cf90a | 66 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
02bfc030 | 67 | .master = &omap2420_mpu_hwmod, |
4a7cf90a | 68 | .slave = &omap2420_l3_main_hwmod, |
02bfc030 PW |
69 | .user = OCP_USER_MPU, |
70 | }; | |
71 | ||
72 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
73 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
74 | &omap2420_mpu__l3_main, | |
02bfc030 PW |
75 | }; |
76 | ||
996746ca SG |
77 | /* DSS -> l3 */ |
78 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { | |
79 | .master = &omap2420_dss_core_hwmod, | |
80 | .slave = &omap2420_l3_main_hwmod, | |
81 | .fw = { | |
82 | .omap2 = { | |
83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
84 | .flags = OMAP_FIREWALL_L3, | |
85 | } | |
86 | }, | |
87 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
88 | }; | |
89 | ||
02bfc030 | 90 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
91 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
92 | &omap2420_l3_main__l4_core, | |
02bfc030 PW |
93 | }; |
94 | ||
95 | /* L3 */ | |
4a7cf90a | 96 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
fa98347e | 97 | .name = "l3_main", |
43b40992 | 98 | .class = &l3_hwmod_class, |
4a7cf90a KH |
99 | .masters = omap2420_l3_main_masters, |
100 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), | |
101 | .slaves = omap2420_l3_main_slaves, | |
102 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), | |
2eb1875d KH |
103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
104 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
105 | }; |
106 | ||
107 | static struct omap_hwmod omap2420_l4_wkup_hwmod; | |
046465b7 KH |
108 | static struct omap_hwmod omap2420_uart1_hwmod; |
109 | static struct omap_hwmod omap2420_uart2_hwmod; | |
110 | static struct omap_hwmod omap2420_uart3_hwmod; | |
2004290f PW |
111 | static struct omap_hwmod omap2420_i2c1_hwmod; |
112 | static struct omap_hwmod omap2420_i2c2_hwmod; | |
3cb72fa4 C |
113 | static struct omap_hwmod omap2420_mcbsp1_hwmod; |
114 | static struct omap_hwmod omap2420_mcbsp2_hwmod; | |
02bfc030 | 115 | |
617871de | 116 | /* l4 core -> mcspi1 interface */ |
617871de C |
117 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
118 | .master = &omap2420_l4_core_hwmod, | |
119 | .slave = &omap2420_mcspi1_hwmod, | |
120 | .clk = "mcspi1_ick", | |
ded11383 | 121 | .addr = omap2_mcspi1_addr_space, |
617871de C |
122 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
123 | }; | |
124 | ||
125 | /* l4 core -> mcspi2 interface */ | |
617871de C |
126 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
127 | .master = &omap2420_l4_core_hwmod, | |
128 | .slave = &omap2420_mcspi2_hwmod, | |
129 | .clk = "mcspi2_ick", | |
ded11383 | 130 | .addr = omap2_mcspi2_addr_space, |
617871de C |
131 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
132 | }; | |
133 | ||
02bfc030 PW |
134 | /* L4_CORE -> L4_WKUP interface */ |
135 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | |
136 | .master = &omap2420_l4_core_hwmod, | |
137 | .slave = &omap2420_l4_wkup_hwmod, | |
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
139 | }; | |
140 | ||
046465b7 | 141 | /* L4 CORE -> UART1 interface */ |
046465b7 KH |
142 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
143 | .master = &omap2420_l4_core_hwmod, | |
144 | .slave = &omap2420_uart1_hwmod, | |
145 | .clk = "uart1_ick", | |
ded11383 | 146 | .addr = omap2xxx_uart1_addr_space, |
046465b7 KH |
147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
148 | }; | |
149 | ||
150 | /* L4 CORE -> UART2 interface */ | |
046465b7 KH |
151 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
152 | .master = &omap2420_l4_core_hwmod, | |
153 | .slave = &omap2420_uart2_hwmod, | |
154 | .clk = "uart2_ick", | |
ded11383 | 155 | .addr = omap2xxx_uart2_addr_space, |
046465b7 KH |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
157 | }; | |
158 | ||
159 | /* L4 PER -> UART3 interface */ | |
046465b7 KH |
160 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
161 | .master = &omap2420_l4_core_hwmod, | |
162 | .slave = &omap2420_uart3_hwmod, | |
163 | .clk = "uart3_ick", | |
ded11383 | 164 | .addr = omap2xxx_uart3_addr_space, |
046465b7 KH |
165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
166 | }; | |
167 | ||
2004290f | 168 | /* L4 CORE -> I2C1 interface */ |
2004290f PW |
169 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
170 | .master = &omap2420_l4_core_hwmod, | |
171 | .slave = &omap2420_i2c1_hwmod, | |
172 | .clk = "i2c1_ick", | |
ded11383 | 173 | .addr = omap2_i2c1_addr_space, |
2004290f PW |
174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
175 | }; | |
176 | ||
177 | /* L4 CORE -> I2C2 interface */ | |
2004290f PW |
178 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
179 | .master = &omap2420_l4_core_hwmod, | |
180 | .slave = &omap2420_i2c2_hwmod, | |
181 | .clk = "i2c2_ick", | |
ded11383 | 182 | .addr = omap2_i2c2_addr_space, |
2004290f PW |
183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
184 | }; | |
185 | ||
02bfc030 PW |
186 | /* Slave interfaces on the L4_CORE interconnect */ |
187 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { | |
4a7cf90a | 188 | &omap2420_l3_main__l4_core, |
02bfc030 PW |
189 | }; |
190 | ||
191 | /* Master interfaces on the L4_CORE interconnect */ | |
192 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |
193 | &omap2420_l4_core__l4_wkup, | |
046465b7 KH |
194 | &omap2_l4_core__uart1, |
195 | &omap2_l4_core__uart2, | |
196 | &omap2_l4_core__uart3, | |
2004290f PW |
197 | &omap2420_l4_core__i2c1, |
198 | &omap2420_l4_core__i2c2 | |
02bfc030 PW |
199 | }; |
200 | ||
201 | /* L4 CORE */ | |
202 | static struct omap_hwmod omap2420_l4_core_hwmod = { | |
fa98347e | 203 | .name = "l4_core", |
43b40992 | 204 | .class = &l4_hwmod_class, |
02bfc030 PW |
205 | .masters = omap2420_l4_core_masters, |
206 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), | |
207 | .slaves = omap2420_l4_core_slaves, | |
208 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), | |
2eb1875d KH |
209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
210 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
211 | }; |
212 | ||
213 | /* Slave interfaces on the L4_WKUP interconnect */ | |
214 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { | |
215 | &omap2420_l4_core__l4_wkup, | |
216 | }; | |
217 | ||
218 | /* Master interfaces on the L4_WKUP interconnect */ | |
219 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { | |
220 | }; | |
221 | ||
222 | /* L4 WKUP */ | |
223 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | |
fa98347e | 224 | .name = "l4_wkup", |
43b40992 | 225 | .class = &l4_hwmod_class, |
02bfc030 PW |
226 | .masters = omap2420_l4_wkup_masters, |
227 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), | |
228 | .slaves = omap2420_l4_wkup_slaves, | |
229 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), | |
2eb1875d KH |
230 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
231 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
232 | }; |
233 | ||
234 | /* Master interfaces on the MPU device */ | |
235 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { | |
4a7cf90a | 236 | &omap2420_mpu__l3_main, |
02bfc030 PW |
237 | }; |
238 | ||
239 | /* MPU */ | |
240 | static struct omap_hwmod omap2420_mpu_hwmod = { | |
5c2c0296 | 241 | .name = "mpu", |
43b40992 | 242 | .class = &mpu_hwmod_class, |
50ebdac2 | 243 | .main_clk = "mpu_ck", |
02bfc030 PW |
244 | .masters = omap2420_mpu_masters, |
245 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), | |
246 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
247 | }; | |
248 | ||
08072acf PW |
249 | /* |
250 | * IVA1 interface data | |
251 | */ | |
252 | ||
253 | /* IVA <- L3 interface */ | |
254 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | |
255 | .master = &omap2420_l3_main_hwmod, | |
256 | .slave = &omap2420_iva_hwmod, | |
257 | .clk = "iva1_ifck", | |
258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
259 | }; | |
260 | ||
261 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { | |
262 | &omap2420_l3__iva, | |
263 | }; | |
264 | ||
265 | /* | |
266 | * IVA2 (IVA2) | |
267 | */ | |
268 | ||
269 | static struct omap_hwmod omap2420_iva_hwmod = { | |
270 | .name = "iva", | |
271 | .class = &iva_hwmod_class, | |
272 | .masters = omap2420_iva_masters, | |
273 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), | |
274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
275 | }; | |
276 | ||
eddb1262 TG |
277 | /* Timer Common */ |
278 | static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { | |
279 | .rev_offs = 0x0000, | |
280 | .sysc_offs = 0x0010, | |
281 | .syss_offs = 0x0014, | |
282 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
283 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
284 | SYSC_HAS_AUTOIDLE), | |
285 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
286 | .sysc_fields = &omap_hwmod_sysc_type1, | |
287 | }; | |
288 | ||
289 | static struct omap_hwmod_class omap2420_timer_hwmod_class = { | |
290 | .name = "timer", | |
291 | .sysc = &omap2420_timer_sysc, | |
292 | .rev = OMAP_TIMER_IP_VERSION_1, | |
293 | }; | |
294 | ||
295 | /* timer1 */ | |
296 | static struct omap_hwmod omap2420_timer1_hwmod; | |
297 | static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { | |
298 | { .irq = 37, }, | |
212738a4 | 299 | { .irq = -1 } |
eddb1262 TG |
300 | }; |
301 | ||
302 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | |
303 | { | |
304 | .pa_start = 0x48028000, | |
305 | .pa_end = 0x48028000 + SZ_1K - 1, | |
306 | .flags = ADDR_TYPE_RT | |
307 | }, | |
78183f3f | 308 | { } |
eddb1262 TG |
309 | }; |
310 | ||
311 | /* l4_wkup -> timer1 */ | |
312 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | |
313 | .master = &omap2420_l4_wkup_hwmod, | |
314 | .slave = &omap2420_timer1_hwmod, | |
315 | .clk = "gpt1_ick", | |
316 | .addr = omap2420_timer1_addrs, | |
eddb1262 TG |
317 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
318 | }; | |
319 | ||
320 | /* timer1 slave port */ | |
321 | static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { | |
322 | &omap2420_l4_wkup__timer1, | |
323 | }; | |
324 | ||
325 | /* timer1 hwmod */ | |
326 | static struct omap_hwmod omap2420_timer1_hwmod = { | |
327 | .name = "timer1", | |
328 | .mpu_irqs = omap2420_timer1_mpu_irqs, | |
eddb1262 TG |
329 | .main_clk = "gpt1_fck", |
330 | .prcm = { | |
331 | .omap2 = { | |
332 | .prcm_reg_id = 1, | |
333 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
334 | .module_offs = WKUP_MOD, | |
335 | .idlest_reg_id = 1, | |
336 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
337 | }, | |
338 | }, | |
339 | .slaves = omap2420_timer1_slaves, | |
340 | .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), | |
341 | .class = &omap2420_timer_hwmod_class, | |
342 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
343 | }; | |
344 | ||
345 | /* timer2 */ | |
346 | static struct omap_hwmod omap2420_timer2_hwmod; | |
347 | static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { | |
348 | { .irq = 38, }, | |
212738a4 | 349 | { .irq = -1 } |
eddb1262 TG |
350 | }; |
351 | ||
eddb1262 TG |
352 | |
353 | /* l4_core -> timer2 */ | |
354 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { | |
355 | .master = &omap2420_l4_core_hwmod, | |
356 | .slave = &omap2420_timer2_hwmod, | |
357 | .clk = "gpt2_ick", | |
ded11383 | 358 | .addr = omap2xxx_timer2_addrs, |
eddb1262 TG |
359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
360 | }; | |
361 | ||
362 | /* timer2 slave port */ | |
363 | static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { | |
364 | &omap2420_l4_core__timer2, | |
365 | }; | |
366 | ||
367 | /* timer2 hwmod */ | |
368 | static struct omap_hwmod omap2420_timer2_hwmod = { | |
369 | .name = "timer2", | |
370 | .mpu_irqs = omap2420_timer2_mpu_irqs, | |
eddb1262 TG |
371 | .main_clk = "gpt2_fck", |
372 | .prcm = { | |
373 | .omap2 = { | |
374 | .prcm_reg_id = 1, | |
375 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
376 | .module_offs = CORE_MOD, | |
377 | .idlest_reg_id = 1, | |
378 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
379 | }, | |
380 | }, | |
381 | .slaves = omap2420_timer2_slaves, | |
382 | .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), | |
383 | .class = &omap2420_timer_hwmod_class, | |
384 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
385 | }; | |
386 | ||
387 | /* timer3 */ | |
388 | static struct omap_hwmod omap2420_timer3_hwmod; | |
389 | static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { | |
390 | { .irq = 39, }, | |
212738a4 | 391 | { .irq = -1 } |
eddb1262 TG |
392 | }; |
393 | ||
eddb1262 TG |
394 | /* l4_core -> timer3 */ |
395 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { | |
396 | .master = &omap2420_l4_core_hwmod, | |
397 | .slave = &omap2420_timer3_hwmod, | |
398 | .clk = "gpt3_ick", | |
ded11383 | 399 | .addr = omap2xxx_timer3_addrs, |
eddb1262 TG |
400 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
401 | }; | |
402 | ||
403 | /* timer3 slave port */ | |
404 | static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { | |
405 | &omap2420_l4_core__timer3, | |
406 | }; | |
407 | ||
408 | /* timer3 hwmod */ | |
409 | static struct omap_hwmod omap2420_timer3_hwmod = { | |
410 | .name = "timer3", | |
411 | .mpu_irqs = omap2420_timer3_mpu_irqs, | |
eddb1262 TG |
412 | .main_clk = "gpt3_fck", |
413 | .prcm = { | |
414 | .omap2 = { | |
415 | .prcm_reg_id = 1, | |
416 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
417 | .module_offs = CORE_MOD, | |
418 | .idlest_reg_id = 1, | |
419 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
420 | }, | |
421 | }, | |
422 | .slaves = omap2420_timer3_slaves, | |
423 | .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), | |
424 | .class = &omap2420_timer_hwmod_class, | |
425 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
426 | }; | |
427 | ||
428 | /* timer4 */ | |
429 | static struct omap_hwmod omap2420_timer4_hwmod; | |
430 | static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { | |
431 | { .irq = 40, }, | |
212738a4 | 432 | { .irq = -1 } |
eddb1262 TG |
433 | }; |
434 | ||
eddb1262 TG |
435 | /* l4_core -> timer4 */ |
436 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { | |
437 | .master = &omap2420_l4_core_hwmod, | |
438 | .slave = &omap2420_timer4_hwmod, | |
439 | .clk = "gpt4_ick", | |
ded11383 | 440 | .addr = omap2xxx_timer4_addrs, |
eddb1262 TG |
441 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
442 | }; | |
443 | ||
444 | /* timer4 slave port */ | |
445 | static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { | |
446 | &omap2420_l4_core__timer4, | |
447 | }; | |
448 | ||
449 | /* timer4 hwmod */ | |
450 | static struct omap_hwmod omap2420_timer4_hwmod = { | |
451 | .name = "timer4", | |
452 | .mpu_irqs = omap2420_timer4_mpu_irqs, | |
eddb1262 TG |
453 | .main_clk = "gpt4_fck", |
454 | .prcm = { | |
455 | .omap2 = { | |
456 | .prcm_reg_id = 1, | |
457 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
458 | .module_offs = CORE_MOD, | |
459 | .idlest_reg_id = 1, | |
460 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
461 | }, | |
462 | }, | |
463 | .slaves = omap2420_timer4_slaves, | |
464 | .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), | |
465 | .class = &omap2420_timer_hwmod_class, | |
466 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
467 | }; | |
468 | ||
469 | /* timer5 */ | |
470 | static struct omap_hwmod omap2420_timer5_hwmod; | |
471 | static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { | |
472 | { .irq = 41, }, | |
212738a4 | 473 | { .irq = -1 } |
eddb1262 TG |
474 | }; |
475 | ||
eddb1262 TG |
476 | /* l4_core -> timer5 */ |
477 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { | |
478 | .master = &omap2420_l4_core_hwmod, | |
479 | .slave = &omap2420_timer5_hwmod, | |
480 | .clk = "gpt5_ick", | |
ded11383 | 481 | .addr = omap2xxx_timer5_addrs, |
eddb1262 TG |
482 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
483 | }; | |
484 | ||
485 | /* timer5 slave port */ | |
486 | static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { | |
487 | &omap2420_l4_core__timer5, | |
488 | }; | |
489 | ||
490 | /* timer5 hwmod */ | |
491 | static struct omap_hwmod omap2420_timer5_hwmod = { | |
492 | .name = "timer5", | |
493 | .mpu_irqs = omap2420_timer5_mpu_irqs, | |
eddb1262 TG |
494 | .main_clk = "gpt5_fck", |
495 | .prcm = { | |
496 | .omap2 = { | |
497 | .prcm_reg_id = 1, | |
498 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
499 | .module_offs = CORE_MOD, | |
500 | .idlest_reg_id = 1, | |
501 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
502 | }, | |
503 | }, | |
504 | .slaves = omap2420_timer5_slaves, | |
505 | .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), | |
506 | .class = &omap2420_timer_hwmod_class, | |
507 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
508 | }; | |
509 | ||
510 | ||
511 | /* timer6 */ | |
512 | static struct omap_hwmod omap2420_timer6_hwmod; | |
513 | static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { | |
514 | { .irq = 42, }, | |
212738a4 | 515 | { .irq = -1 } |
eddb1262 TG |
516 | }; |
517 | ||
eddb1262 TG |
518 | /* l4_core -> timer6 */ |
519 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { | |
520 | .master = &omap2420_l4_core_hwmod, | |
521 | .slave = &omap2420_timer6_hwmod, | |
522 | .clk = "gpt6_ick", | |
ded11383 | 523 | .addr = omap2xxx_timer6_addrs, |
eddb1262 TG |
524 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
525 | }; | |
526 | ||
527 | /* timer6 slave port */ | |
528 | static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { | |
529 | &omap2420_l4_core__timer6, | |
530 | }; | |
531 | ||
532 | /* timer6 hwmod */ | |
533 | static struct omap_hwmod omap2420_timer6_hwmod = { | |
534 | .name = "timer6", | |
535 | .mpu_irqs = omap2420_timer6_mpu_irqs, | |
eddb1262 TG |
536 | .main_clk = "gpt6_fck", |
537 | .prcm = { | |
538 | .omap2 = { | |
539 | .prcm_reg_id = 1, | |
540 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
541 | .module_offs = CORE_MOD, | |
542 | .idlest_reg_id = 1, | |
543 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
544 | }, | |
545 | }, | |
546 | .slaves = omap2420_timer6_slaves, | |
547 | .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), | |
548 | .class = &omap2420_timer_hwmod_class, | |
549 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
550 | }; | |
551 | ||
552 | /* timer7 */ | |
553 | static struct omap_hwmod omap2420_timer7_hwmod; | |
554 | static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { | |
555 | { .irq = 43, }, | |
212738a4 | 556 | { .irq = -1 } |
eddb1262 TG |
557 | }; |
558 | ||
eddb1262 TG |
559 | /* l4_core -> timer7 */ |
560 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { | |
561 | .master = &omap2420_l4_core_hwmod, | |
562 | .slave = &omap2420_timer7_hwmod, | |
563 | .clk = "gpt7_ick", | |
ded11383 | 564 | .addr = omap2xxx_timer7_addrs, |
eddb1262 TG |
565 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
566 | }; | |
567 | ||
568 | /* timer7 slave port */ | |
569 | static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { | |
570 | &omap2420_l4_core__timer7, | |
571 | }; | |
572 | ||
573 | /* timer7 hwmod */ | |
574 | static struct omap_hwmod omap2420_timer7_hwmod = { | |
575 | .name = "timer7", | |
576 | .mpu_irqs = omap2420_timer7_mpu_irqs, | |
eddb1262 TG |
577 | .main_clk = "gpt7_fck", |
578 | .prcm = { | |
579 | .omap2 = { | |
580 | .prcm_reg_id = 1, | |
581 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
582 | .module_offs = CORE_MOD, | |
583 | .idlest_reg_id = 1, | |
584 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
585 | }, | |
586 | }, | |
587 | .slaves = omap2420_timer7_slaves, | |
588 | .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), | |
589 | .class = &omap2420_timer_hwmod_class, | |
590 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
591 | }; | |
592 | ||
593 | /* timer8 */ | |
594 | static struct omap_hwmod omap2420_timer8_hwmod; | |
595 | static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { | |
596 | { .irq = 44, }, | |
212738a4 | 597 | { .irq = -1 } |
eddb1262 TG |
598 | }; |
599 | ||
eddb1262 TG |
600 | /* l4_core -> timer8 */ |
601 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { | |
602 | .master = &omap2420_l4_core_hwmod, | |
603 | .slave = &omap2420_timer8_hwmod, | |
604 | .clk = "gpt8_ick", | |
ded11383 | 605 | .addr = omap2xxx_timer8_addrs, |
eddb1262 TG |
606 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
607 | }; | |
608 | ||
609 | /* timer8 slave port */ | |
610 | static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { | |
611 | &omap2420_l4_core__timer8, | |
612 | }; | |
613 | ||
614 | /* timer8 hwmod */ | |
615 | static struct omap_hwmod omap2420_timer8_hwmod = { | |
616 | .name = "timer8", | |
617 | .mpu_irqs = omap2420_timer8_mpu_irqs, | |
eddb1262 TG |
618 | .main_clk = "gpt8_fck", |
619 | .prcm = { | |
620 | .omap2 = { | |
621 | .prcm_reg_id = 1, | |
622 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
623 | .module_offs = CORE_MOD, | |
624 | .idlest_reg_id = 1, | |
625 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
626 | }, | |
627 | }, | |
628 | .slaves = omap2420_timer8_slaves, | |
629 | .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), | |
630 | .class = &omap2420_timer_hwmod_class, | |
631 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
632 | }; | |
633 | ||
634 | /* timer9 */ | |
635 | static struct omap_hwmod omap2420_timer9_hwmod; | |
636 | static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { | |
637 | { .irq = 45, }, | |
212738a4 | 638 | { .irq = -1 } |
eddb1262 TG |
639 | }; |
640 | ||
eddb1262 TG |
641 | /* l4_core -> timer9 */ |
642 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { | |
643 | .master = &omap2420_l4_core_hwmod, | |
644 | .slave = &omap2420_timer9_hwmod, | |
645 | .clk = "gpt9_ick", | |
ded11383 | 646 | .addr = omap2xxx_timer9_addrs, |
eddb1262 TG |
647 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
648 | }; | |
649 | ||
650 | /* timer9 slave port */ | |
651 | static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { | |
652 | &omap2420_l4_core__timer9, | |
653 | }; | |
654 | ||
655 | /* timer9 hwmod */ | |
656 | static struct omap_hwmod omap2420_timer9_hwmod = { | |
657 | .name = "timer9", | |
658 | .mpu_irqs = omap2420_timer9_mpu_irqs, | |
eddb1262 TG |
659 | .main_clk = "gpt9_fck", |
660 | .prcm = { | |
661 | .omap2 = { | |
662 | .prcm_reg_id = 1, | |
663 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
664 | .module_offs = CORE_MOD, | |
665 | .idlest_reg_id = 1, | |
666 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
667 | }, | |
668 | }, | |
669 | .slaves = omap2420_timer9_slaves, | |
670 | .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), | |
671 | .class = &omap2420_timer_hwmod_class, | |
672 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
673 | }; | |
674 | ||
675 | /* timer10 */ | |
676 | static struct omap_hwmod omap2420_timer10_hwmod; | |
677 | static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { | |
678 | { .irq = 46, }, | |
212738a4 | 679 | { .irq = -1 } |
eddb1262 TG |
680 | }; |
681 | ||
eddb1262 TG |
682 | /* l4_core -> timer10 */ |
683 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { | |
684 | .master = &omap2420_l4_core_hwmod, | |
685 | .slave = &omap2420_timer10_hwmod, | |
686 | .clk = "gpt10_ick", | |
ded11383 | 687 | .addr = omap2_timer10_addrs, |
eddb1262 TG |
688 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
689 | }; | |
690 | ||
691 | /* timer10 slave port */ | |
692 | static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { | |
693 | &omap2420_l4_core__timer10, | |
694 | }; | |
695 | ||
696 | /* timer10 hwmod */ | |
697 | static struct omap_hwmod omap2420_timer10_hwmod = { | |
698 | .name = "timer10", | |
699 | .mpu_irqs = omap2420_timer10_mpu_irqs, | |
eddb1262 TG |
700 | .main_clk = "gpt10_fck", |
701 | .prcm = { | |
702 | .omap2 = { | |
703 | .prcm_reg_id = 1, | |
704 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
705 | .module_offs = CORE_MOD, | |
706 | .idlest_reg_id = 1, | |
707 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
708 | }, | |
709 | }, | |
710 | .slaves = omap2420_timer10_slaves, | |
711 | .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), | |
712 | .class = &omap2420_timer_hwmod_class, | |
713 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
714 | }; | |
715 | ||
716 | /* timer11 */ | |
717 | static struct omap_hwmod omap2420_timer11_hwmod; | |
718 | static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { | |
719 | { .irq = 47, }, | |
212738a4 | 720 | { .irq = -1 } |
eddb1262 TG |
721 | }; |
722 | ||
eddb1262 TG |
723 | /* l4_core -> timer11 */ |
724 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { | |
725 | .master = &omap2420_l4_core_hwmod, | |
726 | .slave = &omap2420_timer11_hwmod, | |
727 | .clk = "gpt11_ick", | |
ded11383 | 728 | .addr = omap2_timer11_addrs, |
eddb1262 TG |
729 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
730 | }; | |
731 | ||
732 | /* timer11 slave port */ | |
733 | static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { | |
734 | &omap2420_l4_core__timer11, | |
735 | }; | |
736 | ||
737 | /* timer11 hwmod */ | |
738 | static struct omap_hwmod omap2420_timer11_hwmod = { | |
739 | .name = "timer11", | |
740 | .mpu_irqs = omap2420_timer11_mpu_irqs, | |
eddb1262 TG |
741 | .main_clk = "gpt11_fck", |
742 | .prcm = { | |
743 | .omap2 = { | |
744 | .prcm_reg_id = 1, | |
745 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
746 | .module_offs = CORE_MOD, | |
747 | .idlest_reg_id = 1, | |
748 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
749 | }, | |
750 | }, | |
751 | .slaves = omap2420_timer11_slaves, | |
752 | .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), | |
753 | .class = &omap2420_timer_hwmod_class, | |
754 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
755 | }; | |
756 | ||
757 | /* timer12 */ | |
758 | static struct omap_hwmod omap2420_timer12_hwmod; | |
759 | static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { | |
760 | { .irq = 48, }, | |
212738a4 | 761 | { .irq = -1 } |
eddb1262 TG |
762 | }; |
763 | ||
eddb1262 TG |
764 | /* l4_core -> timer12 */ |
765 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { | |
766 | .master = &omap2420_l4_core_hwmod, | |
767 | .slave = &omap2420_timer12_hwmod, | |
768 | .clk = "gpt12_ick", | |
ded11383 | 769 | .addr = omap2xxx_timer12_addrs, |
eddb1262 TG |
770 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
771 | }; | |
772 | ||
773 | /* timer12 slave port */ | |
774 | static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { | |
775 | &omap2420_l4_core__timer12, | |
776 | }; | |
777 | ||
778 | /* timer12 hwmod */ | |
779 | static struct omap_hwmod omap2420_timer12_hwmod = { | |
780 | .name = "timer12", | |
781 | .mpu_irqs = omap2420_timer12_mpu_irqs, | |
eddb1262 TG |
782 | .main_clk = "gpt12_fck", |
783 | .prcm = { | |
784 | .omap2 = { | |
785 | .prcm_reg_id = 1, | |
786 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
787 | .module_offs = CORE_MOD, | |
788 | .idlest_reg_id = 1, | |
789 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
790 | }, | |
791 | }, | |
792 | .slaves = omap2420_timer12_slaves, | |
793 | .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), | |
794 | .class = &omap2420_timer_hwmod_class, | |
795 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
796 | }; | |
797 | ||
a714b9cf VC |
798 | /* l4_wkup -> wd_timer2 */ |
799 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | |
800 | { | |
801 | .pa_start = 0x48022000, | |
802 | .pa_end = 0x4802207f, | |
803 | .flags = ADDR_TYPE_RT | |
804 | }, | |
78183f3f | 805 | { } |
a714b9cf VC |
806 | }; |
807 | ||
808 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { | |
809 | .master = &omap2420_l4_wkup_hwmod, | |
810 | .slave = &omap2420_wd_timer2_hwmod, | |
811 | .clk = "mpu_wdt_ick", | |
812 | .addr = omap2420_wd_timer2_addrs, | |
a714b9cf VC |
813 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
814 | }; | |
815 | ||
816 | /* | |
817 | * 'wd_timer' class | |
818 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
819 | * overflow condition | |
820 | */ | |
821 | ||
822 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { | |
823 | .rev_offs = 0x0000, | |
824 | .sysc_offs = 0x0010, | |
825 | .syss_offs = 0x0014, | |
826 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
d73d65fa | 827 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
a714b9cf VC |
828 | .sysc_fields = &omap_hwmod_sysc_type1, |
829 | }; | |
830 | ||
831 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { | |
ff2516fb PW |
832 | .name = "wd_timer", |
833 | .sysc = &omap2420_wd_timer_sysc, | |
834 | .pre_shutdown = &omap2_wd_timer_disable | |
a714b9cf VC |
835 | }; |
836 | ||
837 | /* wd_timer2 */ | |
838 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { | |
839 | &omap2420_l4_wkup__wd_timer2, | |
840 | }; | |
841 | ||
842 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { | |
843 | .name = "wd_timer2", | |
844 | .class = &omap2420_wd_timer_hwmod_class, | |
845 | .main_clk = "mpu_wdt_fck", | |
846 | .prcm = { | |
847 | .omap2 = { | |
848 | .prcm_reg_id = 1, | |
849 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
850 | .module_offs = WKUP_MOD, | |
851 | .idlest_reg_id = 1, | |
852 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
853 | }, | |
854 | }, | |
855 | .slaves = omap2420_wd_timer2_slaves, | |
856 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), | |
857 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
858 | }; | |
859 | ||
046465b7 KH |
860 | /* UART */ |
861 | ||
862 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
863 | .rev_offs = 0x50, | |
864 | .sysc_offs = 0x54, | |
865 | .syss_offs = 0x58, | |
866 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
867 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
d73d65fa | 868 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
046465b7 KH |
869 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
870 | .sysc_fields = &omap_hwmod_sysc_type1, | |
871 | }; | |
872 | ||
873 | static struct omap_hwmod_class uart_class = { | |
874 | .name = "uart", | |
875 | .sysc = &uart_sysc, | |
876 | }; | |
877 | ||
878 | /* UART1 */ | |
879 | ||
880 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
881 | { .irq = INT_24XX_UART1_IRQ, }, | |
212738a4 | 882 | { .irq = -1 } |
046465b7 KH |
883 | }; |
884 | ||
885 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
886 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
887 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
888 | }; | |
889 | ||
890 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { | |
891 | &omap2_l4_core__uart1, | |
892 | }; | |
893 | ||
894 | static struct omap_hwmod omap2420_uart1_hwmod = { | |
895 | .name = "uart1", | |
896 | .mpu_irqs = uart1_mpu_irqs, | |
046465b7 KH |
897 | .sdma_reqs = uart1_sdma_reqs, |
898 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
899 | .main_clk = "uart1_fck", | |
900 | .prcm = { | |
901 | .omap2 = { | |
902 | .module_offs = CORE_MOD, | |
903 | .prcm_reg_id = 1, | |
904 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
905 | .idlest_reg_id = 1, | |
906 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
907 | }, | |
908 | }, | |
909 | .slaves = omap2420_uart1_slaves, | |
910 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), | |
911 | .class = &uart_class, | |
912 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
913 | }; | |
914 | ||
915 | /* UART2 */ | |
916 | ||
917 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
918 | { .irq = INT_24XX_UART2_IRQ, }, | |
212738a4 | 919 | { .irq = -1 } |
046465b7 KH |
920 | }; |
921 | ||
922 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
923 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
924 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
925 | }; | |
926 | ||
927 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { | |
928 | &omap2_l4_core__uart2, | |
929 | }; | |
930 | ||
931 | static struct omap_hwmod omap2420_uart2_hwmod = { | |
932 | .name = "uart2", | |
933 | .mpu_irqs = uart2_mpu_irqs, | |
046465b7 KH |
934 | .sdma_reqs = uart2_sdma_reqs, |
935 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
936 | .main_clk = "uart2_fck", | |
937 | .prcm = { | |
938 | .omap2 = { | |
939 | .module_offs = CORE_MOD, | |
940 | .prcm_reg_id = 1, | |
941 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
942 | .idlest_reg_id = 1, | |
943 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
944 | }, | |
945 | }, | |
946 | .slaves = omap2420_uart2_slaves, | |
947 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), | |
948 | .class = &uart_class, | |
949 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
950 | }; | |
951 | ||
952 | /* UART3 */ | |
953 | ||
954 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
955 | { .irq = INT_24XX_UART3_IRQ, }, | |
212738a4 | 956 | { .irq = -1 } |
046465b7 KH |
957 | }; |
958 | ||
959 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
960 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
961 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
962 | }; | |
963 | ||
964 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { | |
965 | &omap2_l4_core__uart3, | |
966 | }; | |
967 | ||
968 | static struct omap_hwmod omap2420_uart3_hwmod = { | |
969 | .name = "uart3", | |
970 | .mpu_irqs = uart3_mpu_irqs, | |
046465b7 KH |
971 | .sdma_reqs = uart3_sdma_reqs, |
972 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
973 | .main_clk = "uart3_fck", | |
974 | .prcm = { | |
975 | .omap2 = { | |
976 | .module_offs = CORE_MOD, | |
977 | .prcm_reg_id = 2, | |
978 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
979 | .idlest_reg_id = 2, | |
980 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
981 | }, | |
982 | }, | |
983 | .slaves = omap2420_uart3_slaves, | |
984 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), | |
985 | .class = &uart_class, | |
986 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
987 | }; | |
988 | ||
996746ca SG |
989 | /* |
990 | * 'dss' class | |
991 | * display sub-system | |
992 | */ | |
993 | ||
994 | static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { | |
995 | .rev_offs = 0x0000, | |
996 | .sysc_offs = 0x0010, | |
997 | .syss_offs = 0x0014, | |
998 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
999 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1000 | }; | |
1001 | ||
1002 | static struct omap_hwmod_class omap2420_dss_hwmod_class = { | |
1003 | .name = "dss", | |
1004 | .sysc = &omap2420_dss_sysc, | |
1005 | }; | |
1006 | ||
996746ca SG |
1007 | static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { |
1008 | { .name = "dispc", .dma_req = 5 }, | |
1009 | }; | |
1010 | ||
1011 | /* dss */ | |
1012 | /* dss master ports */ | |
1013 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { | |
1014 | &omap2420_dss__l3, | |
1015 | }; | |
1016 | ||
996746ca SG |
1017 | /* l4_core -> dss */ |
1018 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { | |
1019 | .master = &omap2420_l4_core_hwmod, | |
1020 | .slave = &omap2420_dss_core_hwmod, | |
1021 | .clk = "dss_ick", | |
ded11383 | 1022 | .addr = omap2_dss_addrs, |
996746ca SG |
1023 | .fw = { |
1024 | .omap2 = { | |
1025 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
1026 | .flags = OMAP_FIREWALL_L4, | |
1027 | } | |
1028 | }, | |
1029 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1030 | }; | |
1031 | ||
1032 | /* dss slave ports */ | |
1033 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { | |
1034 | &omap2420_l4_core__dss, | |
1035 | }; | |
1036 | ||
1037 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1038 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
1039 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
1040 | }; | |
1041 | ||
1042 | static struct omap_hwmod omap2420_dss_core_hwmod = { | |
1043 | .name = "dss_core", | |
1044 | .class = &omap2420_dss_hwmod_class, | |
1045 | .main_clk = "dss1_fck", /* instead of dss_fck */ | |
996746ca SG |
1046 | .sdma_reqs = omap2420_dss_sdma_chs, |
1047 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), | |
1048 | .prcm = { | |
1049 | .omap2 = { | |
1050 | .prcm_reg_id = 1, | |
1051 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1052 | .module_offs = CORE_MOD, | |
1053 | .idlest_reg_id = 1, | |
1054 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
1055 | }, | |
1056 | }, | |
1057 | .opt_clks = dss_opt_clks, | |
1058 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1059 | .slaves = omap2420_dss_slaves, | |
1060 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), | |
1061 | .masters = omap2420_dss_masters, | |
1062 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), | |
1063 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1064 | .flags = HWMOD_NO_IDLEST, | |
1065 | }; | |
1066 | ||
1067 | /* | |
1068 | * 'dispc' class | |
1069 | * display controller | |
1070 | */ | |
1071 | ||
1072 | static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { | |
1073 | .rev_offs = 0x0000, | |
1074 | .sysc_offs = 0x0010, | |
1075 | .syss_offs = 0x0014, | |
1076 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
1077 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1078 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1079 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1080 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1081 | }; | |
1082 | ||
1083 | static struct omap_hwmod_class omap2420_dispc_hwmod_class = { | |
1084 | .name = "dispc", | |
1085 | .sysc = &omap2420_dispc_sysc, | |
1086 | }; | |
1087 | ||
affe360d | 1088 | static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { |
1089 | { .irq = 25 }, | |
212738a4 | 1090 | { .irq = -1 } |
affe360d | 1091 | }; |
1092 | ||
996746ca SG |
1093 | /* l4_core -> dss_dispc */ |
1094 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { | |
1095 | .master = &omap2420_l4_core_hwmod, | |
1096 | .slave = &omap2420_dss_dispc_hwmod, | |
1097 | .clk = "dss_ick", | |
ded11383 | 1098 | .addr = omap2_dss_dispc_addrs, |
996746ca SG |
1099 | .fw = { |
1100 | .omap2 = { | |
1101 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, | |
1102 | .flags = OMAP_FIREWALL_L4, | |
1103 | } | |
1104 | }, | |
1105 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1106 | }; | |
1107 | ||
1108 | /* dss_dispc slave ports */ | |
1109 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { | |
1110 | &omap2420_l4_core__dss_dispc, | |
1111 | }; | |
1112 | ||
1113 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { | |
1114 | .name = "dss_dispc", | |
1115 | .class = &omap2420_dispc_hwmod_class, | |
affe360d | 1116 | .mpu_irqs = omap2420_dispc_irqs, |
996746ca SG |
1117 | .main_clk = "dss1_fck", |
1118 | .prcm = { | |
1119 | .omap2 = { | |
1120 | .prcm_reg_id = 1, | |
1121 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1122 | .module_offs = CORE_MOD, | |
1123 | .idlest_reg_id = 1, | |
1124 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
1125 | }, | |
1126 | }, | |
1127 | .slaves = omap2420_dss_dispc_slaves, | |
1128 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), | |
1129 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1130 | .flags = HWMOD_NO_IDLEST, | |
1131 | }; | |
1132 | ||
1133 | /* | |
1134 | * 'rfbi' class | |
1135 | * remote frame buffer interface | |
1136 | */ | |
1137 | ||
1138 | static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { | |
1139 | .rev_offs = 0x0000, | |
1140 | .sysc_offs = 0x0010, | |
1141 | .syss_offs = 0x0014, | |
1142 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1143 | SYSC_HAS_AUTOIDLE), | |
1144 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1145 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1146 | }; | |
1147 | ||
1148 | static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { | |
1149 | .name = "rfbi", | |
1150 | .sysc = &omap2420_rfbi_sysc, | |
1151 | }; | |
1152 | ||
996746ca SG |
1153 | /* l4_core -> dss_rfbi */ |
1154 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { | |
1155 | .master = &omap2420_l4_core_hwmod, | |
1156 | .slave = &omap2420_dss_rfbi_hwmod, | |
1157 | .clk = "dss_ick", | |
ded11383 | 1158 | .addr = omap2_dss_rfbi_addrs, |
996746ca SG |
1159 | .fw = { |
1160 | .omap2 = { | |
1161 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
1162 | .flags = OMAP_FIREWALL_L4, | |
1163 | } | |
1164 | }, | |
1165 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1166 | }; | |
1167 | ||
1168 | /* dss_rfbi slave ports */ | |
1169 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { | |
1170 | &omap2420_l4_core__dss_rfbi, | |
1171 | }; | |
1172 | ||
1173 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { | |
1174 | .name = "dss_rfbi", | |
1175 | .class = &omap2420_rfbi_hwmod_class, | |
1176 | .main_clk = "dss1_fck", | |
1177 | .prcm = { | |
1178 | .omap2 = { | |
1179 | .prcm_reg_id = 1, | |
1180 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1181 | .module_offs = CORE_MOD, | |
1182 | }, | |
1183 | }, | |
1184 | .slaves = omap2420_dss_rfbi_slaves, | |
1185 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), | |
1186 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1187 | .flags = HWMOD_NO_IDLEST, | |
1188 | }; | |
1189 | ||
1190 | /* | |
1191 | * 'venc' class | |
1192 | * video encoder | |
1193 | */ | |
1194 | ||
1195 | static struct omap_hwmod_class omap2420_venc_hwmod_class = { | |
1196 | .name = "venc", | |
1197 | }; | |
1198 | ||
996746ca SG |
1199 | /* l4_core -> dss_venc */ |
1200 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { | |
1201 | .master = &omap2420_l4_core_hwmod, | |
1202 | .slave = &omap2420_dss_venc_hwmod, | |
1203 | .clk = "dss_54m_fck", | |
ded11383 | 1204 | .addr = omap2_dss_venc_addrs, |
996746ca SG |
1205 | .fw = { |
1206 | .omap2 = { | |
1207 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, | |
1208 | .flags = OMAP_FIREWALL_L4, | |
1209 | } | |
1210 | }, | |
c39bee8a | 1211 | .flags = OCPIF_SWSUP_IDLE, |
996746ca SG |
1212 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1213 | }; | |
1214 | ||
1215 | /* dss_venc slave ports */ | |
1216 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { | |
1217 | &omap2420_l4_core__dss_venc, | |
1218 | }; | |
1219 | ||
1220 | static struct omap_hwmod omap2420_dss_venc_hwmod = { | |
1221 | .name = "dss_venc", | |
1222 | .class = &omap2420_venc_hwmod_class, | |
1223 | .main_clk = "dss1_fck", | |
1224 | .prcm = { | |
1225 | .omap2 = { | |
1226 | .prcm_reg_id = 1, | |
1227 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1228 | .module_offs = CORE_MOD, | |
1229 | }, | |
1230 | }, | |
1231 | .slaves = omap2420_dss_venc_slaves, | |
1232 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), | |
1233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1234 | .flags = HWMOD_NO_IDLEST, | |
1235 | }; | |
1236 | ||
2004290f PW |
1237 | /* I2C common */ |
1238 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1239 | .rev_offs = 0x00, | |
1240 | .sysc_offs = 0x20, | |
1241 | .syss_offs = 0x10, | |
d73d65fa | 1242 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
2004290f PW |
1243 | .sysc_fields = &omap_hwmod_sysc_type1, |
1244 | }; | |
1245 | ||
1246 | static struct omap_hwmod_class i2c_class = { | |
1247 | .name = "i2c", | |
1248 | .sysc = &i2c_sysc, | |
1249 | }; | |
1250 | ||
1251 | static struct omap_i2c_dev_attr i2c_dev_attr; | |
1252 | ||
1253 | /* I2C1 */ | |
1254 | ||
1255 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | |
1256 | { .irq = INT_24XX_I2C1_IRQ, }, | |
212738a4 | 1257 | { .irq = -1 } |
2004290f PW |
1258 | }; |
1259 | ||
1260 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
1261 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
1262 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
1263 | }; | |
1264 | ||
1265 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { | |
1266 | &omap2420_l4_core__i2c1, | |
1267 | }; | |
1268 | ||
1269 | static struct omap_hwmod omap2420_i2c1_hwmod = { | |
1270 | .name = "i2c1", | |
1271 | .mpu_irqs = i2c1_mpu_irqs, | |
2004290f PW |
1272 | .sdma_reqs = i2c1_sdma_reqs, |
1273 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
1274 | .main_clk = "i2c1_fck", | |
1275 | .prcm = { | |
1276 | .omap2 = { | |
1277 | .module_offs = CORE_MOD, | |
1278 | .prcm_reg_id = 1, | |
1279 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | |
1280 | .idlest_reg_id = 1, | |
1281 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | |
1282 | }, | |
1283 | }, | |
1284 | .slaves = omap2420_i2c1_slaves, | |
1285 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), | |
1286 | .class = &i2c_class, | |
1287 | .dev_attr = &i2c_dev_attr, | |
1288 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1289 | .flags = HWMOD_16BIT_REG, | |
1290 | }; | |
1291 | ||
1292 | /* I2C2 */ | |
1293 | ||
1294 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | |
1295 | { .irq = INT_24XX_I2C2_IRQ, }, | |
212738a4 | 1296 | { .irq = -1 } |
2004290f PW |
1297 | }; |
1298 | ||
1299 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
1300 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
1301 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
1302 | }; | |
1303 | ||
1304 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { | |
1305 | &omap2420_l4_core__i2c2, | |
1306 | }; | |
1307 | ||
1308 | static struct omap_hwmod omap2420_i2c2_hwmod = { | |
1309 | .name = "i2c2", | |
1310 | .mpu_irqs = i2c2_mpu_irqs, | |
2004290f PW |
1311 | .sdma_reqs = i2c2_sdma_reqs, |
1312 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
1313 | .main_clk = "i2c2_fck", | |
1314 | .prcm = { | |
1315 | .omap2 = { | |
1316 | .module_offs = CORE_MOD, | |
1317 | .prcm_reg_id = 1, | |
1318 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | |
1319 | .idlest_reg_id = 1, | |
1320 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | |
1321 | }, | |
1322 | }, | |
1323 | .slaves = omap2420_i2c2_slaves, | |
1324 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), | |
1325 | .class = &i2c_class, | |
1326 | .dev_attr = &i2c_dev_attr, | |
1327 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1328 | .flags = HWMOD_16BIT_REG, | |
1329 | }; | |
1330 | ||
59c348c3 VC |
1331 | /* l4_wkup -> gpio1 */ |
1332 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | |
1333 | { | |
1334 | .pa_start = 0x48018000, | |
1335 | .pa_end = 0x480181ff, | |
1336 | .flags = ADDR_TYPE_RT | |
1337 | }, | |
78183f3f | 1338 | { } |
59c348c3 VC |
1339 | }; |
1340 | ||
1341 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | |
1342 | .master = &omap2420_l4_wkup_hwmod, | |
1343 | .slave = &omap2420_gpio1_hwmod, | |
1344 | .clk = "gpios_ick", | |
1345 | .addr = omap2420_gpio1_addr_space, | |
59c348c3 VC |
1346 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1347 | }; | |
1348 | ||
1349 | /* l4_wkup -> gpio2 */ | |
1350 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | |
1351 | { | |
1352 | .pa_start = 0x4801a000, | |
1353 | .pa_end = 0x4801a1ff, | |
1354 | .flags = ADDR_TYPE_RT | |
1355 | }, | |
78183f3f | 1356 | { } |
59c348c3 VC |
1357 | }; |
1358 | ||
1359 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | |
1360 | .master = &omap2420_l4_wkup_hwmod, | |
1361 | .slave = &omap2420_gpio2_hwmod, | |
1362 | .clk = "gpios_ick", | |
1363 | .addr = omap2420_gpio2_addr_space, | |
59c348c3 VC |
1364 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1365 | }; | |
1366 | ||
1367 | /* l4_wkup -> gpio3 */ | |
1368 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | |
1369 | { | |
1370 | .pa_start = 0x4801c000, | |
1371 | .pa_end = 0x4801c1ff, | |
1372 | .flags = ADDR_TYPE_RT | |
1373 | }, | |
78183f3f | 1374 | { } |
59c348c3 VC |
1375 | }; |
1376 | ||
1377 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | |
1378 | .master = &omap2420_l4_wkup_hwmod, | |
1379 | .slave = &omap2420_gpio3_hwmod, | |
1380 | .clk = "gpios_ick", | |
1381 | .addr = omap2420_gpio3_addr_space, | |
59c348c3 VC |
1382 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1383 | }; | |
1384 | ||
1385 | /* l4_wkup -> gpio4 */ | |
1386 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | |
1387 | { | |
1388 | .pa_start = 0x4801e000, | |
1389 | .pa_end = 0x4801e1ff, | |
1390 | .flags = ADDR_TYPE_RT | |
1391 | }, | |
78183f3f | 1392 | { } |
59c348c3 VC |
1393 | }; |
1394 | ||
1395 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | |
1396 | .master = &omap2420_l4_wkup_hwmod, | |
1397 | .slave = &omap2420_gpio4_hwmod, | |
1398 | .clk = "gpios_ick", | |
1399 | .addr = omap2420_gpio4_addr_space, | |
59c348c3 VC |
1400 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1401 | }; | |
1402 | ||
1403 | /* gpio dev_attr */ | |
1404 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1405 | .bank_width = 32, | |
1406 | .dbck_flag = false, | |
1407 | }; | |
1408 | ||
1409 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { | |
1410 | .rev_offs = 0x0000, | |
1411 | .sysc_offs = 0x0010, | |
1412 | .syss_offs = 0x0014, | |
1413 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
d73d65fa A |
1414 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1415 | SYSS_HAS_RESET_STATUS), | |
59c348c3 VC |
1416 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1417 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1418 | }; | |
1419 | ||
1420 | /* | |
1421 | * 'gpio' class | |
1422 | * general purpose io module | |
1423 | */ | |
1424 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { | |
1425 | .name = "gpio", | |
1426 | .sysc = &omap242x_gpio_sysc, | |
1427 | .rev = 0, | |
1428 | }; | |
1429 | ||
1430 | /* gpio1 */ | |
1431 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { | |
1432 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
212738a4 | 1433 | { .irq = -1 } |
59c348c3 VC |
1434 | }; |
1435 | ||
1436 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { | |
1437 | &omap2420_l4_wkup__gpio1, | |
1438 | }; | |
1439 | ||
1440 | static struct omap_hwmod omap2420_gpio1_hwmod = { | |
1441 | .name = "gpio1", | |
f95440ca | 1442 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
59c348c3 | 1443 | .mpu_irqs = omap242x_gpio1_irqs, |
59c348c3 VC |
1444 | .main_clk = "gpios_fck", |
1445 | .prcm = { | |
1446 | .omap2 = { | |
1447 | .prcm_reg_id = 1, | |
1448 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1449 | .module_offs = WKUP_MOD, | |
1450 | .idlest_reg_id = 1, | |
1451 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1452 | }, | |
1453 | }, | |
1454 | .slaves = omap2420_gpio1_slaves, | |
1455 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), | |
1456 | .class = &omap242x_gpio_hwmod_class, | |
1457 | .dev_attr = &gpio_dev_attr, | |
1458 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1459 | }; | |
1460 | ||
1461 | /* gpio2 */ | |
1462 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { | |
1463 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
212738a4 | 1464 | { .irq = -1 } |
59c348c3 VC |
1465 | }; |
1466 | ||
1467 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { | |
1468 | &omap2420_l4_wkup__gpio2, | |
1469 | }; | |
1470 | ||
1471 | static struct omap_hwmod omap2420_gpio2_hwmod = { | |
1472 | .name = "gpio2", | |
f95440ca | 1473 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
59c348c3 | 1474 | .mpu_irqs = omap242x_gpio2_irqs, |
59c348c3 VC |
1475 | .main_clk = "gpios_fck", |
1476 | .prcm = { | |
1477 | .omap2 = { | |
1478 | .prcm_reg_id = 1, | |
1479 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1480 | .module_offs = WKUP_MOD, | |
1481 | .idlest_reg_id = 1, | |
1482 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1483 | }, | |
1484 | }, | |
1485 | .slaves = omap2420_gpio2_slaves, | |
1486 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), | |
1487 | .class = &omap242x_gpio_hwmod_class, | |
1488 | .dev_attr = &gpio_dev_attr, | |
1489 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1490 | }; | |
1491 | ||
1492 | /* gpio3 */ | |
1493 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { | |
1494 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
212738a4 | 1495 | { .irq = -1 } |
59c348c3 VC |
1496 | }; |
1497 | ||
1498 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { | |
1499 | &omap2420_l4_wkup__gpio3, | |
1500 | }; | |
1501 | ||
1502 | static struct omap_hwmod omap2420_gpio3_hwmod = { | |
1503 | .name = "gpio3", | |
f95440ca | 1504 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
59c348c3 | 1505 | .mpu_irqs = omap242x_gpio3_irqs, |
59c348c3 VC |
1506 | .main_clk = "gpios_fck", |
1507 | .prcm = { | |
1508 | .omap2 = { | |
1509 | .prcm_reg_id = 1, | |
1510 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1511 | .module_offs = WKUP_MOD, | |
1512 | .idlest_reg_id = 1, | |
1513 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1514 | }, | |
1515 | }, | |
1516 | .slaves = omap2420_gpio3_slaves, | |
1517 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), | |
1518 | .class = &omap242x_gpio_hwmod_class, | |
1519 | .dev_attr = &gpio_dev_attr, | |
1520 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1521 | }; | |
1522 | ||
1523 | /* gpio4 */ | |
1524 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { | |
1525 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
212738a4 | 1526 | { .irq = -1 } |
59c348c3 VC |
1527 | }; |
1528 | ||
1529 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { | |
1530 | &omap2420_l4_wkup__gpio4, | |
1531 | }; | |
1532 | ||
1533 | static struct omap_hwmod omap2420_gpio4_hwmod = { | |
1534 | .name = "gpio4", | |
f95440ca | 1535 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
59c348c3 | 1536 | .mpu_irqs = omap242x_gpio4_irqs, |
59c348c3 VC |
1537 | .main_clk = "gpios_fck", |
1538 | .prcm = { | |
1539 | .omap2 = { | |
1540 | .prcm_reg_id = 1, | |
1541 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1542 | .module_offs = WKUP_MOD, | |
1543 | .idlest_reg_id = 1, | |
1544 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1545 | }, | |
1546 | }, | |
1547 | .slaves = omap2420_gpio4_slaves, | |
1548 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), | |
1549 | .class = &omap242x_gpio_hwmod_class, | |
1550 | .dev_attr = &gpio_dev_attr, | |
1551 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1552 | }; | |
1553 | ||
745685df MK |
1554 | /* system dma */ |
1555 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { | |
1556 | .rev_offs = 0x0000, | |
1557 | .sysc_offs = 0x002c, | |
1558 | .syss_offs = 0x0028, | |
1559 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
1560 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
d73d65fa | 1561 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
745685df MK |
1562 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
1563 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1564 | }; | |
1565 | ||
1566 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { | |
1567 | .name = "dma", | |
1568 | .sysc = &omap2420_dma_sysc, | |
1569 | }; | |
1570 | ||
1571 | /* dma attributes */ | |
1572 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1573 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1574 | IS_CSSA_32 | IS_CDSA_32, | |
1575 | .lch_count = 32, | |
1576 | }; | |
1577 | ||
1578 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { | |
1579 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
1580 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
1581 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
1582 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
212738a4 | 1583 | { .irq = -1 } |
745685df MK |
1584 | }; |
1585 | ||
745685df MK |
1586 | /* dma_system -> L3 */ |
1587 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | |
1588 | .master = &omap2420_dma_system_hwmod, | |
1589 | .slave = &omap2420_l3_main_hwmod, | |
1590 | .clk = "core_l3_ck", | |
1591 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1592 | }; | |
1593 | ||
1594 | /* dma_system master ports */ | |
1595 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { | |
1596 | &omap2420_dma_system__l3, | |
1597 | }; | |
1598 | ||
1599 | /* l4_core -> dma_system */ | |
1600 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | |
1601 | .master = &omap2420_l4_core_hwmod, | |
1602 | .slave = &omap2420_dma_system_hwmod, | |
1603 | .clk = "sdma_ick", | |
ded11383 | 1604 | .addr = omap2_dma_system_addrs, |
745685df MK |
1605 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1606 | }; | |
1607 | ||
1608 | /* dma_system slave ports */ | |
1609 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { | |
1610 | &omap2420_l4_core__dma_system, | |
1611 | }; | |
1612 | ||
1613 | static struct omap_hwmod omap2420_dma_system_hwmod = { | |
1614 | .name = "dma", | |
1615 | .class = &omap2420_dma_hwmod_class, | |
1616 | .mpu_irqs = omap2420_dma_system_irqs, | |
745685df MK |
1617 | .main_clk = "core_l3_ck", |
1618 | .slaves = omap2420_dma_system_slaves, | |
1619 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), | |
1620 | .masters = omap2420_dma_system_masters, | |
1621 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), | |
1622 | .dev_attr = &dma_dev_attr, | |
1623 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1624 | .flags = HWMOD_NO_IDLEST, | |
1625 | }; | |
1626 | ||
fca1ab55 ORL |
1627 | /* |
1628 | * 'mailbox' class | |
1629 | * mailbox module allowing communication between the on-chip processors | |
1630 | * using a queued mailbox-interrupt mechanism. | |
1631 | */ | |
1632 | ||
1633 | static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { | |
1634 | .rev_offs = 0x000, | |
1635 | .sysc_offs = 0x010, | |
1636 | .syss_offs = 0x014, | |
1637 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1638 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1639 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1640 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1641 | }; | |
1642 | ||
1643 | static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { | |
1644 | .name = "mailbox", | |
1645 | .sysc = &omap2420_mailbox_sysc, | |
1646 | }; | |
1647 | ||
1648 | /* mailbox */ | |
1649 | static struct omap_hwmod omap2420_mailbox_hwmod; | |
1650 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { | |
1651 | { .name = "dsp", .irq = 26 }, | |
1652 | { .name = "iva", .irq = 34 }, | |
212738a4 | 1653 | { .irq = -1 } |
fca1ab55 ORL |
1654 | }; |
1655 | ||
fca1ab55 ORL |
1656 | /* l4_core -> mailbox */ |
1657 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | |
1658 | .master = &omap2420_l4_core_hwmod, | |
1659 | .slave = &omap2420_mailbox_hwmod, | |
ded11383 | 1660 | .addr = omap2_mailbox_addrs, |
fca1ab55 ORL |
1661 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1662 | }; | |
1663 | ||
1664 | /* mailbox slave ports */ | |
1665 | static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { | |
1666 | &omap2420_l4_core__mailbox, | |
1667 | }; | |
1668 | ||
1669 | static struct omap_hwmod omap2420_mailbox_hwmod = { | |
1670 | .name = "mailbox", | |
1671 | .class = &omap2420_mailbox_hwmod_class, | |
1672 | .mpu_irqs = omap2420_mailbox_irqs, | |
fca1ab55 ORL |
1673 | .main_clk = "mailboxes_ick", |
1674 | .prcm = { | |
1675 | .omap2 = { | |
1676 | .prcm_reg_id = 1, | |
1677 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1678 | .module_offs = CORE_MOD, | |
1679 | .idlest_reg_id = 1, | |
1680 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
1681 | }, | |
1682 | }, | |
1683 | .slaves = omap2420_mailbox_slaves, | |
1684 | .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), | |
1685 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1686 | }; | |
1687 | ||
617871de C |
1688 | /* |
1689 | * 'mcspi' class | |
1690 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1691 | * bus | |
1692 | */ | |
1693 | ||
1694 | static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { | |
1695 | .rev_offs = 0x0000, | |
1696 | .sysc_offs = 0x0010, | |
1697 | .syss_offs = 0x0014, | |
1698 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1699 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1700 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1701 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1702 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1703 | }; | |
1704 | ||
1705 | static struct omap_hwmod_class omap2420_mcspi_class = { | |
1706 | .name = "mcspi", | |
1707 | .sysc = &omap2420_mcspi_sysc, | |
1708 | .rev = OMAP2_MCSPI_REV, | |
1709 | }; | |
1710 | ||
1711 | /* mcspi1 */ | |
1712 | static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { | |
1713 | { .irq = 65 }, | |
212738a4 | 1714 | { .irq = -1 } |
617871de C |
1715 | }; |
1716 | ||
1717 | static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { | |
1718 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ | |
1719 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ | |
1720 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ | |
1721 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ | |
1722 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ | |
1723 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ | |
1724 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ | |
1725 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ | |
1726 | }; | |
1727 | ||
1728 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { | |
1729 | &omap2420_l4_core__mcspi1, | |
1730 | }; | |
1731 | ||
1732 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1733 | .num_chipselect = 4, | |
1734 | }; | |
1735 | ||
1736 | static struct omap_hwmod omap2420_mcspi1_hwmod = { | |
1737 | .name = "mcspi1_hwmod", | |
1738 | .mpu_irqs = omap2420_mcspi1_mpu_irqs, | |
617871de C |
1739 | .sdma_reqs = omap2420_mcspi1_sdma_reqs, |
1740 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), | |
1741 | .main_clk = "mcspi1_fck", | |
1742 | .prcm = { | |
1743 | .omap2 = { | |
1744 | .module_offs = CORE_MOD, | |
1745 | .prcm_reg_id = 1, | |
1746 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1747 | .idlest_reg_id = 1, | |
1748 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1749 | }, | |
1750 | }, | |
1751 | .slaves = omap2420_mcspi1_slaves, | |
1752 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), | |
1753 | .class = &omap2420_mcspi_class, | |
1754 | .dev_attr = &omap_mcspi1_dev_attr, | |
1755 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1756 | }; | |
1757 | ||
1758 | /* mcspi2 */ | |
1759 | static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { | |
1760 | { .irq = 66 }, | |
212738a4 | 1761 | { .irq = -1 } |
617871de C |
1762 | }; |
1763 | ||
1764 | static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { | |
1765 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ | |
1766 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ | |
1767 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ | |
1768 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ | |
1769 | }; | |
1770 | ||
1771 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { | |
1772 | &omap2420_l4_core__mcspi2, | |
1773 | }; | |
1774 | ||
1775 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1776 | .num_chipselect = 2, | |
1777 | }; | |
1778 | ||
1779 | static struct omap_hwmod omap2420_mcspi2_hwmod = { | |
1780 | .name = "mcspi2_hwmod", | |
1781 | .mpu_irqs = omap2420_mcspi2_mpu_irqs, | |
617871de C |
1782 | .sdma_reqs = omap2420_mcspi2_sdma_reqs, |
1783 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), | |
1784 | .main_clk = "mcspi2_fck", | |
1785 | .prcm = { | |
1786 | .omap2 = { | |
1787 | .module_offs = CORE_MOD, | |
1788 | .prcm_reg_id = 1, | |
1789 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1790 | .idlest_reg_id = 1, | |
1791 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1792 | }, | |
1793 | }, | |
1794 | .slaves = omap2420_mcspi2_slaves, | |
1795 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), | |
1796 | .class = &omap2420_mcspi_class, | |
1797 | .dev_attr = &omap_mcspi2_dev_attr, | |
1798 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1799 | }; | |
1800 | ||
3cb72fa4 C |
1801 | /* |
1802 | * 'mcbsp' class | |
1803 | * multi channel buffered serial port controller | |
1804 | */ | |
1805 | ||
1806 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |
1807 | .name = "mcbsp", | |
1808 | }; | |
1809 | ||
1810 | /* mcbsp1 */ | |
1811 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | |
1812 | { .name = "tx", .irq = 59 }, | |
1813 | { .name = "rx", .irq = 60 }, | |
212738a4 | 1814 | { .irq = -1 } |
3cb72fa4 C |
1815 | }; |
1816 | ||
1817 | static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { | |
1818 | { .name = "rx", .dma_req = 32 }, | |
1819 | { .name = "tx", .dma_req = 31 }, | |
1820 | }; | |
1821 | ||
3cb72fa4 C |
1822 | /* l4_core -> mcbsp1 */ |
1823 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | |
1824 | .master = &omap2420_l4_core_hwmod, | |
1825 | .slave = &omap2420_mcbsp1_hwmod, | |
1826 | .clk = "mcbsp1_ick", | |
ded11383 | 1827 | .addr = omap2_mcbsp1_addrs, |
3cb72fa4 C |
1828 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1829 | }; | |
1830 | ||
1831 | /* mcbsp1 slave ports */ | |
1832 | static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { | |
1833 | &omap2420_l4_core__mcbsp1, | |
1834 | }; | |
1835 | ||
1836 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { | |
1837 | .name = "mcbsp1", | |
1838 | .class = &omap2420_mcbsp_hwmod_class, | |
1839 | .mpu_irqs = omap2420_mcbsp1_irqs, | |
3cb72fa4 C |
1840 | .sdma_reqs = omap2420_mcbsp1_sdma_chs, |
1841 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), | |
1842 | .main_clk = "mcbsp1_fck", | |
1843 | .prcm = { | |
1844 | .omap2 = { | |
1845 | .prcm_reg_id = 1, | |
1846 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1847 | .module_offs = CORE_MOD, | |
1848 | .idlest_reg_id = 1, | |
1849 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
1850 | }, | |
1851 | }, | |
1852 | .slaves = omap2420_mcbsp1_slaves, | |
1853 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), | |
1854 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1855 | }; | |
1856 | ||
1857 | /* mcbsp2 */ | |
1858 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | |
1859 | { .name = "tx", .irq = 62 }, | |
1860 | { .name = "rx", .irq = 63 }, | |
212738a4 | 1861 | { .irq = -1 } |
3cb72fa4 C |
1862 | }; |
1863 | ||
1864 | static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { | |
1865 | { .name = "rx", .dma_req = 34 }, | |
1866 | { .name = "tx", .dma_req = 33 }, | |
1867 | }; | |
1868 | ||
3cb72fa4 C |
1869 | /* l4_core -> mcbsp2 */ |
1870 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | |
1871 | .master = &omap2420_l4_core_hwmod, | |
1872 | .slave = &omap2420_mcbsp2_hwmod, | |
1873 | .clk = "mcbsp2_ick", | |
ded11383 | 1874 | .addr = omap2xxx_mcbsp2_addrs, |
3cb72fa4 C |
1875 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1876 | }; | |
1877 | ||
1878 | /* mcbsp2 slave ports */ | |
1879 | static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { | |
1880 | &omap2420_l4_core__mcbsp2, | |
1881 | }; | |
1882 | ||
1883 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { | |
1884 | .name = "mcbsp2", | |
1885 | .class = &omap2420_mcbsp_hwmod_class, | |
1886 | .mpu_irqs = omap2420_mcbsp2_irqs, | |
3cb72fa4 C |
1887 | .sdma_reqs = omap2420_mcbsp2_sdma_chs, |
1888 | .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), | |
1889 | .main_clk = "mcbsp2_fck", | |
1890 | .prcm = { | |
1891 | .omap2 = { | |
1892 | .prcm_reg_id = 1, | |
1893 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1894 | .module_offs = CORE_MOD, | |
1895 | .idlest_reg_id = 1, | |
1896 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
1897 | }, | |
1898 | }, | |
1899 | .slaves = omap2420_mcbsp2_slaves, | |
1900 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), | |
1901 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1902 | }; | |
1903 | ||
02bfc030 | 1904 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
4a7cf90a | 1905 | &omap2420_l3_main_hwmod, |
02bfc030 PW |
1906 | &omap2420_l4_core_hwmod, |
1907 | &omap2420_l4_wkup_hwmod, | |
1908 | &omap2420_mpu_hwmod, | |
08072acf | 1909 | &omap2420_iva_hwmod, |
eddb1262 TG |
1910 | |
1911 | &omap2420_timer1_hwmod, | |
1912 | &omap2420_timer2_hwmod, | |
1913 | &omap2420_timer3_hwmod, | |
1914 | &omap2420_timer4_hwmod, | |
1915 | &omap2420_timer5_hwmod, | |
1916 | &omap2420_timer6_hwmod, | |
1917 | &omap2420_timer7_hwmod, | |
1918 | &omap2420_timer8_hwmod, | |
1919 | &omap2420_timer9_hwmod, | |
1920 | &omap2420_timer10_hwmod, | |
1921 | &omap2420_timer11_hwmod, | |
1922 | &omap2420_timer12_hwmod, | |
1923 | ||
a714b9cf | 1924 | &omap2420_wd_timer2_hwmod, |
046465b7 KH |
1925 | &omap2420_uart1_hwmod, |
1926 | &omap2420_uart2_hwmod, | |
1927 | &omap2420_uart3_hwmod, | |
996746ca SG |
1928 | /* dss class */ |
1929 | &omap2420_dss_core_hwmod, | |
1930 | &omap2420_dss_dispc_hwmod, | |
1931 | &omap2420_dss_rfbi_hwmod, | |
1932 | &omap2420_dss_venc_hwmod, | |
1933 | /* i2c class */ | |
2004290f PW |
1934 | &omap2420_i2c1_hwmod, |
1935 | &omap2420_i2c2_hwmod, | |
59c348c3 VC |
1936 | |
1937 | /* gpio class */ | |
1938 | &omap2420_gpio1_hwmod, | |
1939 | &omap2420_gpio2_hwmod, | |
1940 | &omap2420_gpio3_hwmod, | |
1941 | &omap2420_gpio4_hwmod, | |
745685df MK |
1942 | |
1943 | /* dma_system class*/ | |
1944 | &omap2420_dma_system_hwmod, | |
617871de | 1945 | |
fca1ab55 ORL |
1946 | /* mailbox class */ |
1947 | &omap2420_mailbox_hwmod, | |
1948 | ||
3cb72fa4 C |
1949 | /* mcbsp class */ |
1950 | &omap2420_mcbsp1_hwmod, | |
1951 | &omap2420_mcbsp2_hwmod, | |
1952 | ||
617871de C |
1953 | /* mcspi class */ |
1954 | &omap2420_mcspi1_hwmod, | |
1955 | &omap2420_mcspi2_hwmod, | |
02bfc030 PW |
1956 | NULL, |
1957 | }; | |
1958 | ||
7359154e PW |
1959 | int __init omap2420_hwmod_init(void) |
1960 | { | |
550c8092 | 1961 | return omap_hwmod_register(omap2420_hwmods); |
7359154e | 1962 | } |