[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c

/*
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */

#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"

/*
 * OMAP2420 hardware module integration data
 *
 * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

/*
 * IP blocks
 */

/* IVA1 (IVA1) */
static struct omap_hwmod_class iva1_hwmod_class = {
	.name		= "iva1",
};

static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	{ .name = "iva", .rst_shift = 8 },
};

static struct omap_hwmod omap2420_iva_hwmod = {
	.name		= "iva",
	.class		= &iva1_hwmod_class,
	.clkdm_name	= "iva1_clkdm",
	.rst_lines	= omap2420_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
	.main_clk	= "iva1_ifck",
};

/* DSP */
static struct omap_hwmod_class dsp_hwmod_class = {
	.name		= "dsp",
};

static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	{ .name = "logic", .rst_shift = 0 },
	{ .name = "mmu", .rst_shift = 1 },
};

static struct omap_hwmod omap2420_dsp_hwmod = {
	.name		= "dsp",
	.class		= &dsp_hwmod_class,
	.clkdm_name	= "dsp_clkdm",
	.rst_lines	= omap2420_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
	.main_clk	= "dsp_fck",
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
	.rev		= OMAP_I2C_IP_VERSION_1,
	.reset		= &omap_i2c_reset,
};

static struct omap_i2c_dev_attr i2c_dev_attr = {
	.flags		= OMAP_I2C_FLAG_NO_FIFO |
			  OMAP_I2C_FLAG_SIMPLE_CLOCK |
			  OMAP_I2C_FLAG_16BIT_DATA_REG |
			  OMAP_I2C_FLAG_BUS_SHIFT_2,
};

/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
	.name		= "i2c1",
	.mpu_irqs	= omap2_i2c1_mpu_irqs,
	.sdma_reqs	= omap2_i2c1_sdma_reqs,
	.main_clk	= "i2c1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	/*
	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	 * while a transfer is active seems to cause the I2C block to
	 * timeout. Why? Good question."
	 */
	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
};

/* I2C2 */
static struct omap_hwmod omap2420_i2c2_hwmod = {
	.name		= "i2c2",
	.mpu_irqs	= omap2_i2c2_mpu_irqs,
	.sdma_reqs	= omap2_i2c2_sdma_reqs,
	.main_clk	= "i2c2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_I2C2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
		},
	},
	.class		= &i2c_class,
	.dev_attr	= &i2c_dev_attr,
	.flags		= HWMOD_16BIT_REG,
};

/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
						IS_CSSA_32 | IS_CDSA_32,
	.lch_count = 32,
};

static struct omap_hwmod omap2420_dma_system_hwmod = {
	.name		= "dma",
	.class		= &omap2xxx_dma_hwmod_class,
	.mpu_irqs	= omap2_dma_system_irqs,
	.main_clk	= "core_l3_ck",
	.dev_attr	= &dma_dev_attr,
	.flags		= HWMOD_NO_IDLEST,
};

/* mailbox */
static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
	{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
	{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
};

static struct omap_mbox_pdata omap2420_mailbox_attrs = {
	.info_cnt	= ARRAY_SIZE(omap2420_mailbox_info),
	.info		= omap2420_mailbox_info,
};

static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap2xxx_mailbox_hwmod_class,
	.mpu_irqs	= omap2420_mailbox_irqs,
	.main_clk	= "mailboxes_ick",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
		},
	},
	.dev_attr	= &omap2420_mailbox_attrs,
};

/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	.name = "mcbsp",
};

static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	{ .role = "prcm_fck", .clk = "func_96m_ck" },
};

/* mcbsp1 */
static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
	{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
	{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap2420_mcbsp_hwmod_class,
	.mpu_irqs	= omap2420_mcbsp1_irqs,
	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
	.main_clk	= "mcbsp1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

/* mcbsp2 */
static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
	{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
	{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap2420_mcbsp_hwmod_class,
	.mpu_irqs	= omap2420_mcbsp2_irqs,
	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
	.main_clk	= "mcbsp2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	.rev_offs	= 0x3c,
	.sysc_offs	= 0x64,
	.syss_offs	= 0x68,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	.name	= "msdi",
	.sysc	= &omap2420_msdi_sysc,
	.reset	= &omap_msdi_reset,
};

/* msdi1 */
static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
	{ .irq = 83 + OMAP_INTC_START, },
	{ .irq = -1 },
};

static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
	{ .dma_req = -1 }
};

static struct omap_hwmod omap2420_msdi1_hwmod = {
	.name		= "msdi1",
	.class		= &omap2420_msdi_hwmod_class,
	.mpu_irqs	= omap2420_msdi1_irqs,
	.sdma_reqs	= omap2420_msdi1_sdma_reqs,
	.main_clk	= "mmc_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP2420_EN_MMC_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
		},
	},
	.flags		= HWMOD_16BIT_REG,
};

/* HDQ1W/1-wire */
static struct omap_hwmod omap2420_hdq1w_hwmod = {
	.name		= "hdq1w",
	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
	.main_clk	= "hdq_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
		},
	},
	.class		= &omap2_hdq1w_class,
};

/*
 * interfaces
 */

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.addr		= omap2_i2c1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.addr		= omap2_i2c2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* IVA <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__iva = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_iva_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* DSP <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_dsp_hwmod,
	.clk		= "dsp_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
	{
		.pa_start	= 0x48028000,
		.pa_end		= 0x48028000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_timer1_hwmod,
	.clk		= "gpt1_ick",
	.addr		= omap2420_timer1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
	{
		.pa_start	= 0x48022000,
		.pa_end		= 0x4802207f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.addr		= omap2420_wd_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
	{
		.pa_start	= 0x48018000,
		.pa_end		= 0x480181ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio1_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio2 */
static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
	{
		.pa_start	= 0x4801a000,
		.pa_end		= 0x4801a1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio2_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio3 */
static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
	{
		.pa_start	= 0x4801c000,
		.pa_end		= 0x4801c1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio3_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio3_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio4 */
static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
	{
		.pa_start	= 0x4801e000,
		.pa_end		= 0x4801e1ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio4_hwmod,
	.clk		= "gpios_ick",
	.addr		= omap2420_gpio4_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	.master		= &omap2420_dma_system_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_dma_system_hwmod,
	.clk		= "sdma_ick",
	.addr		= omap2_dma_system_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mailbox_hwmod,
	.addr		= omap2_mailbox_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp1_hwmod,
	.clk		= "mcbsp1_ick",
	.addr		= omap2_mcbsp1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp2_hwmod,
	.clk		= "mcbsp2_ick",
	.addr		= omap2xxx_mcbsp2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
	{
		.pa_start	= 0x4809c000,
		.pa_end		= 0x4809c000 + SZ_128 - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

/* l4_core -> msdi1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_msdi1_hwmod,
	.clk		= "mmc_ick",
	.addr		= omap2420_msdi1_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> hdq1w interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_hdq1w_hwmod,
	.clk		= "hdq_ick",
	.addr		= omap2_hdq1w_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};


/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
	{
		.pa_start	= 0x48004000,
		.pa_end		= 0x4800401f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
	{
		.pa_start	= 0x6800a000,
		.pa_end		= 0x6800afff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_counter_32k_hwmod,
	.clk		= "sync_32k_ick",
	.addr		= omap2420_counter_32k_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2xxx_gpmc_hwmod,
	.clk		= "core_l3_ck",
	.addr		= omap2420_gpmc_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
	&omap2xxx_l3_main__l4_core,
	&omap2xxx_mpu__l3_main,
	&omap2xxx_dss__l3,
	&omap2xxx_l4_core__mcspi1,
	&omap2xxx_l4_core__mcspi2,
	&omap2xxx_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
	&omap2420_l4_core__i2c1,
	&omap2420_l4_core__i2c2,
	&omap2420_l3__iva,
	&omap2420_l3__dsp,
	&omap2420_l4_wkup__timer1,
	&omap2xxx_l4_core__timer2,
	&omap2xxx_l4_core__timer3,
	&omap2xxx_l4_core__timer4,
	&omap2xxx_l4_core__timer5,
	&omap2xxx_l4_core__timer6,
	&omap2xxx_l4_core__timer7,
	&omap2xxx_l4_core__timer8,
	&omap2xxx_l4_core__timer9,
	&omap2xxx_l4_core__timer10,
	&omap2xxx_l4_core__timer11,
	&omap2xxx_l4_core__timer12,
	&omap2420_l4_wkup__wd_timer2,
	&omap2xxx_l4_core__dss,
	&omap2xxx_l4_core__dss_dispc,
	&omap2xxx_l4_core__dss_rfbi,
	&omap2xxx_l4_core__dss_venc,
	&omap2420_l4_wkup__gpio1,
	&omap2420_l4_wkup__gpio2,
	&omap2420_l4_wkup__gpio3,
	&omap2420_l4_wkup__gpio4,
	&omap2420_dma_system__l3,
	&omap2420_l4_core__dma_system,
	&omap2420_l4_core__mailbox,
	&omap2420_l4_core__mcbsp1,
	&omap2420_l4_core__mcbsp2,
	&omap2420_l4_core__msdi1,
	&omap2xxx_l4_core__rng,
	&omap2xxx_l4_core__sham,
	&omap2xxx_l4_core__aes,
	&omap2420_l4_core__hdq1w,
	&omap2420_l4_wkup__counter_32k,
	&omap2420_l3__gpmc,
	NULL,
};

int __init omap2420_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
Commit	Line	Data
02bfc030	1	/*
7359154e	2	* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
02bfc030	3	*
78183f3f	4	* Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5	5	* Copyright (C) 2012 Texas Instruments, Inc.
02bfc030 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* XXX handle crossbar/shared link difference for L3?
7359154e	13	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	14	*/
3a8761c0 TL	15
3a8761c0 TL	16	#include <linux/i2c-omap.h>
2203747c	17	#include <linux/platform_data/spi-omap2-mcspi.h>
45c3eb7d	18	#include <linux/omap-dma.h>
b8a7cf8e	19	#include <linux/platform_data/mailbox-omap.h>
eddb1262	20	#include <plat/dmtimer.h>
2a296c8f TL	21
2a296c8f TL	22	#include "omap_hwmod.h"
1e0f51a9	23	#include "l3_2xxx.h"
70606b1c	24	#include "l4_2xxx.h"
02bfc030	25
43b40992 PW	26	#include "omap_hwmod_common_data.h"
43b40992 PW	27
a714b9cf	28	#include "cm-regbits-24xx.h"
2004290f	29	#include "prm-regbits-24xx.h"
3a8761c0	30	#include "i2c.h"
68f39e74	31	#include "mmc.h"
3d82cbbb	32	#include "serial.h"
ff2516fb	33	#include "wd_timer.h"
02bfc030	34
7359154e PW	35	/*
	36	* OMAP2420 hardware module integration data
	37	*
844a3b63	38	* All of the data in this section should be autogeneratable from the
7359154e PW	39	* TI hardware database or other technical documentation. Data that
	40	* is driver-specific or driver-kernel integration-specific belongs
	41	* elsewhere.
	42	*/
	43
844a3b63 PW	44	/*
	45	* IP blocks
	46	*/
996746ca	47
3af35fbc PW	48	/* IVA1 (IVA1) */
	49	static struct omap_hwmod_class iva1_hwmod_class = {
	50	.name = "iva1",
	51	};
	52
	53	static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	54	{ .name = "iva", .rst_shift = 8 },
	55	};
	56
08072acf PW	57	static struct omap_hwmod omap2420_iva_hwmod = {
08072acf PW	58	.name = "iva",
3af35fbc PW	59	.class = &iva1_hwmod_class,
	60	.clkdm_name = "iva1_clkdm",
	61	.rst_lines = omap2420_iva_resets,
	62	.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
	63	.main_clk = "iva1_ifck",
	64	};
	65
	66	/* DSP */
	67	static struct omap_hwmod_class dsp_hwmod_class = {
	68	.name = "dsp",
	69	};
	70
	71	static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	72	{ .name = "logic", .rst_shift = 0 },
	73	{ .name = "mmu", .rst_shift = 1 },
	74	};
	75
	76	static struct omap_hwmod omap2420_dsp_hwmod = {
	77	.name = "dsp",
	78	.class = &dsp_hwmod_class,
	79	.clkdm_name = "dsp_clkdm",
	80	.rst_lines = omap2420_dsp_resets,
	81	.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
	82	.main_clk = "dsp_fck",
08072acf PW	83	};
08072acf PW	84
2004290f PW	85	/* I2C common */
	86	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	87	.rev_offs = 0x00,
	88	.sysc_offs = 0x20,
	89	.syss_offs = 0x10,
d73d65fa	90	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
2004290f PW	91	.sysc_fields = &omap_hwmod_sysc_type1,
	92	};
	93
	94	static struct omap_hwmod_class i2c_class = {
	95	.name = "i2c",
	96	.sysc = &i2c_sysc,
db791a75	97	.rev = OMAP_I2C_IP_VERSION_1,
6d3c55fd	98	.reset = &omap_i2c_reset,
2004290f PW	99	};
2004290f PW	100
4d4441a6 AG	101	static struct omap_i2c_dev_attr i2c_dev_attr = {
	102	.flags = OMAP_I2C_FLAG_NO_FIFO \|
	103	OMAP_I2C_FLAG_SIMPLE_CLOCK \|
	104	OMAP_I2C_FLAG_16BIT_DATA_REG \|
	105	OMAP_I2C_FLAG_BUS_SHIFT_2,
	106	};
2004290f PW	107
2004290f PW	108	/* I2C1 */
2004290f PW	109	static struct omap_hwmod omap2420_i2c1_hwmod = {
2004290f PW	110	.name = "i2c1",
0d619a89	111	.mpu_irqs = omap2_i2c1_mpu_irqs,
d826ebfa	112	.sdma_reqs = omap2_i2c1_sdma_reqs,
2004290f PW	113	.main_clk = "i2c1_fck",
	114	.prcm = {
	115	.omap2 = {
	116	.module_offs = CORE_MOD,
	117	.prcm_reg_id = 1,
	118	.module_bit = OMAP2420_EN_I2C1_SHIFT,
	119	.idlest_reg_id = 1,
	120	.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
	121	},
	122	},
2004290f PW	123	.class = &i2c_class,
2004290f PW	124	.dev_attr = &i2c_dev_attr,
aff2f7d9 PW	125	/*
	126	* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	127	* while a transfer is active seems to cause the I2C block to
	128	* timeout. Why? Good question."
	129	*/
	130	.flags = (HWMOD_16BIT_REG \| HWMOD_BLOCK_WFI),
2004290f PW	131	};
	132
	133	/* I2C2 */
2004290f PW	134	static struct omap_hwmod omap2420_i2c2_hwmod = {
2004290f PW	135	.name = "i2c2",
0d619a89	136	.mpu_irqs = omap2_i2c2_mpu_irqs,
d826ebfa	137	.sdma_reqs = omap2_i2c2_sdma_reqs,
2004290f PW	138	.main_clk = "i2c2_fck",
	139	.prcm = {
	140	.omap2 = {
	141	.module_offs = CORE_MOD,
	142	.prcm_reg_id = 1,
	143	.module_bit = OMAP2420_EN_I2C2_SHIFT,
	144	.idlest_reg_id = 1,
	145	.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
	146	},
	147	},
2004290f PW	148	.class = &i2c_class,
2004290f PW	149	.dev_attr = &i2c_dev_attr,
2004290f PW	150	.flags = HWMOD_16BIT_REG,
	151	};
	152
745685df MK	153	/* dma attributes */
	154	static struct omap_dma_dev_attr dma_dev_attr = {
	155	.dev_caps = RESERVE_CHANNEL \| DMA_LINKED_LCH \| GLOBAL_PRIORITY \|
	156	IS_CSSA_32 \| IS_CDSA_32,
	157	.lch_count = 32,
	158	};
	159
745685df MK	160	static struct omap_hwmod omap2420_dma_system_hwmod = {
745685df MK	161	.name = "dma",
273b9465	162	.class = &omap2xxx_dma_hwmod_class,
0d619a89	163	.mpu_irqs = omap2_dma_system_irqs,
745685df	164	.main_clk = "core_l3_ck",
745685df	165	.dev_attr = &dma_dev_attr,
745685df MK	166	.flags = HWMOD_NO_IDLEST,
	167	};
	168
fca1ab55	169	/* mailbox */
b8a7cf8e SA	170	static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
	171	{ .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
	172	{ .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
	173	};
	174
	175	static struct omap_mbox_pdata omap2420_mailbox_attrs = {
	176	.info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
	177	.info = omap2420_mailbox_info,
	178	};
	179
fca1ab55	180	static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
7d7e1eba TL	181	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
	182	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
	183	{ .irq = -1 },
fca1ab55 ORL	184	};
fca1ab55 ORL	185
fca1ab55 ORL	186	static struct omap_hwmod omap2420_mailbox_hwmod = {
fca1ab55 ORL	187	.name = "mailbox",
273b9465	188	.class = &omap2xxx_mailbox_hwmod_class,
fca1ab55	189	.mpu_irqs = omap2420_mailbox_irqs,
fca1ab55 ORL	190	.main_clk = "mailboxes_ick",
	191	.prcm = {
	192	.omap2 = {
	193	.prcm_reg_id = 1,
	194	.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
	195	.module_offs = CORE_MOD,
	196	.idlest_reg_id = 1,
	197	.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
	198	},
	199	},
b8a7cf8e	200	.dev_attr = &omap2420_mailbox_attrs,
fca1ab55 ORL	201	};
fca1ab55 ORL	202
3cb72fa4 C	203	/*
	204	* 'mcbsp' class
	205	* multi channel buffered serial port controller
	206	*/
	207
	208	static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	209	.name = "mcbsp",
	210	};
	211
b3153100 PU	212	static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	213	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	214	{ .role = "prcm_fck", .clk = "func_96m_ck" },
	215	};
	216
3cb72fa4 C	217	/* mcbsp1 */
3cb72fa4 C	218	static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
7d7e1eba TL	219	{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
	220	{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
	221	{ .irq = -1 },
3cb72fa4 C	222	};
3cb72fa4 C	223
3cb72fa4 C	224	static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	225	.name = "mcbsp1",
	226	.class = &omap2420_mcbsp_hwmod_class,
	227	.mpu_irqs = omap2420_mcbsp1_irqs,
d826ebfa	228	.sdma_reqs = omap2_mcbsp1_sdma_reqs,
3cb72fa4 C	229	.main_clk = "mcbsp1_fck",
	230	.prcm = {
	231	.omap2 = {
	232	.prcm_reg_id = 1,
	233	.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
	234	.module_offs = CORE_MOD,
	235	.idlest_reg_id = 1,
	236	.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
	237	},
	238	},
b3153100 PU	239	.opt_clks = mcbsp_opt_clks,
b3153100 PU	240	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
3cb72fa4 C	241	};
	242
	243	/* mcbsp2 */
	244	static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
7d7e1eba TL	245	{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
	246	{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
	247	{ .irq = -1 },
3cb72fa4 C	248	};
3cb72fa4 C	249
3cb72fa4 C	250	static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	251	.name = "mcbsp2",
	252	.class = &omap2420_mcbsp_hwmod_class,
	253	.mpu_irqs = omap2420_mcbsp2_irqs,
d826ebfa	254	.sdma_reqs = omap2_mcbsp2_sdma_reqs,
3cb72fa4 C	255	.main_clk = "mcbsp2_fck",
	256	.prcm = {
	257	.omap2 = {
	258	.prcm_reg_id = 1,
	259	.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
	260	.module_offs = CORE_MOD,
	261	.idlest_reg_id = 1,
	262	.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
	263	},
	264	},
b3153100 PU	265	.opt_clks = mcbsp_opt_clks,
b3153100 PU	266	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
0a78c5c5 PW	267	};
0a78c5c5 PW	268
ad1b6662 TL	269	static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	270	.rev_offs = 0x3c,
	271	.sysc_offs = 0x64,
	272	.syss_offs = 0x68,
	273	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
	274	.sysc_fields = &omap_hwmod_sysc_type1,
	275	};
	276
	277	static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	278	.name = "msdi",
	279	.sysc = &omap2420_msdi_sysc,
	280	.reset = &omap_msdi_reset,
	281	};
	282
	283	/* msdi1 */
	284	static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
7d7e1eba TL	285	{ .irq = 83 + OMAP_INTC_START, },
7d7e1eba TL	286	{ .irq = -1 },
ad1b6662 TL	287	};
	288
	289	static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
	290	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
	291	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
	292	{ .dma_req = -1 }
	293	};
	294
	295	static struct omap_hwmod omap2420_msdi1_hwmod = {
	296	.name = "msdi1",
	297	.class = &omap2420_msdi_hwmod_class,
	298	.mpu_irqs = omap2420_msdi1_irqs,
	299	.sdma_reqs = omap2420_msdi1_sdma_reqs,
	300	.main_clk = "mmc_fck",
	301	.prcm = {
	302	.omap2 = {
	303	.prcm_reg_id = 1,
	304	.module_bit = OMAP2420_EN_MMC_SHIFT,
	305	.module_offs = CORE_MOD,
	306	.idlest_reg_id = 1,
	307	.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
	308	},
	309	},
	310	.flags = HWMOD_16BIT_REG,
	311	};
	312
f32bd778 PW	313	/* HDQ1W/1-wire */
	314	static struct omap_hwmod omap2420_hdq1w_hwmod = {
	315	.name = "hdq1w",
	316	.mpu_irqs = omap2_hdq1w_mpu_irqs,
	317	.main_clk = "hdq_fck",
	318	.prcm = {
	319	.omap2 = {
	320	.module_offs = CORE_MOD,
	321	.prcm_reg_id = 1,
	322	.module_bit = OMAP24XX_EN_HDQ_SHIFT,
	323	.idlest_reg_id = 1,
	324	.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
	325	},
	326	},
	327	.class = &omap2_hdq1w_class,
	328	};
	329
844a3b63 PW	330	/*
	331	* interfaces
	332	*/
	333
844a3b63 PW	334	/* L4 CORE -> I2C1 interface */
844a3b63 PW	335	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
cb48427e	336	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	337	.slave = &omap2420_i2c1_hwmod,
	338	.clk = "i2c1_ick",
	339	.addr = omap2_i2c1_addr_space,
	340	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	341	};
	342
	343	/* L4 CORE -> I2C2 interface */
	344	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
cb48427e	345	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	346	.slave = &omap2420_i2c2_hwmod,
	347	.clk = "i2c2_ick",
	348	.addr = omap2_i2c2_addr_space,
	349	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	350	};
	351
	352	/* IVA <- L3 interface */
	353	static struct omap_hwmod_ocp_if omap2420_l3__iva = {
cb48427e	354	.master = &omap2xxx_l3_main_hwmod,
844a3b63	355	.slave = &omap2420_iva_hwmod,
3af35fbc PW	356	.clk = "core_l3_ck",
	357	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	358	};
	359
	360	/* DSP <- L3 interface */
	361	static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	362	.master = &omap2xxx_l3_main_hwmod,
	363	.slave = &omap2420_dsp_hwmod,
	364	.clk = "dsp_ick",
844a3b63 PW	365	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	366	};
	367
	368	static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
	369	{
	370	.pa_start = 0x48028000,
	371	.pa_end = 0x48028000 + SZ_1K - 1,
	372	.flags = ADDR_TYPE_RT
	373	},
	374	{ }
	375	};
	376
	377	/* l4_wkup -> timer1 */
	378	static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
cb48427e PW	379	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	380	.slave = &omap2xxx_timer1_hwmod,
844a3b63 PW	381	.clk = "gpt1_ick",
	382	.addr = omap2420_timer1_addrs,
	383	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	384	};
	385
844a3b63 PW	386	/* l4_wkup -> wd_timer2 */
	387	static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
	388	{
	389	.pa_start = 0x48022000,
	390	.pa_end = 0x4802207f,
	391	.flags = ADDR_TYPE_RT
	392	},
	393	{ }
	394	};
	395
	396	static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
cb48427e PW	397	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	398	.slave = &omap2xxx_wd_timer2_hwmod,
844a3b63 PW	399	.clk = "mpu_wdt_ick",
	400	.addr = omap2420_wd_timer2_addrs,
	401	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	402	};
	403
844a3b63 PW	404	/* l4_wkup -> gpio1 */
	405	static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
	406	{
	407	.pa_start = 0x48018000,
	408	.pa_end = 0x480181ff,
	409	.flags = ADDR_TYPE_RT
	410	},
	411	{ }
	412	};
	413
	414	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
cb48427e PW	415	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	416	.slave = &omap2xxx_gpio1_hwmod,
844a3b63 PW	417	.clk = "gpios_ick",
	418	.addr = omap2420_gpio1_addr_space,
	419	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	420	};
	421
	422	/* l4_wkup -> gpio2 */
	423	static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
	424	{
	425	.pa_start = 0x4801a000,
	426	.pa_end = 0x4801a1ff,
	427	.flags = ADDR_TYPE_RT
	428	},
	429	{ }
	430	};
	431
	432	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
cb48427e PW	433	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	434	.slave = &omap2xxx_gpio2_hwmod,
844a3b63 PW	435	.clk = "gpios_ick",
	436	.addr = omap2420_gpio2_addr_space,
	437	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	438	};
	439
	440	/* l4_wkup -> gpio3 */
	441	static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
	442	{
	443	.pa_start = 0x4801c000,
	444	.pa_end = 0x4801c1ff,
	445	.flags = ADDR_TYPE_RT
	446	},
	447	{ }
	448	};
	449
	450	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
cb48427e PW	451	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	452	.slave = &omap2xxx_gpio3_hwmod,
844a3b63 PW	453	.clk = "gpios_ick",
	454	.addr = omap2420_gpio3_addr_space,
	455	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	456	};
	457
	458	/* l4_wkup -> gpio4 */
	459	static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
	460	{
	461	.pa_start = 0x4801e000,
	462	.pa_end = 0x4801e1ff,
	463	.flags = ADDR_TYPE_RT
	464	},
	465	{ }
	466	};
	467
	468	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
cb48427e PW	469	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	470	.slave = &omap2xxx_gpio4_hwmod,
844a3b63 PW	471	.clk = "gpios_ick",
	472	.addr = omap2420_gpio4_addr_space,
	473	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	474	};
	475
	476	/* dma_system -> L3 */
	477	static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	478	.master = &omap2420_dma_system_hwmod,
cb48427e	479	.slave = &omap2xxx_l3_main_hwmod,
844a3b63 PW	480	.clk = "core_l3_ck",
	481	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	482	};
	483
	484	/* l4_core -> dma_system */
	485	static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
cb48427e	486	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	487	.slave = &omap2420_dma_system_hwmod,
	488	.clk = "sdma_ick",
	489	.addr = omap2_dma_system_addrs,
	490	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	491	};
	492
	493	/* l4_core -> mailbox */
	494	static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
cb48427e	495	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	496	.slave = &omap2420_mailbox_hwmod,
	497	.addr = omap2_mailbox_addrs,
	498	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	499	};
	500
	501	/* l4_core -> mcbsp1 */
	502	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
cb48427e	503	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	504	.slave = &omap2420_mcbsp1_hwmod,
	505	.clk = "mcbsp1_ick",
	506	.addr = omap2_mcbsp1_addrs,
	507	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	508	};
	509
	510	/* l4_core -> mcbsp2 */
	511	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
cb48427e	512	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	513	.slave = &omap2420_mcbsp2_hwmod,
	514	.clk = "mcbsp2_ick",
	515	.addr = omap2xxx_mcbsp2_addrs,
	516	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	517	};
	518
ad1b6662 TL	519	static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
	520	{
	521	.pa_start = 0x4809c000,
	522	.pa_end = 0x4809c000 + SZ_128 - 1,
	523	.flags = ADDR_TYPE_RT,
	524	},
	525	{ }
	526	};
	527
	528	/* l4_core -> msdi1 */
	529	static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	530	.master = &omap2xxx_l4_core_hwmod,
	531	.slave = &omap2420_msdi1_hwmod,
	532	.clk = "mmc_ick",
	533	.addr = omap2420_msdi1_addrs,
	534	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	535	};
	536
f32bd778 PW	537	/* l4_core -> hdq1w interface */
	538	static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	539	.master = &omap2xxx_l4_core_hwmod,
	540	.slave = &omap2420_hdq1w_hwmod,
	541	.clk = "hdq_ick",
	542	.addr = omap2_hdq1w_addr_space,
	543	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	544	.flags = OMAP_FIREWALL_L4 \| OCPIF_SWSUP_IDLE,
	545	};
	546
	547
c8d82ff6 VH	548	/* l4_wkup -> 32ksync_counter */
	549	static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
	550	{
	551	.pa_start = 0x48004000,
	552	.pa_end = 0x4800401f,
	553	.flags = ADDR_TYPE_RT
	554	},
	555	{ }
	556	};
	557
49484a60 AM	558	static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
	559	{
	560	.pa_start = 0x6800a000,
	561	.pa_end = 0x6800afff,
	562	.flags = ADDR_TYPE_RT
	563	},
	564	{ }
	565	};
	566
c8d82ff6 VH	567	static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	568	.master = &omap2xxx_l4_wkup_hwmod,
	569	.slave = &omap2xxx_counter_32k_hwmod,
	570	.clk = "sync_32k_ick",
	571	.addr = omap2420_counter_32k_addrs,
	572	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	573	};
	574
49484a60 AM	575	static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	576	.master = &omap2xxx_l3_main_hwmod,
	577	.slave = &omap2xxx_gpmc_hwmod,
	578	.clk = "core_l3_ck",
	579	.addr = omap2420_gpmc_addrs,
	580	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	581	};
	582
0a78c5c5	583	static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
6a29755f PW	584	&omap2xxx_l3_main__l4_core,
	585	&omap2xxx_mpu__l3_main,
	586	&omap2xxx_dss__l3,
	587	&omap2xxx_l4_core__mcspi1,
	588	&omap2xxx_l4_core__mcspi2,
	589	&omap2xxx_l4_core__l4_wkup,
0a78c5c5 PW	590	&omap2_l4_core__uart1,
	591	&omap2_l4_core__uart2,
	592	&omap2_l4_core__uart3,
	593	&omap2420_l4_core__i2c1,
	594	&omap2420_l4_core__i2c2,
	595	&omap2420_l3__iva,
3af35fbc	596	&omap2420_l3__dsp,
0a78c5c5	597	&omap2420_l4_wkup__timer1,
6a29755f PW	598	&omap2xxx_l4_core__timer2,
	599	&omap2xxx_l4_core__timer3,
	600	&omap2xxx_l4_core__timer4,
	601	&omap2xxx_l4_core__timer5,
	602	&omap2xxx_l4_core__timer6,
	603	&omap2xxx_l4_core__timer7,
	604	&omap2xxx_l4_core__timer8,
	605	&omap2xxx_l4_core__timer9,
	606	&omap2xxx_l4_core__timer10,
	607	&omap2xxx_l4_core__timer11,
	608	&omap2xxx_l4_core__timer12,
0a78c5c5	609	&omap2420_l4_wkup__wd_timer2,
6a29755f PW	610	&omap2xxx_l4_core__dss,
	611	&omap2xxx_l4_core__dss_dispc,
	612	&omap2xxx_l4_core__dss_rfbi,
	613	&omap2xxx_l4_core__dss_venc,
0a78c5c5 PW	614	&omap2420_l4_wkup__gpio1,
	615	&omap2420_l4_wkup__gpio2,
	616	&omap2420_l4_wkup__gpio3,
	617	&omap2420_l4_wkup__gpio4,
	618	&omap2420_dma_system__l3,
	619	&omap2420_l4_core__dma_system,
	620	&omap2420_l4_core__mailbox,
	621	&omap2420_l4_core__mcbsp1,
	622	&omap2420_l4_core__mcbsp2,
ad1b6662	623	&omap2420_l4_core__msdi1,
e9b0a2fb	624	&omap2xxx_l4_core__rng,
e569e994	625	&omap2xxx_l4_core__sham,
660ffd6b	626	&omap2xxx_l4_core__aes,
f32bd778	627	&omap2420_l4_core__hdq1w,
c8d82ff6	628	&omap2420_l4_wkup__counter_32k,
49484a60	629	&omap2420_l3__gpmc,
02bfc030 PW	630	NULL,
	631	};
	632
7359154e PW	633	int __init omap2420_hwmod_init(void)
7359154e PW	634	{
9ebfd285	635	omap_hwmod_init();
0a78c5c5	636	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
7359154e	637	}