Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
ce491cf8 | 15 | #include <plat/omap_hwmod.h> |
02bfc030 | 16 | #include <mach/irqs.h> |
ce491cf8 TL |
17 | #include <plat/cpu.h> |
18 | #include <plat/dma.h> | |
046465b7 | 19 | #include <plat/serial.h> |
2004290f | 20 | #include <plat/i2c.h> |
59c348c3 | 21 | #include <plat/gpio.h> |
617871de | 22 | #include <plat/mcspi.h> |
eddb1262 | 23 | #include <plat/dmtimer.h> |
996746ca SG |
24 | #include <plat/l3_2xxx.h> |
25 | #include <plat/l4_2xxx.h> | |
02bfc030 | 26 | |
43b40992 PW |
27 | #include "omap_hwmod_common_data.h" |
28 | ||
a714b9cf | 29 | #include "cm-regbits-24xx.h" |
2004290f | 30 | #include "prm-regbits-24xx.h" |
ff2516fb | 31 | #include "wd_timer.h" |
02bfc030 | 32 | |
7359154e PW |
33 | /* |
34 | * OMAP2420 hardware module integration data | |
35 | * | |
844a3b63 | 36 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
37 | * TI hardware database or other technical documentation. Data that |
38 | * is driver-specific or driver-kernel integration-specific belongs | |
39 | * elsewhere. | |
40 | */ | |
41 | ||
844a3b63 PW |
42 | /* |
43 | * IP blocks | |
44 | */ | |
996746ca | 45 | |
844a3b63 | 46 | /* IVA2 (IVA2) */ |
08072acf PW |
47 | static struct omap_hwmod omap2420_iva_hwmod = { |
48 | .name = "iva", | |
49 | .class = &iva_hwmod_class, | |
08072acf PW |
50 | }; |
51 | ||
2004290f PW |
52 | /* I2C common */ |
53 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
54 | .rev_offs = 0x00, | |
55 | .sysc_offs = 0x20, | |
56 | .syss_offs = 0x10, | |
d73d65fa | 57 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
2004290f PW |
58 | .sysc_fields = &omap_hwmod_sysc_type1, |
59 | }; | |
60 | ||
61 | static struct omap_hwmod_class i2c_class = { | |
62 | .name = "i2c", | |
63 | .sysc = &i2c_sysc, | |
db791a75 | 64 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 65 | .reset = &omap_i2c_reset, |
2004290f PW |
66 | }; |
67 | ||
4d4441a6 AG |
68 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
69 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
70 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
71 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
72 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
73 | }; | |
2004290f PW |
74 | |
75 | /* I2C1 */ | |
2004290f PW |
76 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
77 | .name = "i2c1", | |
0d619a89 | 78 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 79 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
80 | .main_clk = "i2c1_fck", |
81 | .prcm = { | |
82 | .omap2 = { | |
83 | .module_offs = CORE_MOD, | |
84 | .prcm_reg_id = 1, | |
85 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | |
86 | .idlest_reg_id = 1, | |
87 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | |
88 | }, | |
89 | }, | |
2004290f PW |
90 | .class = &i2c_class, |
91 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
92 | .flags = HWMOD_16BIT_REG, |
93 | }; | |
94 | ||
95 | /* I2C2 */ | |
2004290f PW |
96 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
97 | .name = "i2c2", | |
0d619a89 | 98 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 99 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
100 | .main_clk = "i2c2_fck", |
101 | .prcm = { | |
102 | .omap2 = { | |
103 | .module_offs = CORE_MOD, | |
104 | .prcm_reg_id = 1, | |
105 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | |
106 | .idlest_reg_id = 1, | |
107 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | |
108 | }, | |
109 | }, | |
2004290f PW |
110 | .class = &i2c_class, |
111 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
112 | .flags = HWMOD_16BIT_REG, |
113 | }; | |
114 | ||
745685df MK |
115 | /* dma attributes */ |
116 | static struct omap_dma_dev_attr dma_dev_attr = { | |
117 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
118 | IS_CSSA_32 | IS_CDSA_32, | |
119 | .lch_count = 32, | |
120 | }; | |
121 | ||
745685df MK |
122 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
123 | .name = "dma", | |
273b9465 | 124 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 125 | .mpu_irqs = omap2_dma_system_irqs, |
745685df | 126 | .main_clk = "core_l3_ck", |
745685df | 127 | .dev_attr = &dma_dev_attr, |
745685df MK |
128 | .flags = HWMOD_NO_IDLEST, |
129 | }; | |
130 | ||
fca1ab55 | 131 | /* mailbox */ |
fca1ab55 ORL |
132 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
133 | { .name = "dsp", .irq = 26 }, | |
134 | { .name = "iva", .irq = 34 }, | |
212738a4 | 135 | { .irq = -1 } |
fca1ab55 ORL |
136 | }; |
137 | ||
fca1ab55 ORL |
138 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
139 | .name = "mailbox", | |
273b9465 | 140 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 141 | .mpu_irqs = omap2420_mailbox_irqs, |
fca1ab55 ORL |
142 | .main_clk = "mailboxes_ick", |
143 | .prcm = { | |
144 | .omap2 = { | |
145 | .prcm_reg_id = 1, | |
146 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
147 | .module_offs = CORE_MOD, | |
148 | .idlest_reg_id = 1, | |
149 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
150 | }, | |
151 | }, | |
fca1ab55 ORL |
152 | }; |
153 | ||
3cb72fa4 C |
154 | /* |
155 | * 'mcbsp' class | |
156 | * multi channel buffered serial port controller | |
157 | */ | |
158 | ||
159 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |
160 | .name = "mcbsp", | |
161 | }; | |
162 | ||
163 | /* mcbsp1 */ | |
164 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | |
165 | { .name = "tx", .irq = 59 }, | |
166 | { .name = "rx", .irq = 60 }, | |
212738a4 | 167 | { .irq = -1 } |
3cb72fa4 C |
168 | }; |
169 | ||
3cb72fa4 C |
170 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
171 | .name = "mcbsp1", | |
172 | .class = &omap2420_mcbsp_hwmod_class, | |
173 | .mpu_irqs = omap2420_mcbsp1_irqs, | |
d826ebfa | 174 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
3cb72fa4 C |
175 | .main_clk = "mcbsp1_fck", |
176 | .prcm = { | |
177 | .omap2 = { | |
178 | .prcm_reg_id = 1, | |
179 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
180 | .module_offs = CORE_MOD, | |
181 | .idlest_reg_id = 1, | |
182 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
183 | }, | |
184 | }, | |
3cb72fa4 C |
185 | }; |
186 | ||
187 | /* mcbsp2 */ | |
188 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | |
189 | { .name = "tx", .irq = 62 }, | |
190 | { .name = "rx", .irq = 63 }, | |
212738a4 | 191 | { .irq = -1 } |
3cb72fa4 C |
192 | }; |
193 | ||
3cb72fa4 C |
194 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
195 | .name = "mcbsp2", | |
196 | .class = &omap2420_mcbsp_hwmod_class, | |
197 | .mpu_irqs = omap2420_mcbsp2_irqs, | |
d826ebfa | 198 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
3cb72fa4 C |
199 | .main_clk = "mcbsp2_fck", |
200 | .prcm = { | |
201 | .omap2 = { | |
202 | .prcm_reg_id = 1, | |
203 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
204 | .module_offs = CORE_MOD, | |
205 | .idlest_reg_id = 1, | |
206 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
207 | }, | |
208 | }, | |
0a78c5c5 PW |
209 | }; |
210 | ||
844a3b63 PW |
211 | /* |
212 | * interfaces | |
213 | */ | |
214 | ||
844a3b63 PW |
215 | /* L4 CORE -> I2C1 interface */ |
216 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { | |
cb48427e | 217 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
218 | .slave = &omap2420_i2c1_hwmod, |
219 | .clk = "i2c1_ick", | |
220 | .addr = omap2_i2c1_addr_space, | |
221 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
222 | }; | |
223 | ||
224 | /* L4 CORE -> I2C2 interface */ | |
225 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { | |
cb48427e | 226 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
227 | .slave = &omap2420_i2c2_hwmod, |
228 | .clk = "i2c2_ick", | |
229 | .addr = omap2_i2c2_addr_space, | |
230 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
231 | }; | |
232 | ||
233 | /* IVA <- L3 interface */ | |
234 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | |
cb48427e | 235 | .master = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
236 | .slave = &omap2420_iva_hwmod, |
237 | .clk = "iva1_ifck", | |
238 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
239 | }; | |
240 | ||
241 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | |
242 | { | |
243 | .pa_start = 0x48028000, | |
244 | .pa_end = 0x48028000 + SZ_1K - 1, | |
245 | .flags = ADDR_TYPE_RT | |
246 | }, | |
247 | { } | |
248 | }; | |
249 | ||
250 | /* l4_wkup -> timer1 */ | |
251 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | |
cb48427e PW |
252 | .master = &omap2xxx_l4_wkup_hwmod, |
253 | .slave = &omap2xxx_timer1_hwmod, | |
844a3b63 PW |
254 | .clk = "gpt1_ick", |
255 | .addr = omap2420_timer1_addrs, | |
256 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
257 | }; | |
258 | ||
844a3b63 PW |
259 | /* l4_wkup -> wd_timer2 */ |
260 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | |
261 | { | |
262 | .pa_start = 0x48022000, | |
263 | .pa_end = 0x4802207f, | |
264 | .flags = ADDR_TYPE_RT | |
265 | }, | |
266 | { } | |
267 | }; | |
268 | ||
269 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { | |
cb48427e PW |
270 | .master = &omap2xxx_l4_wkup_hwmod, |
271 | .slave = &omap2xxx_wd_timer2_hwmod, | |
844a3b63 PW |
272 | .clk = "mpu_wdt_ick", |
273 | .addr = omap2420_wd_timer2_addrs, | |
274 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
275 | }; | |
276 | ||
844a3b63 PW |
277 | /* l4_wkup -> gpio1 */ |
278 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | |
279 | { | |
280 | .pa_start = 0x48018000, | |
281 | .pa_end = 0x480181ff, | |
282 | .flags = ADDR_TYPE_RT | |
283 | }, | |
284 | { } | |
285 | }; | |
286 | ||
287 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | |
cb48427e PW |
288 | .master = &omap2xxx_l4_wkup_hwmod, |
289 | .slave = &omap2xxx_gpio1_hwmod, | |
844a3b63 PW |
290 | .clk = "gpios_ick", |
291 | .addr = omap2420_gpio1_addr_space, | |
292 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
293 | }; | |
294 | ||
295 | /* l4_wkup -> gpio2 */ | |
296 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | |
297 | { | |
298 | .pa_start = 0x4801a000, | |
299 | .pa_end = 0x4801a1ff, | |
300 | .flags = ADDR_TYPE_RT | |
301 | }, | |
302 | { } | |
303 | }; | |
304 | ||
305 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | |
cb48427e PW |
306 | .master = &omap2xxx_l4_wkup_hwmod, |
307 | .slave = &omap2xxx_gpio2_hwmod, | |
844a3b63 PW |
308 | .clk = "gpios_ick", |
309 | .addr = omap2420_gpio2_addr_space, | |
310 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
311 | }; | |
312 | ||
313 | /* l4_wkup -> gpio3 */ | |
314 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | |
315 | { | |
316 | .pa_start = 0x4801c000, | |
317 | .pa_end = 0x4801c1ff, | |
318 | .flags = ADDR_TYPE_RT | |
319 | }, | |
320 | { } | |
321 | }; | |
322 | ||
323 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | |
cb48427e PW |
324 | .master = &omap2xxx_l4_wkup_hwmod, |
325 | .slave = &omap2xxx_gpio3_hwmod, | |
844a3b63 PW |
326 | .clk = "gpios_ick", |
327 | .addr = omap2420_gpio3_addr_space, | |
328 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
329 | }; | |
330 | ||
331 | /* l4_wkup -> gpio4 */ | |
332 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | |
333 | { | |
334 | .pa_start = 0x4801e000, | |
335 | .pa_end = 0x4801e1ff, | |
336 | .flags = ADDR_TYPE_RT | |
337 | }, | |
338 | { } | |
339 | }; | |
340 | ||
341 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | |
cb48427e PW |
342 | .master = &omap2xxx_l4_wkup_hwmod, |
343 | .slave = &omap2xxx_gpio4_hwmod, | |
844a3b63 PW |
344 | .clk = "gpios_ick", |
345 | .addr = omap2420_gpio4_addr_space, | |
346 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
347 | }; | |
348 | ||
349 | /* dma_system -> L3 */ | |
350 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | |
351 | .master = &omap2420_dma_system_hwmod, | |
cb48427e | 352 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
353 | .clk = "core_l3_ck", |
354 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
355 | }; | |
356 | ||
357 | /* l4_core -> dma_system */ | |
358 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | |
cb48427e | 359 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
360 | .slave = &omap2420_dma_system_hwmod, |
361 | .clk = "sdma_ick", | |
362 | .addr = omap2_dma_system_addrs, | |
363 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
364 | }; | |
365 | ||
366 | /* l4_core -> mailbox */ | |
367 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | |
cb48427e | 368 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
369 | .slave = &omap2420_mailbox_hwmod, |
370 | .addr = omap2_mailbox_addrs, | |
371 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
372 | }; | |
373 | ||
374 | /* l4_core -> mcbsp1 */ | |
375 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | |
cb48427e | 376 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
377 | .slave = &omap2420_mcbsp1_hwmod, |
378 | .clk = "mcbsp1_ick", | |
379 | .addr = omap2_mcbsp1_addrs, | |
380 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
381 | }; | |
382 | ||
383 | /* l4_core -> mcbsp2 */ | |
384 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | |
cb48427e | 385 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
386 | .slave = &omap2420_mcbsp2_hwmod, |
387 | .clk = "mcbsp2_ick", | |
388 | .addr = omap2xxx_mcbsp2_addrs, | |
389 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
390 | }; | |
391 | ||
0a78c5c5 | 392 | static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { |
6a29755f PW |
393 | &omap2xxx_l3_main__l4_core, |
394 | &omap2xxx_mpu__l3_main, | |
395 | &omap2xxx_dss__l3, | |
396 | &omap2xxx_l4_core__mcspi1, | |
397 | &omap2xxx_l4_core__mcspi2, | |
398 | &omap2xxx_l4_core__l4_wkup, | |
0a78c5c5 PW |
399 | &omap2_l4_core__uart1, |
400 | &omap2_l4_core__uart2, | |
401 | &omap2_l4_core__uart3, | |
402 | &omap2420_l4_core__i2c1, | |
403 | &omap2420_l4_core__i2c2, | |
404 | &omap2420_l3__iva, | |
405 | &omap2420_l4_wkup__timer1, | |
6a29755f PW |
406 | &omap2xxx_l4_core__timer2, |
407 | &omap2xxx_l4_core__timer3, | |
408 | &omap2xxx_l4_core__timer4, | |
409 | &omap2xxx_l4_core__timer5, | |
410 | &omap2xxx_l4_core__timer6, | |
411 | &omap2xxx_l4_core__timer7, | |
412 | &omap2xxx_l4_core__timer8, | |
413 | &omap2xxx_l4_core__timer9, | |
414 | &omap2xxx_l4_core__timer10, | |
415 | &omap2xxx_l4_core__timer11, | |
416 | &omap2xxx_l4_core__timer12, | |
0a78c5c5 | 417 | &omap2420_l4_wkup__wd_timer2, |
6a29755f PW |
418 | &omap2xxx_l4_core__dss, |
419 | &omap2xxx_l4_core__dss_dispc, | |
420 | &omap2xxx_l4_core__dss_rfbi, | |
421 | &omap2xxx_l4_core__dss_venc, | |
0a78c5c5 PW |
422 | &omap2420_l4_wkup__gpio1, |
423 | &omap2420_l4_wkup__gpio2, | |
424 | &omap2420_l4_wkup__gpio3, | |
425 | &omap2420_l4_wkup__gpio4, | |
426 | &omap2420_dma_system__l3, | |
427 | &omap2420_l4_core__dma_system, | |
428 | &omap2420_l4_core__mailbox, | |
429 | &omap2420_l4_core__mcbsp1, | |
430 | &omap2420_l4_core__mcbsp2, | |
02bfc030 PW |
431 | NULL, |
432 | }; | |
433 | ||
7359154e PW |
434 | int __init omap2420_hwmod_init(void) |
435 | { | |
0a78c5c5 | 436 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
7359154e | 437 | } |