Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
3a8761c0 TL |
15 | |
16 | #include <linux/i2c-omap.h> | |
2203747c AB |
17 | #include <linux/platform_data/asoc-ti-mcbsp.h> |
18 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
45c3eb7d | 19 | #include <linux/omap-dma.h> |
b8a7cf8e | 20 | #include <linux/platform_data/mailbox-omap.h> |
b6b58229 | 21 | #include <plat/dmtimer.h> |
2a296c8f TL |
22 | |
23 | #include "omap_hwmod.h" | |
68f39e74 | 24 | #include "mmc.h" |
1e0f51a9 | 25 | #include "l3_2xxx.h" |
02bfc030 | 26 | |
dbc04161 | 27 | #include "soc.h" |
43b40992 | 28 | #include "omap_hwmod_common_data.h" |
02bfc030 | 29 | #include "prm-regbits-24xx.h" |
165e2161 | 30 | #include "cm-regbits-24xx.h" |
3a8761c0 | 31 | #include "i2c.h" |
ff2516fb | 32 | #include "wd_timer.h" |
02bfc030 | 33 | |
7359154e PW |
34 | /* |
35 | * OMAP2430 hardware module integration data | |
36 | * | |
844a3b63 | 37 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
38 | * TI hardware database or other technical documentation. Data that |
39 | * is driver-specific or driver-kernel integration-specific belongs | |
40 | * elsewhere. | |
41 | */ | |
42 | ||
844a3b63 PW |
43 | /* |
44 | * IP blocks | |
45 | */ | |
de56dbb6 | 46 | |
844a3b63 | 47 | /* IVA2 (IVA2) */ |
3af35fbc PW |
48 | static struct omap_hwmod_rst_info omap2430_iva_resets[] = { |
49 | { .name = "logic", .rst_shift = 0 }, | |
50 | { .name = "mmu", .rst_shift = 1 }, | |
51 | }; | |
52 | ||
08072acf PW |
53 | static struct omap_hwmod omap2430_iva_hwmod = { |
54 | .name = "iva", | |
55 | .class = &iva_hwmod_class, | |
3af35fbc PW |
56 | .clkdm_name = "dsp_clkdm", |
57 | .rst_lines = omap2430_iva_resets, | |
58 | .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), | |
59 | .main_clk = "dsp_fck", | |
08072acf PW |
60 | }; |
61 | ||
2004290f PW |
62 | /* I2C common */ |
63 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
64 | .rev_offs = 0x00, | |
65 | .sysc_offs = 0x20, | |
66 | .syss_offs = 0x10, | |
2d403fe0 PW |
67 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
68 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
69 | .sysc_fields = &omap_hwmod_sysc_type1, |
70 | }; | |
71 | ||
72 | static struct omap_hwmod_class i2c_class = { | |
73 | .name = "i2c", | |
74 | .sysc = &i2c_sysc, | |
db791a75 | 75 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 76 | .reset = &omap_i2c_reset, |
2004290f PW |
77 | }; |
78 | ||
50ebb777 | 79 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f | 80 | .fifo_depth = 8, /* bytes */ |
2c88ab8c | 81 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | |
4d4441a6 | 82 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, |
2004290f PW |
83 | }; |
84 | ||
50ebb777 | 85 | /* I2C1 */ |
2004290f PW |
86 | static struct omap_hwmod omap2430_i2c1_hwmod = { |
87 | .name = "i2c1", | |
3e600522 | 88 | .flags = HWMOD_16BIT_REG, |
2004290f PW |
89 | .main_clk = "i2chs1_fck", |
90 | .prcm = { | |
91 | .omap2 = { | |
92 | /* | |
93 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
94 | * I2CHS IP's do not follow the usual pattern. | |
95 | * prcm_reg_id alone cannot be used to program | |
96 | * the iclk and fclk. Needs to be handled using | |
25985edc | 97 | * additional flags when clk handling is moved |
2004290f PW |
98 | * to hwmod framework. |
99 | */ | |
100 | .module_offs = CORE_MOD, | |
101 | .prcm_reg_id = 1, | |
102 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
103 | .idlest_reg_id = 1, | |
104 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
105 | }, | |
106 | }, | |
2004290f | 107 | .class = &i2c_class, |
50ebb777 | 108 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
109 | }; |
110 | ||
111 | /* I2C2 */ | |
2004290f PW |
112 | static struct omap_hwmod omap2430_i2c2_hwmod = { |
113 | .name = "i2c2", | |
3e600522 | 114 | .flags = HWMOD_16BIT_REG, |
2004290f PW |
115 | .main_clk = "i2chs2_fck", |
116 | .prcm = { | |
117 | .omap2 = { | |
118 | .module_offs = CORE_MOD, | |
119 | .prcm_reg_id = 1, | |
120 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
121 | .idlest_reg_id = 1, | |
122 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
123 | }, | |
124 | }, | |
2004290f | 125 | .class = &i2c_class, |
50ebb777 | 126 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
127 | }; |
128 | ||
aeac0e44 | 129 | /* gpio5 */ |
aeac0e44 VC |
130 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
131 | .name = "gpio5", | |
f95440ca | 132 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 VC |
133 | .main_clk = "gpio5_fck", |
134 | .prcm = { | |
135 | .omap2 = { | |
136 | .prcm_reg_id = 2, | |
137 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
138 | .module_offs = CORE_MOD, | |
139 | .idlest_reg_id = 2, | |
140 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
141 | }, | |
142 | }, | |
273b9465 | 143 | .class = &omap2xxx_gpio_hwmod_class, |
cb48427e | 144 | .dev_attr = &omap2xxx_gpio_dev_attr, |
aeac0e44 VC |
145 | }; |
146 | ||
82cbd1ae MK |
147 | /* dma attributes */ |
148 | static struct omap_dma_dev_attr dma_dev_attr = { | |
149 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
150 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
151 | .lch_count = 32, | |
152 | }; | |
153 | ||
82cbd1ae MK |
154 | static struct omap_hwmod omap2430_dma_system_hwmod = { |
155 | .name = "dma", | |
273b9465 | 156 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 157 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae | 158 | .main_clk = "core_l3_ck", |
82cbd1ae | 159 | .dev_attr = &dma_dev_attr, |
82cbd1ae MK |
160 | .flags = HWMOD_NO_IDLEST, |
161 | }; | |
162 | ||
fca1ab55 | 163 | /* mailbox */ |
b8a7cf8e SA |
164 | static struct omap_mbox_dev_info omap2430_mailbox_info[] = { |
165 | { .name = "dsp", .tx_id = 0, .rx_id = 1 }, | |
166 | }; | |
167 | ||
168 | static struct omap_mbox_pdata omap2430_mailbox_attrs = { | |
fe32c1f6 SA |
169 | .num_users = 4, |
170 | .num_fifos = 6, | |
b8a7cf8e SA |
171 | .info_cnt = ARRAY_SIZE(omap2430_mailbox_info), |
172 | .info = omap2430_mailbox_info, | |
173 | }; | |
174 | ||
fca1ab55 ORL |
175 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
176 | .name = "mailbox", | |
273b9465 | 177 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 ORL |
178 | .main_clk = "mailboxes_ick", |
179 | .prcm = { | |
180 | .omap2 = { | |
181 | .prcm_reg_id = 1, | |
182 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
183 | .module_offs = CORE_MOD, | |
184 | .idlest_reg_id = 1, | |
185 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
186 | }, | |
187 | }, | |
b8a7cf8e | 188 | .dev_attr = &omap2430_mailbox_attrs, |
fca1ab55 ORL |
189 | }; |
190 | ||
7f904c78 | 191 | /* mcspi3 */ |
7f904c78 C |
192 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
193 | .num_chipselect = 2, | |
194 | }; | |
195 | ||
196 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
bec93811 | 197 | .name = "mcspi3", |
7f904c78 C |
198 | .main_clk = "mcspi3_fck", |
199 | .prcm = { | |
200 | .omap2 = { | |
201 | .module_offs = CORE_MOD, | |
202 | .prcm_reg_id = 2, | |
203 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
204 | .idlest_reg_id = 2, | |
205 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
206 | }, | |
207 | }, | |
273b9465 PW |
208 | .class = &omap2xxx_mcspi_class, |
209 | .dev_attr = &omap_mcspi3_dev_attr, | |
7f904c78 C |
210 | }; |
211 | ||
844a3b63 | 212 | /* usbhsotg */ |
44d02acf HH |
213 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
214 | .rev_offs = 0x0400, | |
215 | .sysc_offs = 0x0404, | |
216 | .syss_offs = 0x0408, | |
217 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
218 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
219 | SYSC_HAS_AUTOIDLE), | |
220 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
221 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
222 | .sysc_fields = &omap_hwmod_sysc_type1, | |
223 | }; | |
224 | ||
225 | static struct omap_hwmod_class usbotg_class = { | |
226 | .name = "usbotg", | |
227 | .sysc = &omap2430_usbhsotg_sysc, | |
228 | }; | |
229 | ||
230 | /* usb_otg_hs */ | |
44d02acf HH |
231 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { |
232 | .name = "usb_otg_hs", | |
44d02acf HH |
233 | .main_clk = "usbhs_ick", |
234 | .prcm = { | |
235 | .omap2 = { | |
236 | .prcm_reg_id = 1, | |
237 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
238 | .module_offs = CORE_MOD, | |
239 | .idlest_reg_id = 1, | |
240 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
241 | }, | |
242 | }, | |
44d02acf HH |
243 | .class = &usbotg_class, |
244 | /* | |
245 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
246 | * broken when autoidle is enabled | |
247 | * workaround is to disable the autoidle bit at module level. | |
248 | */ | |
249 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
250 | | HWMOD_SWSUP_MSTANDBY, | |
44d02acf HH |
251 | }; |
252 | ||
37801b3d C |
253 | /* |
254 | * 'mcbsp' class | |
255 | * multi channel buffered serial port controller | |
256 | */ | |
257 | ||
258 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
259 | .rev_offs = 0x007C, | |
260 | .sysc_offs = 0x008C, | |
261 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
262 | .sysc_fields = &omap_hwmod_sysc_type1, | |
263 | }; | |
264 | ||
265 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
266 | .name = "mcbsp", | |
267 | .sysc = &omap2430_mcbsp_sysc, | |
268 | .rev = MCBSP_CONFIG_TYPE2, | |
269 | }; | |
04aa67de | 270 | |
db382a86 PU |
271 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { |
272 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
273 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | |
274 | }; | |
275 | ||
37801b3d | 276 | /* mcbsp1 */ |
37801b3d C |
277 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
278 | .name = "mcbsp1", | |
279 | .class = &omap2430_mcbsp_hwmod_class, | |
37801b3d C |
280 | .main_clk = "mcbsp1_fck", |
281 | .prcm = { | |
282 | .omap2 = { | |
283 | .prcm_reg_id = 1, | |
284 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
285 | .module_offs = CORE_MOD, | |
286 | .idlest_reg_id = 1, | |
287 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
288 | }, | |
289 | }, | |
db382a86 PU |
290 | .opt_clks = mcbsp_opt_clks, |
291 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
292 | }; |
293 | ||
294 | /* mcbsp2 */ | |
37801b3d C |
295 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
296 | .name = "mcbsp2", | |
297 | .class = &omap2430_mcbsp_hwmod_class, | |
37801b3d C |
298 | .main_clk = "mcbsp2_fck", |
299 | .prcm = { | |
300 | .omap2 = { | |
301 | .prcm_reg_id = 1, | |
302 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
303 | .module_offs = CORE_MOD, | |
304 | .idlest_reg_id = 1, | |
305 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
306 | }, | |
307 | }, | |
db382a86 PU |
308 | .opt_clks = mcbsp_opt_clks, |
309 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
310 | }; |
311 | ||
312 | /* mcbsp3 */ | |
37801b3d C |
313 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
314 | .name = "mcbsp3", | |
315 | .class = &omap2430_mcbsp_hwmod_class, | |
37801b3d C |
316 | .main_clk = "mcbsp3_fck", |
317 | .prcm = { | |
318 | .omap2 = { | |
319 | .prcm_reg_id = 1, | |
320 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
321 | .module_offs = CORE_MOD, | |
322 | .idlest_reg_id = 2, | |
323 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
324 | }, | |
325 | }, | |
db382a86 PU |
326 | .opt_clks = mcbsp_opt_clks, |
327 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
328 | }; |
329 | ||
330 | /* mcbsp4 */ | |
37801b3d C |
331 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
332 | .name = "mcbsp4", | |
333 | .class = &omap2430_mcbsp_hwmod_class, | |
37801b3d C |
334 | .main_clk = "mcbsp4_fck", |
335 | .prcm = { | |
336 | .omap2 = { | |
337 | .prcm_reg_id = 1, | |
338 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
339 | .module_offs = CORE_MOD, | |
340 | .idlest_reg_id = 2, | |
341 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
342 | }, | |
343 | }, | |
db382a86 PU |
344 | .opt_clks = mcbsp_opt_clks, |
345 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
346 | }; |
347 | ||
348 | /* mcbsp5 */ | |
37801b3d C |
349 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
350 | .name = "mcbsp5", | |
351 | .class = &omap2430_mcbsp_hwmod_class, | |
37801b3d C |
352 | .main_clk = "mcbsp5_fck", |
353 | .prcm = { | |
354 | .omap2 = { | |
355 | .prcm_reg_id = 1, | |
356 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
357 | .module_offs = CORE_MOD, | |
358 | .idlest_reg_id = 2, | |
359 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
360 | }, | |
361 | }, | |
db382a86 PU |
362 | .opt_clks = mcbsp_opt_clks, |
363 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d | 364 | }; |
04aa67de | 365 | |
bce06f37 | 366 | /* MMC/SD/SDIO common */ |
bce06f37 PW |
367 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
368 | .rev_offs = 0x1fc, | |
369 | .sysc_offs = 0x10, | |
370 | .syss_offs = 0x14, | |
371 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
372 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
373 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
374 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
375 | .sysc_fields = &omap_hwmod_sysc_type1, | |
376 | }; | |
377 | ||
378 | static struct omap_hwmod_class omap2430_mmc_class = { | |
379 | .name = "mmc", | |
380 | .sysc = &omap2430_mmc_sysc, | |
381 | }; | |
382 | ||
383 | /* MMC/SD/SDIO1 */ | |
bce06f37 PW |
384 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { |
385 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
386 | }; | |
387 | ||
6ab8946f KK |
388 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
389 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
390 | }; | |
391 | ||
bce06f37 PW |
392 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
393 | .name = "mmc1", | |
394 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
bce06f37 PW |
395 | .opt_clks = omap2430_mmc1_opt_clks, |
396 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
397 | .main_clk = "mmchs1_fck", | |
398 | .prcm = { | |
399 | .omap2 = { | |
400 | .module_offs = CORE_MOD, | |
401 | .prcm_reg_id = 2, | |
402 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
403 | .idlest_reg_id = 2, | |
404 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
405 | }, | |
406 | }, | |
6ab8946f | 407 | .dev_attr = &mmc1_dev_attr, |
bce06f37 | 408 | .class = &omap2430_mmc_class, |
bce06f37 PW |
409 | }; |
410 | ||
411 | /* MMC/SD/SDIO2 */ | |
bce06f37 PW |
412 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { |
413 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
414 | }; | |
415 | ||
bce06f37 PW |
416 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
417 | .name = "mmc2", | |
418 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
bce06f37 PW |
419 | .opt_clks = omap2430_mmc2_opt_clks, |
420 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
421 | .main_clk = "mmchs2_fck", | |
422 | .prcm = { | |
423 | .omap2 = { | |
424 | .module_offs = CORE_MOD, | |
425 | .prcm_reg_id = 2, | |
426 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
427 | .idlest_reg_id = 2, | |
428 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
429 | }, | |
430 | }, | |
bce06f37 | 431 | .class = &omap2430_mmc_class, |
bce06f37 | 432 | }; |
04aa67de | 433 | |
f32bd778 PW |
434 | /* HDQ1W/1-wire */ |
435 | static struct omap_hwmod omap2430_hdq1w_hwmod = { | |
436 | .name = "hdq1w", | |
f32bd778 PW |
437 | .main_clk = "hdq_fck", |
438 | .prcm = { | |
439 | .omap2 = { | |
440 | .module_offs = CORE_MOD, | |
441 | .prcm_reg_id = 1, | |
442 | .module_bit = OMAP24XX_EN_HDQ_SHIFT, | |
443 | .idlest_reg_id = 1, | |
444 | .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, | |
445 | }, | |
446 | }, | |
447 | .class = &omap2_hdq1w_class, | |
448 | }; | |
449 | ||
844a3b63 PW |
450 | /* |
451 | * interfaces | |
452 | */ | |
453 | ||
454 | /* L3 -> L4_CORE interface */ | |
844a3b63 PW |
455 | /* l3_core -> usbhsotg interface */ |
456 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
457 | .master = &omap2430_usbhsotg_hwmod, | |
cb48427e | 458 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
459 | .clk = "core_l3_ck", |
460 | .user = OCP_USER_MPU, | |
461 | }; | |
462 | ||
463 | /* L4 CORE -> I2C1 interface */ | |
464 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
cb48427e | 465 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
466 | .slave = &omap2430_i2c1_hwmod, |
467 | .clk = "i2c1_ick", | |
844a3b63 PW |
468 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
469 | }; | |
470 | ||
471 | /* L4 CORE -> I2C2 interface */ | |
472 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
cb48427e | 473 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
474 | .slave = &omap2430_i2c2_hwmod, |
475 | .clk = "i2c2_ick", | |
844a3b63 PW |
476 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
477 | }; | |
478 | ||
844a3b63 PW |
479 | /* l4_core ->usbhsotg interface */ |
480 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
cb48427e | 481 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
482 | .slave = &omap2430_usbhsotg_hwmod, |
483 | .clk = "usb_l4_ick", | |
844a3b63 PW |
484 | .user = OCP_USER_MPU, |
485 | }; | |
486 | ||
487 | /* L4 CORE -> MMC1 interface */ | |
488 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { | |
cb48427e | 489 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
490 | .slave = &omap2430_mmc1_hwmod, |
491 | .clk = "mmchs1_ick", | |
844a3b63 PW |
492 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
493 | }; | |
494 | ||
495 | /* L4 CORE -> MMC2 interface */ | |
496 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { | |
cb48427e | 497 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
498 | .slave = &omap2430_mmc2_hwmod, |
499 | .clk = "mmchs2_ick", | |
844a3b63 PW |
500 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
501 | }; | |
502 | ||
844a3b63 PW |
503 | /* l4 core -> mcspi3 interface */ |
504 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
cb48427e | 505 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
506 | .slave = &omap2430_mcspi3_hwmod, |
507 | .clk = "mcspi3_ick", | |
844a3b63 PW |
508 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
509 | }; | |
510 | ||
511 | /* IVA2 <- L3 interface */ | |
512 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
cb48427e | 513 | .master = &omap2xxx_l3_main_hwmod, |
844a3b63 | 514 | .slave = &omap2430_iva_hwmod, |
3af35fbc | 515 | .clk = "core_l3_ck", |
844a3b63 PW |
516 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
517 | }; | |
518 | ||
844a3b63 PW |
519 | /* l4_wkup -> timer1 */ |
520 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
cb48427e PW |
521 | .master = &omap2xxx_l4_wkup_hwmod, |
522 | .slave = &omap2xxx_timer1_hwmod, | |
844a3b63 | 523 | .clk = "gpt1_ick", |
844a3b63 PW |
524 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
525 | }; | |
526 | ||
844a3b63 | 527 | /* l4_wkup -> wd_timer2 */ |
844a3b63 | 528 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { |
cb48427e PW |
529 | .master = &omap2xxx_l4_wkup_hwmod, |
530 | .slave = &omap2xxx_wd_timer2_hwmod, | |
844a3b63 | 531 | .clk = "mpu_wdt_ick", |
844a3b63 PW |
532 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
533 | }; | |
534 | ||
844a3b63 | 535 | /* l4_wkup -> gpio1 */ |
844a3b63 | 536 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { |
cb48427e PW |
537 | .master = &omap2xxx_l4_wkup_hwmod, |
538 | .slave = &omap2xxx_gpio1_hwmod, | |
844a3b63 | 539 | .clk = "gpios_ick", |
844a3b63 PW |
540 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
541 | }; | |
542 | ||
543 | /* l4_wkup -> gpio2 */ | |
844a3b63 | 544 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { |
cb48427e PW |
545 | .master = &omap2xxx_l4_wkup_hwmod, |
546 | .slave = &omap2xxx_gpio2_hwmod, | |
844a3b63 | 547 | .clk = "gpios_ick", |
844a3b63 PW |
548 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
549 | }; | |
550 | ||
551 | /* l4_wkup -> gpio3 */ | |
844a3b63 | 552 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { |
cb48427e PW |
553 | .master = &omap2xxx_l4_wkup_hwmod, |
554 | .slave = &omap2xxx_gpio3_hwmod, | |
844a3b63 | 555 | .clk = "gpios_ick", |
844a3b63 PW |
556 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
557 | }; | |
558 | ||
559 | /* l4_wkup -> gpio4 */ | |
844a3b63 | 560 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { |
cb48427e PW |
561 | .master = &omap2xxx_l4_wkup_hwmod, |
562 | .slave = &omap2xxx_gpio4_hwmod, | |
844a3b63 | 563 | .clk = "gpios_ick", |
844a3b63 PW |
564 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
565 | }; | |
566 | ||
567 | /* l4_core -> gpio5 */ | |
844a3b63 | 568 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { |
cb48427e | 569 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
570 | .slave = &omap2430_gpio5_hwmod, |
571 | .clk = "gpio5_ick", | |
844a3b63 PW |
572 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
573 | }; | |
574 | ||
575 | /* dma_system -> L3 */ | |
576 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
577 | .master = &omap2430_dma_system_hwmod, | |
cb48427e | 578 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
579 | .clk = "core_l3_ck", |
580 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
581 | }; | |
582 | ||
583 | /* l4_core -> dma_system */ | |
584 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
cb48427e | 585 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
586 | .slave = &omap2430_dma_system_hwmod, |
587 | .clk = "sdma_ick", | |
588 | .addr = omap2_dma_system_addrs, | |
589 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
590 | }; | |
591 | ||
592 | /* l4_core -> mailbox */ | |
593 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
cb48427e | 594 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 | 595 | .slave = &omap2430_mailbox_hwmod, |
844a3b63 PW |
596 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
597 | }; | |
598 | ||
599 | /* l4_core -> mcbsp1 */ | |
600 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
cb48427e | 601 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
602 | .slave = &omap2430_mcbsp1_hwmod, |
603 | .clk = "mcbsp1_ick", | |
844a3b63 PW |
604 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
605 | }; | |
606 | ||
607 | /* l4_core -> mcbsp2 */ | |
608 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
cb48427e | 609 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
610 | .slave = &omap2430_mcbsp2_hwmod, |
611 | .clk = "mcbsp2_ick", | |
844a3b63 PW |
612 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
613 | }; | |
614 | ||
844a3b63 PW |
615 | /* l4_core -> mcbsp3 */ |
616 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
cb48427e | 617 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
618 | .slave = &omap2430_mcbsp3_hwmod, |
619 | .clk = "mcbsp3_ick", | |
844a3b63 PW |
620 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
621 | }; | |
622 | ||
844a3b63 PW |
623 | /* l4_core -> mcbsp4 */ |
624 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
cb48427e | 625 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
626 | .slave = &omap2430_mcbsp4_hwmod, |
627 | .clk = "mcbsp4_ick", | |
844a3b63 PW |
628 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
629 | }; | |
630 | ||
844a3b63 PW |
631 | /* l4_core -> mcbsp5 */ |
632 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
cb48427e | 633 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
634 | .slave = &omap2430_mcbsp5_hwmod, |
635 | .clk = "mcbsp5_ick", | |
844a3b63 PW |
636 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
637 | }; | |
638 | ||
f32bd778 PW |
639 | /* l4_core -> hdq1w */ |
640 | static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { | |
641 | .master = &omap2xxx_l4_core_hwmod, | |
642 | .slave = &omap2430_hdq1w_hwmod, | |
643 | .clk = "hdq_ick", | |
f32bd778 PW |
644 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
645 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
646 | }; | |
647 | ||
c8d82ff6 | 648 | /* l4_wkup -> 32ksync_counter */ |
c8d82ff6 VH |
649 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { |
650 | .master = &omap2xxx_l4_wkup_hwmod, | |
651 | .slave = &omap2xxx_counter_32k_hwmod, | |
652 | .clk = "sync_32k_ick", | |
c8d82ff6 VH |
653 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
654 | }; | |
655 | ||
49484a60 AM |
656 | static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { |
657 | .master = &omap2xxx_l3_main_hwmod, | |
658 | .slave = &omap2xxx_gpmc_hwmod, | |
659 | .clk = "core_l3_ck", | |
49484a60 AM |
660 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
661 | }; | |
662 | ||
0a78c5c5 | 663 | static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
6a29755f PW |
664 | &omap2xxx_l3_main__l4_core, |
665 | &omap2xxx_mpu__l3_main, | |
666 | &omap2xxx_dss__l3, | |
0a78c5c5 PW |
667 | &omap2430_usbhsotg__l3, |
668 | &omap2430_l4_core__i2c1, | |
669 | &omap2430_l4_core__i2c2, | |
6a29755f | 670 | &omap2xxx_l4_core__l4_wkup, |
0a78c5c5 PW |
671 | &omap2_l4_core__uart1, |
672 | &omap2_l4_core__uart2, | |
673 | &omap2_l4_core__uart3, | |
674 | &omap2430_l4_core__usbhsotg, | |
675 | &omap2430_l4_core__mmc1, | |
676 | &omap2430_l4_core__mmc2, | |
6a29755f PW |
677 | &omap2xxx_l4_core__mcspi1, |
678 | &omap2xxx_l4_core__mcspi2, | |
0a78c5c5 PW |
679 | &omap2430_l4_core__mcspi3, |
680 | &omap2430_l3__iva, | |
681 | &omap2430_l4_wkup__timer1, | |
6a29755f PW |
682 | &omap2xxx_l4_core__timer2, |
683 | &omap2xxx_l4_core__timer3, | |
684 | &omap2xxx_l4_core__timer4, | |
685 | &omap2xxx_l4_core__timer5, | |
686 | &omap2xxx_l4_core__timer6, | |
687 | &omap2xxx_l4_core__timer7, | |
688 | &omap2xxx_l4_core__timer8, | |
689 | &omap2xxx_l4_core__timer9, | |
690 | &omap2xxx_l4_core__timer10, | |
691 | &omap2xxx_l4_core__timer11, | |
692 | &omap2xxx_l4_core__timer12, | |
0a78c5c5 | 693 | &omap2430_l4_wkup__wd_timer2, |
6a29755f PW |
694 | &omap2xxx_l4_core__dss, |
695 | &omap2xxx_l4_core__dss_dispc, | |
696 | &omap2xxx_l4_core__dss_rfbi, | |
697 | &omap2xxx_l4_core__dss_venc, | |
0a78c5c5 PW |
698 | &omap2430_l4_wkup__gpio1, |
699 | &omap2430_l4_wkup__gpio2, | |
700 | &omap2430_l4_wkup__gpio3, | |
701 | &omap2430_l4_wkup__gpio4, | |
702 | &omap2430_l4_core__gpio5, | |
703 | &omap2430_dma_system__l3, | |
704 | &omap2430_l4_core__dma_system, | |
705 | &omap2430_l4_core__mailbox, | |
706 | &omap2430_l4_core__mcbsp1, | |
707 | &omap2430_l4_core__mcbsp2, | |
708 | &omap2430_l4_core__mcbsp3, | |
709 | &omap2430_l4_core__mcbsp4, | |
710 | &omap2430_l4_core__mcbsp5, | |
f32bd778 | 711 | &omap2430_l4_core__hdq1w, |
e9b0a2fb | 712 | &omap2xxx_l4_core__rng, |
e569e994 | 713 | &omap2xxx_l4_core__sham, |
660ffd6b | 714 | &omap2xxx_l4_core__aes, |
c8d82ff6 | 715 | &omap2430_l4_wkup__counter_32k, |
49484a60 | 716 | &omap2430_l3__gpmc, |
02bfc030 PW |
717 | NULL, |
718 | }; | |
719 | ||
7359154e PW |
720 | int __init omap2430_hwmod_init(void) |
721 | { | |
9ebfd285 | 722 | omap_hwmod_init(); |
0a78c5c5 | 723 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
7359154e | 724 | } |