Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
7359154e | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
7f904c78 | 21 | #include <plat/mcspi.h> |
02bfc030 | 22 | |
43b40992 PW |
23 | #include "omap_hwmod_common_data.h" |
24 | ||
02bfc030 | 25 | #include "prm-regbits-24xx.h" |
165e2161 | 26 | #include "cm-regbits-24xx.h" |
ff2516fb | 27 | #include "wd_timer.h" |
02bfc030 | 28 | |
7359154e PW |
29 | /* |
30 | * OMAP2430 hardware module integration data | |
31 | * | |
32 | * ALl of the data in this section should be autogeneratable from the | |
33 | * TI hardware database or other technical documentation. Data that | |
34 | * is driver-specific or driver-kernel integration-specific belongs | |
35 | * elsewhere. | |
36 | */ | |
37 | ||
02bfc030 | 38 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 39 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 40 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 41 | static struct omap_hwmod omap2430_l4_core_hwmod; |
165e2161 | 42 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
43 | static struct omap_hwmod omap2430_gpio1_hwmod; |
44 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
45 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
46 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
47 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 48 | static struct omap_hwmod omap2430_dma_system_hwmod; |
7f904c78 C |
49 | static struct omap_hwmod omap2430_mcspi1_hwmod; |
50 | static struct omap_hwmod omap2430_mcspi2_hwmod; | |
51 | static struct omap_hwmod omap2430_mcspi3_hwmod; | |
02bfc030 PW |
52 | |
53 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
54 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
55 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
56 | .slave = &omap2430_l4_core_hwmod, |
57 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
58 | }; | |
59 | ||
60 | /* MPU -> L3 interface */ | |
4a7cf90a | 61 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 62 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 63 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
64 | .user = OCP_USER_MPU, |
65 | }; | |
66 | ||
67 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
68 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
69 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
70 | }; |
71 | ||
72 | /* Master interfaces on the L3 interconnect */ | |
4a7cf90a KH |
73 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
74 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
75 | }; |
76 | ||
77 | /* L3 */ | |
4a7cf90a | 78 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 79 | .name = "l3_main", |
43b40992 | 80 | .class = &l3_hwmod_class, |
4a7cf90a KH |
81 | .masters = omap2430_l3_main_masters, |
82 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
83 | .slaves = omap2430_l3_main_slaves, | |
84 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
85 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
86 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
87 | }; |
88 | ||
89 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
90 | static struct omap_hwmod omap2430_uart1_hwmod; |
91 | static struct omap_hwmod omap2430_uart2_hwmod; | |
92 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
93 | static struct omap_hwmod omap2430_i2c1_hwmod; |
94 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
95 | ||
96 | /* I2C IP block address space length (in bytes) */ | |
97 | #define OMAP2_I2C_AS_LEN 128 | |
98 | ||
99 | /* L4 CORE -> I2C1 interface */ | |
100 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | |
101 | { | |
102 | .pa_start = 0x48070000, | |
103 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
104 | .flags = ADDR_TYPE_RT, | |
105 | }, | |
106 | }; | |
107 | ||
108 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
109 | .master = &omap2430_l4_core_hwmod, | |
110 | .slave = &omap2430_i2c1_hwmod, | |
111 | .clk = "i2c1_ick", | |
112 | .addr = omap2430_i2c1_addr_space, | |
113 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | |
114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
115 | }; | |
116 | ||
117 | /* L4 CORE -> I2C2 interface */ | |
118 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | |
119 | { | |
120 | .pa_start = 0x48072000, | |
121 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
122 | .flags = ADDR_TYPE_RT, | |
123 | }, | |
124 | }; | |
125 | ||
126 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
127 | .master = &omap2430_l4_core_hwmod, | |
128 | .slave = &omap2430_i2c2_hwmod, | |
129 | .clk = "i2c2_ick", | |
130 | .addr = omap2430_i2c2_addr_space, | |
131 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | |
132 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
133 | }; | |
02bfc030 PW |
134 | |
135 | /* L4_CORE -> L4_WKUP interface */ | |
136 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
137 | .master = &omap2430_l4_core_hwmod, | |
138 | .slave = &omap2430_l4_wkup_hwmod, | |
139 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
140 | }; | |
141 | ||
046465b7 KH |
142 | /* L4 CORE -> UART1 interface */ |
143 | static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { | |
144 | { | |
145 | .pa_start = OMAP2_UART1_BASE, | |
146 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, | |
147 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
148 | }, | |
149 | }; | |
150 | ||
151 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
152 | .master = &omap2430_l4_core_hwmod, | |
153 | .slave = &omap2430_uart1_hwmod, | |
154 | .clk = "uart1_ick", | |
155 | .addr = omap2430_uart1_addr_space, | |
156 | .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), | |
157 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
158 | }; | |
159 | ||
160 | /* L4 CORE -> UART2 interface */ | |
161 | static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { | |
162 | { | |
163 | .pa_start = OMAP2_UART2_BASE, | |
164 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, | |
165 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
166 | }, | |
167 | }; | |
168 | ||
169 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
170 | .master = &omap2430_l4_core_hwmod, | |
171 | .slave = &omap2430_uart2_hwmod, | |
172 | .clk = "uart2_ick", | |
173 | .addr = omap2430_uart2_addr_space, | |
174 | .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), | |
175 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
176 | }; | |
177 | ||
178 | /* L4 PER -> UART3 interface */ | |
179 | static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { | |
180 | { | |
181 | .pa_start = OMAP2_UART3_BASE, | |
182 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, | |
183 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
184 | }, | |
185 | }; | |
186 | ||
187 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
188 | .master = &omap2430_l4_core_hwmod, | |
189 | .slave = &omap2430_uart3_hwmod, | |
190 | .clk = "uart3_ick", | |
191 | .addr = omap2430_uart3_addr_space, | |
192 | .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), | |
193 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
194 | }; | |
195 | ||
02bfc030 PW |
196 | /* Slave interfaces on the L4_CORE interconnect */ |
197 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 198 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
199 | }; |
200 | ||
201 | /* Master interfaces on the L4_CORE interconnect */ | |
202 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
203 | &omap2430_l4_core__l4_wkup, | |
204 | }; | |
205 | ||
206 | /* L4 CORE */ | |
207 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 208 | .name = "l4_core", |
43b40992 | 209 | .class = &l4_hwmod_class, |
02bfc030 PW |
210 | .masters = omap2430_l4_core_masters, |
211 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
212 | .slaves = omap2430_l4_core_slaves, | |
213 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
214 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
215 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
216 | }; |
217 | ||
218 | /* Slave interfaces on the L4_WKUP interconnect */ | |
219 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
220 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
221 | &omap2_l4_core__uart1, |
222 | &omap2_l4_core__uart2, | |
223 | &omap2_l4_core__uart3, | |
02bfc030 PW |
224 | }; |
225 | ||
226 | /* Master interfaces on the L4_WKUP interconnect */ | |
227 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
228 | }; | |
229 | ||
7f904c78 C |
230 | /* l4 core -> mcspi1 interface */ |
231 | static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { | |
232 | { | |
233 | .pa_start = 0x48098000, | |
234 | .pa_end = 0x480980ff, | |
235 | .flags = ADDR_TYPE_RT, | |
236 | }, | |
237 | }; | |
238 | ||
239 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { | |
240 | .master = &omap2430_l4_core_hwmod, | |
241 | .slave = &omap2430_mcspi1_hwmod, | |
242 | .clk = "mcspi1_ick", | |
243 | .addr = omap2430_mcspi1_addr_space, | |
244 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), | |
245 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
246 | }; | |
247 | ||
248 | /* l4 core -> mcspi2 interface */ | |
249 | static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { | |
250 | { | |
251 | .pa_start = 0x4809a000, | |
252 | .pa_end = 0x4809a0ff, | |
253 | .flags = ADDR_TYPE_RT, | |
254 | }, | |
255 | }; | |
256 | ||
257 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { | |
258 | .master = &omap2430_l4_core_hwmod, | |
259 | .slave = &omap2430_mcspi2_hwmod, | |
260 | .clk = "mcspi2_ick", | |
261 | .addr = omap2430_mcspi2_addr_space, | |
262 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), | |
263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
264 | }; | |
265 | ||
266 | /* l4 core -> mcspi3 interface */ | |
267 | static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { | |
268 | { | |
269 | .pa_start = 0x480b8000, | |
270 | .pa_end = 0x480b80ff, | |
271 | .flags = ADDR_TYPE_RT, | |
272 | }, | |
273 | }; | |
274 | ||
275 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
276 | .master = &omap2430_l4_core_hwmod, | |
277 | .slave = &omap2430_mcspi3_hwmod, | |
278 | .clk = "mcspi3_ick", | |
279 | .addr = omap2430_mcspi3_addr_space, | |
280 | .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), | |
281 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
282 | }; | |
283 | ||
02bfc030 PW |
284 | /* L4 WKUP */ |
285 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 286 | .name = "l4_wkup", |
43b40992 | 287 | .class = &l4_hwmod_class, |
02bfc030 PW |
288 | .masters = omap2430_l4_wkup_masters, |
289 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
290 | .slaves = omap2430_l4_wkup_slaves, | |
291 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
292 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
293 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
294 | }; |
295 | ||
296 | /* Master interfaces on the MPU device */ | |
297 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 298 | &omap2430_mpu__l3_main, |
02bfc030 PW |
299 | }; |
300 | ||
301 | /* MPU */ | |
302 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 303 | .name = "mpu", |
43b40992 | 304 | .class = &mpu_hwmod_class, |
50ebdac2 | 305 | .main_clk = "mpu_ck", |
02bfc030 PW |
306 | .masters = omap2430_mpu_masters, |
307 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
308 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
309 | }; | |
310 | ||
08072acf PW |
311 | /* |
312 | * IVA2_1 interface data | |
313 | */ | |
314 | ||
315 | /* IVA2 <- L3 interface */ | |
316 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
317 | .master = &omap2430_l3_main_hwmod, | |
318 | .slave = &omap2430_iva_hwmod, | |
319 | .clk = "dsp_fck", | |
320 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
321 | }; | |
322 | ||
323 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
324 | &omap2430_l3__iva, | |
325 | }; | |
326 | ||
327 | /* | |
328 | * IVA2 (IVA2) | |
329 | */ | |
330 | ||
331 | static struct omap_hwmod omap2430_iva_hwmod = { | |
332 | .name = "iva", | |
333 | .class = &iva_hwmod_class, | |
334 | .masters = omap2430_iva_masters, | |
335 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
336 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
337 | }; | |
338 | ||
165e2161 VC |
339 | /* l4_wkup -> wd_timer2 */ |
340 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
341 | { | |
342 | .pa_start = 0x49016000, | |
343 | .pa_end = 0x4901607f, | |
344 | .flags = ADDR_TYPE_RT | |
345 | }, | |
346 | }; | |
347 | ||
348 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
349 | .master = &omap2430_l4_wkup_hwmod, | |
350 | .slave = &omap2430_wd_timer2_hwmod, | |
351 | .clk = "mpu_wdt_ick", | |
352 | .addr = omap2430_wd_timer2_addrs, | |
353 | .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), | |
354 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
355 | }; | |
356 | ||
357 | /* | |
358 | * 'wd_timer' class | |
359 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
360 | * overflow condition | |
361 | */ | |
362 | ||
363 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
364 | .rev_offs = 0x0, | |
365 | .sysc_offs = 0x0010, | |
366 | .syss_offs = 0x0014, | |
367 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
368 | SYSC_HAS_AUTOIDLE), | |
369 | .sysc_fields = &omap_hwmod_sysc_type1, | |
370 | }; | |
371 | ||
372 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
ff2516fb PW |
373 | .name = "wd_timer", |
374 | .sysc = &omap2430_wd_timer_sysc, | |
375 | .pre_shutdown = &omap2_wd_timer_disable | |
165e2161 VC |
376 | }; |
377 | ||
378 | /* wd_timer2 */ | |
379 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
380 | &omap2430_l4_wkup__wd_timer2, | |
381 | }; | |
382 | ||
383 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
384 | .name = "wd_timer2", | |
385 | .class = &omap2430_wd_timer_hwmod_class, | |
386 | .main_clk = "mpu_wdt_fck", | |
387 | .prcm = { | |
388 | .omap2 = { | |
389 | .prcm_reg_id = 1, | |
390 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
391 | .module_offs = WKUP_MOD, | |
392 | .idlest_reg_id = 1, | |
393 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
394 | }, | |
395 | }, | |
396 | .slaves = omap2430_wd_timer2_slaves, | |
397 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
398 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
399 | }; | |
400 | ||
046465b7 KH |
401 | /* UART */ |
402 | ||
403 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
404 | .rev_offs = 0x50, | |
405 | .sysc_offs = 0x54, | |
406 | .syss_offs = 0x58, | |
407 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
408 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
409 | SYSC_HAS_AUTOIDLE), | |
410 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
411 | .sysc_fields = &omap_hwmod_sysc_type1, | |
412 | }; | |
413 | ||
414 | static struct omap_hwmod_class uart_class = { | |
415 | .name = "uart", | |
416 | .sysc = &uart_sysc, | |
417 | }; | |
418 | ||
419 | /* UART1 */ | |
420 | ||
421 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
422 | { .irq = INT_24XX_UART1_IRQ, }, | |
423 | }; | |
424 | ||
425 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
426 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
427 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
428 | }; | |
429 | ||
430 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { | |
431 | &omap2_l4_core__uart1, | |
432 | }; | |
433 | ||
434 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
435 | .name = "uart1", | |
436 | .mpu_irqs = uart1_mpu_irqs, | |
437 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
438 | .sdma_reqs = uart1_sdma_reqs, | |
439 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
440 | .main_clk = "uart1_fck", | |
441 | .prcm = { | |
442 | .omap2 = { | |
443 | .module_offs = CORE_MOD, | |
444 | .prcm_reg_id = 1, | |
445 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
446 | .idlest_reg_id = 1, | |
447 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
448 | }, | |
449 | }, | |
450 | .slaves = omap2430_uart1_slaves, | |
451 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
452 | .class = &uart_class, | |
453 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
454 | }; | |
455 | ||
456 | /* UART2 */ | |
457 | ||
458 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
459 | { .irq = INT_24XX_UART2_IRQ, }, | |
460 | }; | |
461 | ||
462 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
463 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
464 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
465 | }; | |
466 | ||
467 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { | |
468 | &omap2_l4_core__uart2, | |
469 | }; | |
470 | ||
471 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
472 | .name = "uart2", | |
473 | .mpu_irqs = uart2_mpu_irqs, | |
474 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
475 | .sdma_reqs = uart2_sdma_reqs, | |
476 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
477 | .main_clk = "uart2_fck", | |
478 | .prcm = { | |
479 | .omap2 = { | |
480 | .module_offs = CORE_MOD, | |
481 | .prcm_reg_id = 1, | |
482 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
483 | .idlest_reg_id = 1, | |
484 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
485 | }, | |
486 | }, | |
487 | .slaves = omap2430_uart2_slaves, | |
488 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
489 | .class = &uart_class, | |
490 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
491 | }; | |
492 | ||
493 | /* UART3 */ | |
494 | ||
495 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
496 | { .irq = INT_24XX_UART3_IRQ, }, | |
497 | }; | |
498 | ||
499 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
500 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
501 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
502 | }; | |
503 | ||
504 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { | |
505 | &omap2_l4_core__uart3, | |
506 | }; | |
507 | ||
508 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
509 | .name = "uart3", | |
510 | .mpu_irqs = uart3_mpu_irqs, | |
511 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
512 | .sdma_reqs = uart3_sdma_reqs, | |
513 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
514 | .main_clk = "uart3_fck", | |
515 | .prcm = { | |
516 | .omap2 = { | |
517 | .module_offs = CORE_MOD, | |
518 | .prcm_reg_id = 2, | |
519 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
520 | .idlest_reg_id = 2, | |
521 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
522 | }, | |
523 | }, | |
524 | .slaves = omap2430_uart3_slaves, | |
525 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
526 | .class = &uart_class, | |
527 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
528 | }; | |
529 | ||
2004290f PW |
530 | /* I2C common */ |
531 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
532 | .rev_offs = 0x00, | |
533 | .sysc_offs = 0x20, | |
534 | .syss_offs = 0x10, | |
535 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
536 | .sysc_fields = &omap_hwmod_sysc_type1, | |
537 | }; | |
538 | ||
539 | static struct omap_hwmod_class i2c_class = { | |
540 | .name = "i2c", | |
541 | .sysc = &i2c_sysc, | |
542 | }; | |
543 | ||
50ebb777 | 544 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f PW |
545 | .fifo_depth = 8, /* bytes */ |
546 | }; | |
547 | ||
50ebb777 BC |
548 | /* I2C1 */ |
549 | ||
2004290f PW |
550 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
551 | { .irq = INT_24XX_I2C1_IRQ, }, | |
552 | }; | |
553 | ||
554 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
555 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
556 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
557 | }; | |
558 | ||
559 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | |
560 | &omap2430_l4_core__i2c1, | |
561 | }; | |
562 | ||
563 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
564 | .name = "i2c1", | |
565 | .mpu_irqs = i2c1_mpu_irqs, | |
566 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
567 | .sdma_reqs = i2c1_sdma_reqs, | |
568 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
569 | .main_clk = "i2chs1_fck", | |
570 | .prcm = { | |
571 | .omap2 = { | |
572 | /* | |
573 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
574 | * I2CHS IP's do not follow the usual pattern. | |
575 | * prcm_reg_id alone cannot be used to program | |
576 | * the iclk and fclk. Needs to be handled using | |
577 | * additonal flags when clk handling is moved | |
578 | * to hwmod framework. | |
579 | */ | |
580 | .module_offs = CORE_MOD, | |
581 | .prcm_reg_id = 1, | |
582 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
583 | .idlest_reg_id = 1, | |
584 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
585 | }, | |
586 | }, | |
587 | .slaves = omap2430_i2c1_slaves, | |
588 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
589 | .class = &i2c_class, | |
50ebb777 | 590 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
591 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
592 | }; | |
593 | ||
594 | /* I2C2 */ | |
595 | ||
2004290f PW |
596 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
597 | { .irq = INT_24XX_I2C2_IRQ, }, | |
598 | }; | |
599 | ||
600 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
601 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
602 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
603 | }; | |
604 | ||
605 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | |
606 | &omap2430_l4_core__i2c2, | |
607 | }; | |
608 | ||
609 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
610 | .name = "i2c2", | |
611 | .mpu_irqs = i2c2_mpu_irqs, | |
612 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
613 | .sdma_reqs = i2c2_sdma_reqs, | |
614 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
615 | .main_clk = "i2chs2_fck", | |
616 | .prcm = { | |
617 | .omap2 = { | |
618 | .module_offs = CORE_MOD, | |
619 | .prcm_reg_id = 1, | |
620 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
621 | .idlest_reg_id = 1, | |
622 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
623 | }, | |
624 | }, | |
625 | .slaves = omap2430_i2c2_slaves, | |
626 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
627 | .class = &i2c_class, | |
50ebb777 | 628 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
629 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
630 | }; | |
631 | ||
aeac0e44 VC |
632 | /* l4_wkup -> gpio1 */ |
633 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
634 | { | |
635 | .pa_start = 0x4900C000, | |
636 | .pa_end = 0x4900C1ff, | |
637 | .flags = ADDR_TYPE_RT | |
638 | }, | |
639 | }; | |
640 | ||
641 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
642 | .master = &omap2430_l4_wkup_hwmod, | |
643 | .slave = &omap2430_gpio1_hwmod, | |
644 | .clk = "gpios_ick", | |
645 | .addr = omap2430_gpio1_addr_space, | |
646 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | |
647 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
648 | }; | |
649 | ||
650 | /* l4_wkup -> gpio2 */ | |
651 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
652 | { | |
653 | .pa_start = 0x4900E000, | |
654 | .pa_end = 0x4900E1ff, | |
655 | .flags = ADDR_TYPE_RT | |
656 | }, | |
657 | }; | |
658 | ||
659 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
660 | .master = &omap2430_l4_wkup_hwmod, | |
661 | .slave = &omap2430_gpio2_hwmod, | |
662 | .clk = "gpios_ick", | |
663 | .addr = omap2430_gpio2_addr_space, | |
664 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | |
665 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
666 | }; | |
667 | ||
668 | /* l4_wkup -> gpio3 */ | |
669 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
670 | { | |
671 | .pa_start = 0x49010000, | |
672 | .pa_end = 0x490101ff, | |
673 | .flags = ADDR_TYPE_RT | |
674 | }, | |
675 | }; | |
676 | ||
677 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
678 | .master = &omap2430_l4_wkup_hwmod, | |
679 | .slave = &omap2430_gpio3_hwmod, | |
680 | .clk = "gpios_ick", | |
681 | .addr = omap2430_gpio3_addr_space, | |
682 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | |
683 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
684 | }; | |
685 | ||
686 | /* l4_wkup -> gpio4 */ | |
687 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
688 | { | |
689 | .pa_start = 0x49012000, | |
690 | .pa_end = 0x490121ff, | |
691 | .flags = ADDR_TYPE_RT | |
692 | }, | |
693 | }; | |
694 | ||
695 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
696 | .master = &omap2430_l4_wkup_hwmod, | |
697 | .slave = &omap2430_gpio4_hwmod, | |
698 | .clk = "gpios_ick", | |
699 | .addr = omap2430_gpio4_addr_space, | |
700 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | |
701 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
702 | }; | |
703 | ||
704 | /* l4_core -> gpio5 */ | |
705 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
706 | { | |
707 | .pa_start = 0x480B6000, | |
708 | .pa_end = 0x480B61ff, | |
709 | .flags = ADDR_TYPE_RT | |
710 | }, | |
711 | }; | |
712 | ||
713 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
714 | .master = &omap2430_l4_core_hwmod, | |
715 | .slave = &omap2430_gpio5_hwmod, | |
716 | .clk = "gpio5_ick", | |
717 | .addr = omap2430_gpio5_addr_space, | |
718 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | |
719 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
720 | }; | |
721 | ||
722 | /* gpio dev_attr */ | |
723 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
724 | .bank_width = 32, | |
725 | .dbck_flag = false, | |
726 | }; | |
727 | ||
728 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
729 | .rev_offs = 0x0000, | |
730 | .sysc_offs = 0x0010, | |
731 | .syss_offs = 0x0014, | |
732 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
733 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
734 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
735 | .sysc_fields = &omap_hwmod_sysc_type1, | |
736 | }; | |
737 | ||
738 | /* | |
739 | * 'gpio' class | |
740 | * general purpose io module | |
741 | */ | |
742 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
743 | .name = "gpio", | |
744 | .sysc = &omap243x_gpio_sysc, | |
745 | .rev = 0, | |
746 | }; | |
747 | ||
748 | /* gpio1 */ | |
749 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | |
750 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
751 | }; | |
752 | ||
753 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | |
754 | &omap2430_l4_wkup__gpio1, | |
755 | }; | |
756 | ||
757 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
758 | .name = "gpio1", | |
759 | .mpu_irqs = omap243x_gpio1_irqs, | |
760 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | |
761 | .main_clk = "gpios_fck", | |
762 | .prcm = { | |
763 | .omap2 = { | |
764 | .prcm_reg_id = 1, | |
765 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
766 | .module_offs = WKUP_MOD, | |
767 | .idlest_reg_id = 1, | |
768 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
769 | }, | |
770 | }, | |
771 | .slaves = omap2430_gpio1_slaves, | |
772 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
773 | .class = &omap243x_gpio_hwmod_class, | |
774 | .dev_attr = &gpio_dev_attr, | |
775 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
776 | }; | |
777 | ||
778 | /* gpio2 */ | |
779 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | |
780 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
781 | }; | |
782 | ||
783 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | |
784 | &omap2430_l4_wkup__gpio2, | |
785 | }; | |
786 | ||
787 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
788 | .name = "gpio2", | |
789 | .mpu_irqs = omap243x_gpio2_irqs, | |
790 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | |
791 | .main_clk = "gpios_fck", | |
792 | .prcm = { | |
793 | .omap2 = { | |
794 | .prcm_reg_id = 1, | |
795 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
796 | .module_offs = WKUP_MOD, | |
797 | .idlest_reg_id = 1, | |
798 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
799 | }, | |
800 | }, | |
801 | .slaves = omap2430_gpio2_slaves, | |
802 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
803 | .class = &omap243x_gpio_hwmod_class, | |
804 | .dev_attr = &gpio_dev_attr, | |
805 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
806 | }; | |
807 | ||
808 | /* gpio3 */ | |
809 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | |
810 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
811 | }; | |
812 | ||
813 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | |
814 | &omap2430_l4_wkup__gpio3, | |
815 | }; | |
816 | ||
817 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
818 | .name = "gpio3", | |
819 | .mpu_irqs = omap243x_gpio3_irqs, | |
820 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | |
821 | .main_clk = "gpios_fck", | |
822 | .prcm = { | |
823 | .omap2 = { | |
824 | .prcm_reg_id = 1, | |
825 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
826 | .module_offs = WKUP_MOD, | |
827 | .idlest_reg_id = 1, | |
828 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
829 | }, | |
830 | }, | |
831 | .slaves = omap2430_gpio3_slaves, | |
832 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
833 | .class = &omap243x_gpio_hwmod_class, | |
834 | .dev_attr = &gpio_dev_attr, | |
835 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
836 | }; | |
837 | ||
838 | /* gpio4 */ | |
839 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | |
840 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
841 | }; | |
842 | ||
843 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | |
844 | &omap2430_l4_wkup__gpio4, | |
845 | }; | |
846 | ||
847 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
848 | .name = "gpio4", | |
849 | .mpu_irqs = omap243x_gpio4_irqs, | |
850 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | |
851 | .main_clk = "gpios_fck", | |
852 | .prcm = { | |
853 | .omap2 = { | |
854 | .prcm_reg_id = 1, | |
855 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
856 | .module_offs = WKUP_MOD, | |
857 | .idlest_reg_id = 1, | |
858 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
859 | }, | |
860 | }, | |
861 | .slaves = omap2430_gpio4_slaves, | |
862 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
863 | .class = &omap243x_gpio_hwmod_class, | |
864 | .dev_attr = &gpio_dev_attr, | |
865 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
866 | }; | |
867 | ||
868 | /* gpio5 */ | |
869 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
870 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
871 | }; | |
872 | ||
873 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
874 | &omap2430_l4_core__gpio5, | |
875 | }; | |
876 | ||
877 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
878 | .name = "gpio5", | |
879 | .mpu_irqs = omap243x_gpio5_irqs, | |
880 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | |
881 | .main_clk = "gpio5_fck", | |
882 | .prcm = { | |
883 | .omap2 = { | |
884 | .prcm_reg_id = 2, | |
885 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
886 | .module_offs = CORE_MOD, | |
887 | .idlest_reg_id = 2, | |
888 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
889 | }, | |
890 | }, | |
891 | .slaves = omap2430_gpio5_slaves, | |
892 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
893 | .class = &omap243x_gpio_hwmod_class, | |
894 | .dev_attr = &gpio_dev_attr, | |
895 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
896 | }; | |
897 | ||
82cbd1ae MK |
898 | /* dma_system */ |
899 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
900 | .rev_offs = 0x0000, | |
901 | .sysc_offs = 0x002c, | |
902 | .syss_offs = 0x0028, | |
903 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
904 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
905 | SYSC_HAS_AUTOIDLE), | |
906 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
907 | .sysc_fields = &omap_hwmod_sysc_type1, | |
908 | }; | |
909 | ||
910 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
911 | .name = "dma", | |
912 | .sysc = &omap2430_dma_sysc, | |
913 | }; | |
914 | ||
915 | /* dma attributes */ | |
916 | static struct omap_dma_dev_attr dma_dev_attr = { | |
917 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
918 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
919 | .lch_count = 32, | |
920 | }; | |
921 | ||
922 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | |
923 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
924 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
925 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
926 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
927 | }; | |
928 | ||
929 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | |
930 | { | |
931 | .pa_start = 0x48056000, | |
932 | .pa_end = 0x4a0560ff, | |
933 | .flags = ADDR_TYPE_RT | |
934 | }, | |
935 | }; | |
936 | ||
937 | /* dma_system -> L3 */ | |
938 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
939 | .master = &omap2430_dma_system_hwmod, | |
940 | .slave = &omap2430_l3_main_hwmod, | |
941 | .clk = "core_l3_ck", | |
942 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
943 | }; | |
944 | ||
945 | /* dma_system master ports */ | |
946 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
947 | &omap2430_dma_system__l3, | |
948 | }; | |
949 | ||
950 | /* l4_core -> dma_system */ | |
951 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
952 | .master = &omap2430_l4_core_hwmod, | |
953 | .slave = &omap2430_dma_system_hwmod, | |
954 | .clk = "sdma_ick", | |
955 | .addr = omap2430_dma_system_addrs, | |
956 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | |
957 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
958 | }; | |
959 | ||
960 | /* dma_system slave ports */ | |
961 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
962 | &omap2430_l4_core__dma_system, | |
963 | }; | |
964 | ||
965 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
966 | .name = "dma", | |
967 | .class = &omap2430_dma_hwmod_class, | |
968 | .mpu_irqs = omap2430_dma_system_irqs, | |
969 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | |
970 | .main_clk = "core_l3_ck", | |
971 | .slaves = omap2430_dma_system_slaves, | |
972 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
973 | .masters = omap2430_dma_system_masters, | |
974 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
975 | .dev_attr = &dma_dev_attr, | |
976 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
977 | .flags = HWMOD_NO_IDLEST, | |
978 | }; | |
979 | ||
7f904c78 C |
980 | /* |
981 | * 'mcspi' class | |
982 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
983 | * bus | |
984 | */ | |
985 | ||
986 | static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { | |
987 | .rev_offs = 0x0000, | |
988 | .sysc_offs = 0x0010, | |
989 | .syss_offs = 0x0014, | |
990 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
991 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
992 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
993 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
994 | .sysc_fields = &omap_hwmod_sysc_type1, | |
995 | }; | |
996 | ||
997 | static struct omap_hwmod_class omap2430_mcspi_class = { | |
998 | .name = "mcspi", | |
999 | .sysc = &omap2430_mcspi_sysc, | |
1000 | .rev = OMAP2_MCSPI_REV, | |
1001 | }; | |
1002 | ||
1003 | /* mcspi1 */ | |
1004 | static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { | |
1005 | { .irq = 65 }, | |
1006 | }; | |
1007 | ||
1008 | static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { | |
1009 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ | |
1010 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ | |
1011 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ | |
1012 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ | |
1013 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ | |
1014 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ | |
1015 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ | |
1016 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ | |
1017 | }; | |
1018 | ||
1019 | static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { | |
1020 | &omap2430_l4_core__mcspi1, | |
1021 | }; | |
1022 | ||
1023 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1024 | .num_chipselect = 4, | |
1025 | }; | |
1026 | ||
1027 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
1028 | .name = "mcspi1_hwmod", | |
1029 | .mpu_irqs = omap2430_mcspi1_mpu_irqs, | |
1030 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), | |
1031 | .sdma_reqs = omap2430_mcspi1_sdma_reqs, | |
1032 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), | |
1033 | .main_clk = "mcspi1_fck", | |
1034 | .prcm = { | |
1035 | .omap2 = { | |
1036 | .module_offs = CORE_MOD, | |
1037 | .prcm_reg_id = 1, | |
1038 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1039 | .idlest_reg_id = 1, | |
1040 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1041 | }, | |
1042 | }, | |
1043 | .slaves = omap2430_mcspi1_slaves, | |
1044 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), | |
1045 | .class = &omap2430_mcspi_class, | |
1046 | .dev_attr = &omap_mcspi1_dev_attr, | |
1047 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1048 | }; | |
1049 | ||
1050 | /* mcspi2 */ | |
1051 | static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { | |
1052 | { .irq = 66 }, | |
1053 | }; | |
1054 | ||
1055 | static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { | |
1056 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ | |
1057 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ | |
1058 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ | |
1059 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ | |
1060 | }; | |
1061 | ||
1062 | static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { | |
1063 | &omap2430_l4_core__mcspi2, | |
1064 | }; | |
1065 | ||
1066 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1067 | .num_chipselect = 2, | |
1068 | }; | |
1069 | ||
1070 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
1071 | .name = "mcspi2_hwmod", | |
1072 | .mpu_irqs = omap2430_mcspi2_mpu_irqs, | |
1073 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), | |
1074 | .sdma_reqs = omap2430_mcspi2_sdma_reqs, | |
1075 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), | |
1076 | .main_clk = "mcspi2_fck", | |
1077 | .prcm = { | |
1078 | .omap2 = { | |
1079 | .module_offs = CORE_MOD, | |
1080 | .prcm_reg_id = 1, | |
1081 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1082 | .idlest_reg_id = 1, | |
1083 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1084 | }, | |
1085 | }, | |
1086 | .slaves = omap2430_mcspi2_slaves, | |
1087 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), | |
1088 | .class = &omap2430_mcspi_class, | |
1089 | .dev_attr = &omap_mcspi2_dev_attr, | |
1090 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1091 | }; | |
1092 | ||
1093 | /* mcspi3 */ | |
1094 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
1095 | { .irq = 91 }, | |
1096 | }; | |
1097 | ||
1098 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
1099 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
1100 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
1101 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
1102 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
1103 | }; | |
1104 | ||
1105 | static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { | |
1106 | &omap2430_l4_core__mcspi3, | |
1107 | }; | |
1108 | ||
1109 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1110 | .num_chipselect = 2, | |
1111 | }; | |
1112 | ||
1113 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
1114 | .name = "mcspi3_hwmod", | |
1115 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, | |
1116 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), | |
1117 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, | |
1118 | .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), | |
1119 | .main_clk = "mcspi3_fck", | |
1120 | .prcm = { | |
1121 | .omap2 = { | |
1122 | .module_offs = CORE_MOD, | |
1123 | .prcm_reg_id = 2, | |
1124 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1125 | .idlest_reg_id = 2, | |
1126 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
1127 | }, | |
1128 | }, | |
1129 | .slaves = omap2430_mcspi3_slaves, | |
1130 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), | |
1131 | .class = &omap2430_mcspi_class, | |
1132 | .dev_attr = &omap_mcspi3_dev_attr, | |
1133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1134 | }; | |
1135 | ||
02bfc030 | 1136 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 1137 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
1138 | &omap2430_l4_core_hwmod, |
1139 | &omap2430_l4_wkup_hwmod, | |
1140 | &omap2430_mpu_hwmod, | |
08072acf | 1141 | &omap2430_iva_hwmod, |
165e2161 | 1142 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
1143 | &omap2430_uart1_hwmod, |
1144 | &omap2430_uart2_hwmod, | |
1145 | &omap2430_uart3_hwmod, | |
2004290f PW |
1146 | &omap2430_i2c1_hwmod, |
1147 | &omap2430_i2c2_hwmod, | |
aeac0e44 VC |
1148 | |
1149 | /* gpio class */ | |
1150 | &omap2430_gpio1_hwmod, | |
1151 | &omap2430_gpio2_hwmod, | |
1152 | &omap2430_gpio3_hwmod, | |
1153 | &omap2430_gpio4_hwmod, | |
1154 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
1155 | |
1156 | /* dma_system class*/ | |
1157 | &omap2430_dma_system_hwmod, | |
7f904c78 C |
1158 | |
1159 | /* mcspi class */ | |
1160 | &omap2430_mcspi1_hwmod, | |
1161 | &omap2430_mcspi2_hwmod, | |
1162 | &omap2430_mcspi3_hwmod, | |
02bfc030 PW |
1163 | NULL, |
1164 | }; | |
1165 | ||
7359154e PW |
1166 | int __init omap2430_hwmod_init(void) |
1167 | { | |
1168 | return omap_hwmod_init(omap2430_hwmods); | |
1169 | } |